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foss-fpga-tools
/
prjtrellis
/
e10b1cbd1670173183e7ff89fcfc0d753146c5d8
/
.
/
minitests
/
lut
/
lut.v
blob: 2c7266a907cf9fca0c86258c1d58d75c122f74fe [
file
]
module
top
(
input a
,
input b
,
input c
,
input d
,
output q
);
assign q
=
a
&
b
&
c
&
d
;
endmodule