Merge branch 'master' into facade

diff --git a/database b/database
index 2cf058e..1320be7 160000
--- a/database
+++ b/database

@@ -1 +1 @@
-Subproject commit 2cf058e7a3ba36134d21e34823e9b2ecaaceac2c
+Subproject commit 1320be79e0f1e526ea4f9d454a80745cb5639eec

diff --git a/examples/tinyfpga_ax/blinky_ext.lpf b/examples/tinyfpga_ax/blinky_ext.lpf
new file mode 100644
index 0000000..6bc4413
--- /dev/null
+++ b/examples/tinyfpga_ax/blinky_ext.lpf

@@ -0,0 +1,4 @@
+BLOCK RESETPATHS ;
+BLOCK ASYNCPATHS ;
+LOCATE COMP "pin1" SITE "13" ;
+LOCATE COMP "clk" SITE "21" ;

diff --git a/examples/tinyfpga_ax/blinky_ext.v b/examples/tinyfpga_ax/blinky_ext.v
new file mode 100644
index 0000000..b05e409
--- /dev/null
+++ b/examples/tinyfpga_ax/blinky_ext.v

@@ -0,0 +1,17 @@
+// Modified from:
+// https://github.com/tinyfpga/TinyFPGA-A-Series/tree/master/template_a2
+
+module TinyFPGA_A2 (
+  inout pin1,
+  input clk
+);
+
+  reg [23:0] led_timer;
+
+  always @(posedge clk) begin
+    led_timer <= led_timer + 1;
+  end
+
+  // left side of board
+  assign pin1 = led_timer[23];
+endmodule

diff --git a/libtrellis/src/Chip.cpp b/libtrellis/src/Chip.cpp
index 339da74..ce51a52 100644
--- a/libtrellis/src/Chip.cpp
+++ b/libtrellis/src/Chip.cpp

@@ -291,13 +291,19 @@
                 MachXO2Bels::add_lc(*rg, x, y, z);
 
         // PIO Bels
-        if (tile->info.type.find("PIC_L0") != string::npos || tile->info.type.find("PIC_LS0") != string::npos ||
-            tile->info.type.find("PIC_T") != string::npos ||
-            tile->info.type.find("PIC_R0") != string::npos || tile->info.type.find("PIC_RS0") != string::npos ||
-            tile->info.type.find("PIC_B") != string::npos)
+        // DUMMY and CIB tiles can have the below strings and can possibly
+        // have BELs. But they will not have PIO BELs.
+        if (tile->info.type.find("DUMMY") == string::npos && tile->info.type.find("CIB") == string::npos &&
+            (tile->info.type.find("PIC_L0") != string::npos || tile->info.type.find("PIC_T") != string::npos ||
+             tile->info.type.find("PIC_R0") != string::npos || tile->info.type.find("PIC_B") != string::npos))
             for (int z = 0; z < 4; z++)
                 MachXO2Bels::add_pio(*rg, x, y, z);
 
+        // Single I/O pair.
+        if (tile->info.type.find("PIC_LS0") != string::npos || tile->info.type.find("PIC_RS0") != string::npos)
+            for (int z = 0; z < 2; z++)
+                MachXO2Bels::add_pio(*rg, x, y, z);
+
         // DCC/DCM Bels
         if (tile->info.type.find("CENTER_EBR_CIB") != string::npos) {
           for (int z = 0; z < 8; z++)

diff --git a/minitests/reg/async_gsr.v b/minitests/reg/async_gsr.v
new file mode 100644
index 0000000..d0899e4
--- /dev/null
+++ b/minitests/reg/async_gsr.v

@@ -0,0 +1,8 @@
+module top(input clk, d, set, r, output reg q);
+    GSR gsr(.GSR(r));
+    always @(posedge clk or posedge set)
+           if (set)
+                q <= 1'b1;
+           else
+                q <= d;
+endmodule

diff --git a/minitests/reg/async_sr.v b/minitests/reg/async_sr.v
new file mode 100644
index 0000000..b56235f
--- /dev/null
+++ b/minitests/reg/async_sr.v

@@ -0,0 +1,9 @@
+module top(input clk, d, set, reset, cen, output reg q);
+    always @(posedge clk or posedge set or posedge reset)
+           if (set)
+              q <= 1'b1;
+           else if(reset)
+              q <= 1'b0;
+           else if(cen)
+                q <= d;
+endmodule

diff --git a/minitests/reg/lsr_over_ce.v b/minitests/reg/lsr_over_ce.v
new file mode 100644
index 0000000..5161010
--- /dev/null
+++ b/minitests/reg/lsr_over_ce.v

@@ -0,0 +1,8 @@
+module top(input clk, d, set, cen, output reg q);
+    always @(posedge clk)
+         if (set)
+            q <= 1'b1;
+         else
+             if (cen)
+                  q <= d;
+endmodule

diff --git a/tools/read_pinout.py b/tools/read_pinout.py
index 95096d0..199fdc7 100644
--- a/tools/read_pinout.py
+++ b/tools/read_pinout.py

@@ -33,7 +33,7 @@
     max_col = chip.get_max_col()
 
     if chip.info.family == "MachXO2":
-        # I/O Grouping
+        # I/O Grouping is present in MachXO2 pinouts but not ECP5.
         pkg_index_start = 8
     else:
         pkg_index_start = 7
@@ -69,9 +69,9 @@
                 else:
                     metadata[bel] = bank, function, dqs
                 for i in range(len(package_indicies)):
-                    if splitline[7+i] == "-":
+                    if splitline[pkg_index_start+i] == "-":
                         continue
-                    package_data[package_indicies[i]][splitline[7+i]] = bel
+                    package_data[package_indicies[i]][splitline[pkg_index_start+i]] = bel
     json_data = {"packages": {}, "pio_metadata": []}
     for pkg, pins in package_data.items():
         json_data["packages"][pkg] = {}