Sign in
foss-fpga-tools
/
prjtrellis
/
f1b1b355a988b78c746296e097691531d5baf554
/
.
/
minitests
/
wire
/
wire_pad.v
blob: 13bed6fab0596aab7678f5e2cb428863c496f1bd [
file
]
module
top
(
input a
,
output q
);
assign q
=
a
;
endmodule
