minitests/reg/plain.v - prjtrellis - Git at Google


            
            module top(input clk, input d, output reg q);

            
                always @(posedge clk)

            
                    q <= d;

            
            endmodule
	module top(input clk, input d, output reg q);
	always @(posedge clk)
	q <= d;
	endmodule