minitests: Add sv2v conversion to OpenTitan Signed-off-by: Tomasz Michalak <tmichalak@antmicro.com>
diff --git a/minitests/opentitan/src.yosys/Makefile b/minitests/opentitan/src.yosys/Makefile index 6776691..686de82 100644 --- a/minitests/opentitan/src.yosys/Makefile +++ b/minitests/opentitan/src.yosys/Makefile
@@ -1,2 +1,24 @@ -vivado: +ifeq (,$(shell which sv2v)) +$(error "No sv2v in $(PATH), you need to install it first") +endif + +SV_FILES=$(shell find ../src.vivado -name "*.sv") +V_FILES=$(foreach SV_FILE,$(SV_FILES),$(patsubst %.sv,%.v,$(notdir $(SV_FILE)))) + +all: yosys-vivado + +define sv2v_conv = +$(1): + sv2v.sh $(1) $(2) +endef + +$(foreach SV_FILE,$(SV_FILES),$(eval $(call sv2v_conv,$(patsubst %.sv,%.v,$(notdir $(SV_FILE))),$(SV_FILE)))) + +yosys-vivado: sv2v python3 runme.py + +sv2v: $(V_FILES) + @true + +clean: + rm -rf *.v build
diff --git a/minitests/opentitan/src.yosys/runme.py b/minitests/opentitan/src.yosys/runme.py index 2e3d964..cf86b20 100755 --- a/minitests/opentitan/src.yosys/runme.py +++ b/minitests/opentitan/src.yosys/runme.py
@@ -1,5 +1,6 @@ import edalize import os +import glob work_root = 'build' @@ -9,183 +10,24 @@ synth_tool = 'yosys' -srcs = [ - 'pins_if.v', - 'prim_generic_clock_gating.v', - 'prim_generic_clock_mux2.v', - 'prim_generic_flash.v', - 'prim_generic_pad_wrapper.v', - 'prim_generic_ram_1p.v', - 'prim_generic_ram_2p.v', - 'prim_xilinx_clock_gating.v', - 'prim_xilinx_clock_mux2.v', - 'prim_xilinx_pad_wrapper.v', - 'prim_xilinx_ram_2p.v', - 'ibex_alu.v', - 'ibex_compressed_decoder.v', - 'ibex_controller.v', - 'ibex_cs_registers.v', - 'ibex_decoder.v', - 'ibex_ex_block.v', - 'ibex_fetch_fifo.v', - 'ibex_id_stage.v', - 'ibex_if_stage.v', - 'ibex_load_store_unit.v', - 'ibex_multdiv_fast.v', - 'ibex_multdiv_slow.v', - 'ibex_prefetch_buffer.v', - 'ibex_pmp.v', - 'ibex_register_file_ff.v', - 'ibex_core.v', - 'prim_clock_gating.v', - 'prim_clock_mux2.v', - 'prim_diff_decode.v', - 'prim_pad_wrapper.v', - 'prim_ram_1p.v', - 'prim_ram_2p.v', - 'prim_clock_inverter.v', - 'prim_alert_receiver.v', - 'prim_alert_sender.v', - 'prim_arbiter_ppc.v', - 'prim_arbiter_tree.v', - 'prim_esc_receiver.v', - 'prim_esc_sender.v', - 'prim_sram_arbiter.v', - 'prim_fifo_async.v', - 'prim_fifo_sync.v', - 'prim_flop_2sync.v', - 'prim_lfsr.v', - 'prim_packer.v', - 'prim_pulse_sync.v', - 'prim_filter.v', - 'prim_filter_ctr.v', - 'prim_subreg.v', - 'prim_subreg_ext.v', - 'prim_intr_hw.v', - 'prim_secded_39_32_enc.v', - 'prim_secded_39_32_dec.v', - 'prim_ram_2p_adv.v', - 'prim_ram_2p_async_adv.v', - 'prim_flash.v', - 'alert_handler_reg_top.v', - 'pinmux_reg_top.v', - 'usb_fs_nb_in_pe.v', - 'usb_fs_nb_out_pe.v', - 'usb_fs_nb_pe.v', - 'usb_fs_rx.v', - 'usb_fs_tx.v', - 'usb_fs_tx_mux.v', - 'prim_generic_rom.v', - 'prim_xilinx_rom.v', - 'tlul_fifo_sync.v', - 'tlul_fifo_async.v', - 'tlul_assert.v', - 'tlul_err.v', - 'tlul_assert_multiple.v', - 'debug_rom.v', - 'dm_sba.v', - 'dm_csrs.v', - 'dm_mem.v', - 'dmi_cdc.v', - 'dmi_jtag.v', - 'dmi_jtag_tap.v', - 'prim_rom.v', - 'tlul_adapter_reg.v', - 'tlul_adapter_sram.v', - 'tlul_err_resp.v', - 'tlul_socket_1n.v', - 'tlul_socket_m1.v', - 'sram2tlul.v', - 'aes_reg_top.v', - 'aes_core.v', - 'aes_control.v', - 'aes_cipher_core.v', - 'aes_cipher_control.v', - 'aes_sub_bytes.v', - 'aes_sbox.v', - 'aes_sbox_lut.v', - 'aes_sbox_canright.v', - 'aes_shift_rows.v', - 'aes_mix_columns.v', - 'aes_mix_single_column.v', - 'aes_key_expand.v', - 'aes.v', - 'alert_handler_reg_wrap.v', - 'alert_handler_class.v', - 'alert_handler_ping_timer.v', - 'alert_handler_esc_timer.v', - 'alert_handler_accu.v', - 'alert_handler.v', - 'flash_ctrl_reg_top.v', - 'flash_ctrl.v', - 'flash_erase_ctrl.v', - 'flash_prog_ctrl.v', - 'flash_rd_ctrl.v', - 'flash_mp.v', - 'flash_phy.v', - 'gpio.v', - 'gpio_reg_top.v', - 'sha2.v', - 'sha2_pad.v', - 'hmac_reg_top.v', - 'hmac_core.v', - 'hmac.v', - 'nmi_gen_reg_top.v', - 'nmi_gen.v', - 'pinmux.v', - 'rv_core_ibex.v', - 'rv_dm.v', - 'tlul_adapter_host.v', - 'rv_plic_gateway.v', - 'rv_plic_target.v', - 'rv_timer_reg_top.v', - 'timer_core.v', - 'rv_timer.v', - 'spi_device_reg_top.v', - 'spi_fwm_rxf_ctrl.v', - 'spi_fwm_txf_ctrl.v', - 'spi_fwmode.v', - 'spi_device.v', - 'uart_reg_top.v', - 'uart_rx.v', - 'uart_tx.v', - 'uart_core.v', - 'uart.v', - 'usbdev_reg_top.v', - 'usbdev_usbif.v', - 'usbdev_flop_2syncpulse.v', - 'usbdev_linkstate.v', - 'usbdev_iomux.v', - 'usbdev.v', - 'xbar_main.v', - 'xbar_peri.v', - 'rv_plic_reg_top.v', - 'rv_plic.v', - 'padctl.v', - 'top_earlgrey.v', - 'clkgen_xilusp.v', - 'top_earlgrey_zcu104.v', -] +srcs = glob.glob("*.v") with open(post_imp_file, 'w') as f: f.write('write_checkpoint -force design.dcp') files = [ - {'name': os.path.realpath('lowrisc_systems_top_earlgrey_zcu104_0.1/data/pins_zcu104.xdc'), 'file_type': 'xdc'}, - {'name': os.path.realpath('lowrisc_prim_assert_0.1/rtl/prim_assert.sv'), 'file_type': 'systemVerilogSource', 'is_include_file': 'true'} + {'name': os.path.realpath('../src.vivado/lowrisc_systems_top_earlgrey_zcu104_0.1/data/pins_zcu104.xdc'), 'file_type': 'xdc'} ] parameters = { - 'ROM_INIT_FILE': {'datatype': 'str', 'paramtype': 'vlogdefine'}, - 'PRIM_DEFAULT_IMPL': {'datatype': 'str', 'paramtype': 'vlogdefine'}, } for src in srcs: - files.append({'name': os.path.realpath(src), 'file_type': 'systemVerilogSource'}) + files.append({'name': os.path.realpath(src), 'file_type': 'verilogSource'}) tool = 'vivado' -incdirs = [os.path.realpath('lowrisc_prim_assert_0.1/rtl')] +incdirs = {} edam = { 'files' : files, @@ -201,7 +43,5 @@ backend = edalize.get_edatool(tool)(edam=edam, work_root=work_root) -args = ['--ROM_INIT_FILE={}'.format(os.path.realpath('boot_rom_fpga_nexysvideo.vmem'))] - -backend.configure(args) +backend.configure("") backend.build()
diff --git a/minitests/opentitan/src.yosys/sv2v.sh b/minitests/opentitan/src.yosys/sv2v.sh new file mode 100755 index 0000000..e7b9a19 --- /dev/null +++ b/minitests/opentitan/src.yosys/sv2v.sh
@@ -0,0 +1,18 @@ +PRIM_ASSERT_PATH=$(find .. -name prim_assert.sv) +PRIM_ASSERT_DIR=$(dirname ${PRIM_ASSERT_PATH}) +PKG_FILES=$(find .. -name "*_pkg.sv") +if [ "$1" = "prim_generic_pad_wrapper.v" ]; then + sv2v --define=VERILATOR --define=SYNTHESIS --incdir=$PRIM_ASSERT_DIR $2 > $1 +elif [ "$1" = "prim_generic_rom.v" ] || [ "$1" = "prim_xilinx_rom.v" ]; then + sv2v --define=SYNTHESIS --define=ROM_INIT_FILE=../boot_rom_fpga_nexysvideo.vmem --incdir=$PRIM_ASSERT_DIR $2 > $1 +else + sv2v --define=SYNTHESIS --incdir=$PRIM_ASSERT_DIR $PRIM_ASSERT_PATH $PKG_FILES $2 > $1 +fi + + +if [ "$1" = "prim_lfsr.v" ]; then + sed -i 's/sv2v_cast_64\((["A-Za-z0-9_]*)\)/\1/g' $1 +fi +sed -i 's/parameter unsigned/parameter/g' $1 +sed -i 's/localparam unsigned/localparam/g' $1 +sed -i 's/if (.*) ;//g' $1
diff --git a/minitests/opentitan/sv2v.sh b/minitests/opentitan/sv2v.sh deleted file mode 100755 index e23dd3e..0000000 --- a/minitests/opentitan/sv2v.sh +++ /dev/null
@@ -1,30 +0,0 @@ -set -x - -TMPDIR=$(mktemp -d) - -find src.vivado -name "*.sv" -exec cp {} $TMPDIR \; - -pushd $TMPDIR - -for file in *.sv; do - module=`basename -s .sv $file` - echo $file - - if [ "$file" = "prim_generic_pad_wrapper.sv" ]; then - sv2v --define=VERILATOR --define=SYNTHESIS *_pkg.sv prim_assert.sv $file > ${module}.v - else - sv2v --define=SYNTHESIS *_pkg.sv prim_assert.sv $file > ${module}.v - fi - - - sed -i 's/parameter unsigned/parameter/g' ${module}.v - sed -i 's/localparam unsigned/localparam/g' ${module}.v -done - -rm -Rf *_pkg.v - -popd - -cp $TMPDIR/*.v src.yosys/. - -rm -rf $TMPDIR