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foss-fpga-tools
/
prjuray
/
refs/heads/add_tileinfo
/
.
/
fuzzers
/
001-part-yaml
/
top.v
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module
top
(
input clk
,
stb
,
di
,
output
do
);
reg do_reg
=
0
;
always
@(
posedge clk
)
begin
if
(
stb
)
begin
do_reg
=
di
;
end
end
assign
do
=
do_reg
;
endmodule