| source "$::env(XRAY_DIR)/utils/utils.tcl" | |
| proc run {} { | |
| create_project -force -part $::env(XRAY_PART) design design | |
| read_verilog top.v | |
| synth_design -top top | |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports clk] | |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports stb] | |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_02) IOSTANDARD LVCMOS33" [get_ports di] | |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_03) IOSTANDARD LVCMOS33" [get_ports do] | |
| set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] | |
| set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets clk_IBUF] | |
| place_design | |
| route_design | |
| write_checkpoint -force design.dcp | |
| write_bitstream -force design.bit | |
| } | |
| run |