| commit | b7c7f44d78d270885270b213c0b8d6f3964c621f | [log] [tgz] |
|---|---|---|
| author | Tim 'mithro' Ansell <tansell@google.com> | Wed May 27 12:18:33 2020 -0700 |
| committer | Tim 'mithro' Ansell <tansell@google.com> | Wed May 27 12:18:33 2020 -0700 |
| tree | db785c9459f3eca9f6501ec586d2b6c1788d84de | |
| parent | 796d74f6d9eac6320fba95420f0985297f92074f [diff] |
Latest version. Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
Project U-Ray is an attempt at documenting the bitstream format for the Xilinx Ultrascale and Ultrascale+ parts including all parts from the following lines;
It takes a lot of the learning from Project X-Ray and Project Trellis.
| Board | Maker | Price | Part |
|---|---|---|---|
| Ultra96-V2 Zynq UltraScale+ ZU3EG Development Board (ULTRA96-V2-G) | ??? | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD249 |
| Genesys ZU: Zynq Ultrascale+ MPSoC Development Board | Digilent | Xilinx Zynq UltraScale+ MPSoC ZU3EG | $USD1,149 |
We have a goal of initially targeting parts supported by WebPack so that anyone can contribute.
WebPack supports the following parts;
Zynq UltraScale+ MPSoC -- UltraScale+ MPSoC