| // Copyright 2020 Project U-Ray Authors |
| // |
| // Licensed under the Apache License, Version 2.0 (the "License"); |
| // you may not use this file except in compliance with the License. |
| // You may obtain a copy of the License at |
| // |
| // http://www.apache.org/licenses/LICENSE-2.0 |
| // |
| // Unless required by applicable law or agreed to in writing, software |
| // distributed under the License is distributed on an "AS IS" BASIS, |
| // WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| // See the License for the specific language governing permissions and |
| // limitations under the License. |
| |
| set run $::argv |
| create_project -force -part xczu7ev-ffvf1517-2-e design${run} design${run} |
| |
| |
| link_design |
| create_cell -reference LUT6 "misc_lut" |
| place_design |
| route_design |
| |
| remove_net xiphy_* |
| remove_cell xiphy_* |
| |
| foreach tile [get_tiles -filter {TILE_TYPE == RCLK_RCLK_XIPHY_INNER_FT}] { |
| set i 0 |
| foreach pip [get_pips -uphill -of_objects [get_wires "$tile/CLK_TO_XIPHY_BYTES_TOP0" -of_objects $tile]] { |
| set drv_node [get_nodes -uphill -of_objects $pip] |
| puts $drv_node |
| set pins [get_site_pins -of_objects [get_nodes -uphill -of_objects $drv_node] "BUFCE_ROW*"] |
| if {[llength $pins] != 1} { |
| continue |
| } |
| create_net "xiphy_${tile}_clk${i}" |
| set net [get_nets "xiphy_${tile}_clk${i}"] |
| create_cell -reference BUFCE_ROW "xiphy_${tile}_clk${i}_buf" |
| set site [get_sites -of_objects [lindex $pins 0]] |
| place_cell "xiphy_${tile}_clk${i}_buf" "${site}/BUFCE" |
| connect_net -net $net -objects [get_pins "xiphy_${tile}_clk${i}_buf/O"] |
| incr i |
| } |
| foreach sink_node [get_nodes -downhill -of_objects [get_nodes "$tile/CLK_HDISTR_ONE0"] "*CLK_TO_XIPHY*"] { |
| puts $sink_node |
| foreach pin [get_site_pins -of_objects [get_nodes -downhill -of_objects $sink_node] "BITSLICE_RX_TX*/*TX_OCLK"] { |
| set site [get_sites -of_objects $pin] |
| if {[llength [get_cells -of_objects $site]] > 0 } { |
| continue |
| } |
| create_cell -reference OSERDESE3 "xiphy_sink_${site}" |
| place_cell "xiphy_sink_${site}" "${site}/OSERDES" |
| while {1} { |
| set net_idx [expr int(rand() * $i)] |
| if {[lsearch [get_nets -of_objects [get_tiles -of_objects $site]] "xiphy_${tile}_clk${net_idx}"] == -1} { |
| break |
| } |
| } |
| set net [get_nets "xiphy_${tile}_clk${net_idx}"] |
| connect_net -net $net -objects [get_pins "xiphy_sink_${site}/CLK"] |
| break |
| } |
| } |
| } |
| |
| set_property SEVERITY Warning [get_drc_checks] |
| route_design |
| set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] |
| write_checkpoint -force ../specimen_clk/xclkroute_a${run}.dcp |
| write_edif -force ../specimen_clk/xclkroute_a${run}.edf |
| write_bitstream -force ../specimen_clk/xclkroute_a${run}.bit |
| |
