minitests/litex/zephyr/zcu104/src/top.v

//--------------------------------------------------------------------------------
// Auto-generated by Migen (d11565a) & LiteX (9521f2ff) on 2020-02-26 09:26:03
//--------------------------------------------------------------------------------
module top(
	input serial_cts,
	input serial_rts,
	output reg serial_tx,
	input serial_rx,
	(* dont_touch = "true" *)	input clk125_p,
	input clk125_n
);

reg soccontroller_reset_storage = 1'd0;
reg soccontroller_reset_re = 1'd0;
reg [31:0] soccontroller_scratch_storage = 32'd305419896;
reg soccontroller_scratch_re = 1'd0;
wire [31:0] soccontroller_bus_errors_status;
wire soccontroller_bus_errors_we;
wire soccontroller_reset;
wire soccontroller_bus_error;
reg [31:0] soccontroller_bus_errors = 32'd0;
wire cpu_reset;
wire [29:0] cpu_ibus_adr;
wire [31:0] cpu_ibus_dat_w;
wire [31:0] cpu_ibus_dat_r;
wire [3:0] cpu_ibus_sel;
wire cpu_ibus_cyc;
wire cpu_ibus_stb;
wire cpu_ibus_ack;
wire cpu_ibus_we;
wire [2:0] cpu_ibus_cti;
wire [1:0] cpu_ibus_bte;
wire cpu_ibus_err;
wire [29:0] cpu_dbus_adr;
wire [31:0] cpu_dbus_dat_w;
wire [31:0] cpu_dbus_dat_r;
wire [3:0] cpu_dbus_sel;
wire cpu_dbus_cyc;
wire cpu_dbus_stb;
wire cpu_dbus_ack;
wire cpu_dbus_we;
wire [2:0] cpu_dbus_cti;
wire [1:0] cpu_dbus_bte;
wire cpu_dbus_err;
reg [31:0] cpu_interrupt = 32'd0;
reg [31:0] vexriscv = 32'd0;
wire [29:0] basesoc_ram_bus_adr;
wire [31:0] basesoc_ram_bus_dat_w;
wire [31:0] basesoc_ram_bus_dat_r;
wire [3:0] basesoc_ram_bus_sel;
wire basesoc_ram_bus_cyc;
wire basesoc_ram_bus_stb;
reg basesoc_ram_bus_ack = 1'd0;
wire basesoc_ram_bus_we;
wire [2:0] basesoc_ram_bus_cti;
wire [1:0] basesoc_ram_bus_bte;
reg basesoc_ram_bus_err = 1'd0;
wire [12:0] basesoc_adr;
wire [31:0] basesoc_dat_r;
wire [29:0] interface0_ram_bus_adr;
wire [31:0] interface0_ram_bus_dat_w;
wire [31:0] interface0_ram_bus_dat_r;
wire [3:0] interface0_ram_bus_sel;
wire interface0_ram_bus_cyc;
wire interface0_ram_bus_stb;
reg interface0_ram_bus_ack = 1'd0;
wire interface0_ram_bus_we;
wire [2:0] interface0_ram_bus_cti;
wire [1:0] interface0_ram_bus_bte;
reg interface0_ram_bus_err = 1'd0;
wire [9:0] sram0_adr;
wire [31:0] sram0_dat_r;
reg [3:0] sram0_we = 4'd0;
wire [31:0] sram0_dat_w;
wire [29:0] interface1_ram_bus_adr;
wire [31:0] interface1_ram_bus_dat_w;
wire [31:0] interface1_ram_bus_dat_r;
wire [3:0] interface1_ram_bus_sel;
wire interface1_ram_bus_cyc;
wire interface1_ram_bus_stb;
reg interface1_ram_bus_ack = 1'd0;
wire interface1_ram_bus_we;
wire [2:0] interface1_ram_bus_cti;
wire [1:0] interface1_ram_bus_bte;
reg interface1_ram_bus_err = 1'd0;
wire [14:0] sram1_adr;
wire [31:0] sram1_dat_r;
reg [3:0] sram1_we = 4'd0;
wire [31:0] sram1_dat_w;
reg [31:0] storage = 32'd3958241;
reg re = 1'd0;
wire sink_valid;
reg sink_ready = 1'd0;
wire sink_first;
wire sink_last;
wire [7:0] sink_payload_data;
reg uart_clk_txen = 1'd0;
reg [31:0] phase_accumulator_tx = 32'd0;
reg [7:0] tx_reg = 8'd0;
reg [3:0] tx_bitcount = 4'd0;
reg tx_busy = 1'd0;
reg source_valid = 1'd0;
wire source_ready;
reg source_first = 1'd0;
reg source_last = 1'd0;
reg [7:0] source_payload_data = 8'd0;
reg uart_clk_rxen = 1'd0;
reg [31:0] phase_accumulator_rx = 32'd0;
wire rx;
reg rx_r = 1'd0;
reg [7:0] rx_reg = 8'd0;
reg [3:0] rx_bitcount = 4'd0;
reg rx_busy = 1'd0;
wire uart_rxtx_re;
wire [7:0] uart_rxtx_r;
wire uart_rxtx_we;
wire [7:0] uart_rxtx_w;
wire uart_txfull_status;
wire uart_txfull_we;
wire uart_rxempty_status;
wire uart_rxempty_we;
wire uart_irq;
wire uart_tx_status;
reg uart_tx_pending = 1'd0;
wire uart_tx_trigger;
reg uart_tx_clear = 1'd0;
reg uart_tx_old_trigger = 1'd0;
wire uart_rx_status;
reg uart_rx_pending = 1'd0;
wire uart_rx_trigger;
reg uart_rx_clear = 1'd0;
reg uart_rx_old_trigger = 1'd0;
wire uart_eventmanager_status_re;
wire [1:0] uart_eventmanager_status_r;
wire uart_eventmanager_status_we;
reg [1:0] uart_eventmanager_status_w = 2'd0;
wire uart_eventmanager_pending_re;
wire [1:0] uart_eventmanager_pending_r;
wire uart_eventmanager_pending_we;
reg [1:0] uart_eventmanager_pending_w = 2'd0;
reg [1:0] uart_eventmanager_storage = 2'd0;
reg uart_eventmanager_re = 1'd0;
wire uart_uart_sink_valid;
wire uart_uart_sink_ready;
wire uart_uart_sink_first;
wire uart_uart_sink_last;
wire [7:0] uart_uart_sink_payload_data;
wire uart_uart_source_valid;
wire uart_uart_source_ready;
wire uart_uart_source_first;
wire uart_uart_source_last;
wire [7:0] uart_uart_source_payload_data;
wire uart_tx_fifo_sink_valid;
wire uart_tx_fifo_sink_ready;
reg uart_tx_fifo_sink_first = 1'd0;
reg uart_tx_fifo_sink_last = 1'd0;
wire [7:0] uart_tx_fifo_sink_payload_data;
wire uart_tx_fifo_source_valid;
wire uart_tx_fifo_source_ready;
wire uart_tx_fifo_source_first;
wire uart_tx_fifo_source_last;
wire [7:0] uart_tx_fifo_source_payload_data;
wire uart_tx_fifo_re;
reg uart_tx_fifo_readable = 1'd0;
wire uart_tx_fifo_syncfifo_we;
wire uart_tx_fifo_syncfifo_writable;
wire uart_tx_fifo_syncfifo_re;
wire uart_tx_fifo_syncfifo_readable;
wire [9:0] uart_tx_fifo_syncfifo_din;
wire [9:0] uart_tx_fifo_syncfifo_dout;
reg [4:0] uart_tx_fifo_level0 = 5'd0;
reg uart_tx_fifo_replace = 1'd0;
reg [3:0] uart_tx_fifo_produce = 4'd0;
reg [3:0] uart_tx_fifo_consume = 4'd0;
reg [3:0] uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_tx_fifo_wrport_dat_r;
wire uart_tx_fifo_wrport_we;
wire [9:0] uart_tx_fifo_wrport_dat_w;
wire uart_tx_fifo_do_read;
wire [3:0] uart_tx_fifo_rdport_adr;
wire [9:0] uart_tx_fifo_rdport_dat_r;
wire uart_tx_fifo_rdport_re;
wire [4:0] uart_tx_fifo_level1;
wire [7:0] uart_tx_fifo_fifo_in_payload_data;
wire uart_tx_fifo_fifo_in_first;
wire uart_tx_fifo_fifo_in_last;
wire [7:0] uart_tx_fifo_fifo_out_payload_data;
wire uart_tx_fifo_fifo_out_first;
wire uart_tx_fifo_fifo_out_last;
wire uart_rx_fifo_sink_valid;
wire uart_rx_fifo_sink_ready;
wire uart_rx_fifo_sink_first;
wire uart_rx_fifo_sink_last;
wire [7:0] uart_rx_fifo_sink_payload_data;
wire uart_rx_fifo_source_valid;
wire uart_rx_fifo_source_ready;
wire uart_rx_fifo_source_first;
wire uart_rx_fifo_source_last;
wire [7:0] uart_rx_fifo_source_payload_data;
wire uart_rx_fifo_re;
reg uart_rx_fifo_readable = 1'd0;
wire uart_rx_fifo_syncfifo_we;
wire uart_rx_fifo_syncfifo_writable;
wire uart_rx_fifo_syncfifo_re;
wire uart_rx_fifo_syncfifo_readable;
wire [9:0] uart_rx_fifo_syncfifo_din;
wire [9:0] uart_rx_fifo_syncfifo_dout;
reg [4:0] uart_rx_fifo_level0 = 5'd0;
reg uart_rx_fifo_replace = 1'd0;
reg [3:0] uart_rx_fifo_produce = 4'd0;
reg [3:0] uart_rx_fifo_consume = 4'd0;
reg [3:0] uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_rx_fifo_wrport_dat_r;
wire uart_rx_fifo_wrport_we;
wire [9:0] uart_rx_fifo_wrport_dat_w;
wire uart_rx_fifo_do_read;
wire [3:0] uart_rx_fifo_rdport_adr;
wire [9:0] uart_rx_fifo_rdport_dat_r;
wire uart_rx_fifo_rdport_re;
wire [4:0] uart_rx_fifo_level1;
wire [7:0] uart_rx_fifo_fifo_in_payload_data;
wire uart_rx_fifo_fifo_in_first;
wire uart_rx_fifo_fifo_in_last;
wire [7:0] uart_rx_fifo_fifo_out_payload_data;
wire uart_rx_fifo_fifo_out_first;
wire uart_rx_fifo_fifo_out_last;
reg uart_reset = 1'd0;
reg [31:0] timer_load_storage = 32'd0;
reg timer_load_re = 1'd0;
reg [31:0] timer_reload_storage = 32'd0;
reg timer_reload_re = 1'd0;
reg timer_en_storage = 1'd0;
reg timer_en_re = 1'd0;
reg timer_update_value_storage = 1'd0;
reg timer_update_value_re = 1'd0;
reg [31:0] timer_value_status = 32'd0;
wire timer_value_we;
wire timer_irq;
wire timer_zero_status;
reg timer_zero_pending = 1'd0;
wire timer_zero_trigger;
reg timer_zero_clear = 1'd0;
reg timer_zero_old_trigger = 1'd0;
wire timer_eventmanager_status_re;
wire timer_eventmanager_status_r;
wire timer_eventmanager_status_we;
wire timer_eventmanager_status_w;
wire timer_eventmanager_pending_re;
wire timer_eventmanager_pending_r;
wire timer_eventmanager_pending_we;
wire timer_eventmanager_pending_w;
reg timer_eventmanager_storage = 1'd0;
reg timer_eventmanager_re = 1'd0;
reg [31:0] timer_value = 32'd0;
reg [13:0] interface_adr = 14'd0;
reg interface_we = 1'd0;
wire [7:0] interface_dat_w;
wire [7:0] interface_dat_r;
wire [29:0] bus_wishbone_adr;
wire [31:0] bus_wishbone_dat_w;
wire [31:0] bus_wishbone_dat_r;
wire [3:0] bus_wishbone_sel;
wire bus_wishbone_cyc;
wire bus_wishbone_stb;
reg bus_wishbone_ack = 1'd0;
wire bus_wishbone_we;
wire [2:0] bus_wishbone_cti;
wire [1:0] bus_wishbone_bte;
reg bus_wishbone_err = 1'd0;
wire sys_clk;
reg sys_rst = 1'd1;
wire sys4x_clk;
wire pll4x_clk;
wire clk500_clk;
wire clk500_rst;
wire ic_clk;
wire ic_rst;
reg reset = 1'd0;
wire locked;
wire clkin;
wire clkout0;
wire clkout1;
wire clkout_buf;
reg [5:0] ic_reset_counter = 6'd63;
reg ic_reset = 1'd1;
wire ic_rdy;
reg [5:0] ic_rdy_counter = 6'd63;
reg state = 1'd0;
reg next_state = 1'd0;
wire mmcm_fb;
wire [29:0] shared_adr;
wire [31:0] shared_dat_w;
reg [31:0] shared_dat_r = 32'd0;
wire [3:0] shared_sel;
wire shared_cyc;
wire shared_stb;
reg shared_ack = 1'd0;
wire shared_we;
wire [2:0] shared_cti;
wire [1:0] shared_bte;
wire shared_err;
wire [1:0] request;
reg grant = 1'd0;
reg [3:0] slave_sel = 4'd0;
reg [3:0] slave_sel_r = 4'd0;
reg error = 1'd0;
wire wait_1;
wire done;
reg [19:0] count = 20'd1000000;
wire [13:0] interface0_bank_bus_adr;
wire interface0_bank_bus_we;
wire [7:0] interface0_bank_bus_dat_w;
reg [7:0] interface0_bank_bus_dat_r = 8'd0;
wire csrbank0_reset0_re;
wire csrbank0_reset0_r;
wire csrbank0_reset0_we;
wire csrbank0_reset0_w;
wire csrbank0_scratch3_re;
wire [7:0] csrbank0_scratch3_r;
wire csrbank0_scratch3_we;
wire [7:0] csrbank0_scratch3_w;
wire csrbank0_scratch2_re;
wire [7:0] csrbank0_scratch2_r;
wire csrbank0_scratch2_we;
wire [7:0] csrbank0_scratch2_w;
wire csrbank0_scratch1_re;
wire [7:0] csrbank0_scratch1_r;
wire csrbank0_scratch1_we;
wire [7:0] csrbank0_scratch1_w;
wire csrbank0_scratch0_re;
wire [7:0] csrbank0_scratch0_r;
wire csrbank0_scratch0_we;
wire [7:0] csrbank0_scratch0_w;
wire csrbank0_bus_errors3_re;
wire [7:0] csrbank0_bus_errors3_r;
wire csrbank0_bus_errors3_we;
wire [7:0] csrbank0_bus_errors3_w;
wire csrbank0_bus_errors2_re;
wire [7:0] csrbank0_bus_errors2_r;
wire csrbank0_bus_errors2_we;
wire [7:0] csrbank0_bus_errors2_w;
wire csrbank0_bus_errors1_re;
wire [7:0] csrbank0_bus_errors1_r;
wire csrbank0_bus_errors1_we;
wire [7:0] csrbank0_bus_errors1_w;
wire csrbank0_bus_errors0_re;
wire [7:0] csrbank0_bus_errors0_r;
wire csrbank0_bus_errors0_we;
wire [7:0] csrbank0_bus_errors0_w;
wire csrbank0_sel;
wire [13:0] interface1_bank_bus_adr;
wire interface1_bank_bus_we;
wire [7:0] interface1_bank_bus_dat_w;
reg [7:0] interface1_bank_bus_dat_r = 8'd0;
wire csrbank1_load3_re;
wire [7:0] csrbank1_load3_r;
wire csrbank1_load3_we;
wire [7:0] csrbank1_load3_w;
wire csrbank1_load2_re;
wire [7:0] csrbank1_load2_r;
wire csrbank1_load2_we;
wire [7:0] csrbank1_load2_w;
wire csrbank1_load1_re;
wire [7:0] csrbank1_load1_r;
wire csrbank1_load1_we;
wire [7:0] csrbank1_load1_w;
wire csrbank1_load0_re;
wire [7:0] csrbank1_load0_r;
wire csrbank1_load0_we;
wire [7:0] csrbank1_load0_w;
wire csrbank1_reload3_re;
wire [7:0] csrbank1_reload3_r;
wire csrbank1_reload3_we;
wire [7:0] csrbank1_reload3_w;
wire csrbank1_reload2_re;
wire [7:0] csrbank1_reload2_r;
wire csrbank1_reload2_we;
wire [7:0] csrbank1_reload2_w;
wire csrbank1_reload1_re;
wire [7:0] csrbank1_reload1_r;
wire csrbank1_reload1_we;
wire [7:0] csrbank1_reload1_w;
wire csrbank1_reload0_re;
wire [7:0] csrbank1_reload0_r;
wire csrbank1_reload0_we;
wire [7:0] csrbank1_reload0_w;
wire csrbank1_en0_re;
wire csrbank1_en0_r;
wire csrbank1_en0_we;
wire csrbank1_en0_w;
wire csrbank1_update_value0_re;
wire csrbank1_update_value0_r;
wire csrbank1_update_value0_we;
wire csrbank1_update_value0_w;
wire csrbank1_value3_re;
wire [7:0] csrbank1_value3_r;
wire csrbank1_value3_we;
wire [7:0] csrbank1_value3_w;
wire csrbank1_value2_re;
wire [7:0] csrbank1_value2_r;
wire csrbank1_value2_we;
wire [7:0] csrbank1_value2_w;
wire csrbank1_value1_re;
wire [7:0] csrbank1_value1_r;
wire csrbank1_value1_we;
wire [7:0] csrbank1_value1_w;
wire csrbank1_value0_re;
wire [7:0] csrbank1_value0_r;
wire csrbank1_value0_we;
wire [7:0] csrbank1_value0_w;
wire csrbank1_ev_enable0_re;
wire csrbank1_ev_enable0_r;
wire csrbank1_ev_enable0_we;
wire csrbank1_ev_enable0_w;
wire csrbank1_sel;
wire [13:0] interface2_bank_bus_adr;
wire interface2_bank_bus_we;
wire [7:0] interface2_bank_bus_dat_w;
reg [7:0] interface2_bank_bus_dat_r = 8'd0;
wire csrbank2_txfull_re;
wire csrbank2_txfull_r;
wire csrbank2_txfull_we;
wire csrbank2_txfull_w;
wire csrbank2_rxempty_re;
wire csrbank2_rxempty_r;
wire csrbank2_rxempty_we;
wire csrbank2_rxempty_w;
wire csrbank2_ev_enable0_re;
wire [1:0] csrbank2_ev_enable0_r;
wire csrbank2_ev_enable0_we;
wire [1:0] csrbank2_ev_enable0_w;
wire csrbank2_sel;
wire [13:0] interface3_bank_bus_adr;
wire interface3_bank_bus_we;
wire [7:0] interface3_bank_bus_dat_w;
reg [7:0] interface3_bank_bus_dat_r = 8'd0;
wire csrbank3_tuning_word3_re;
wire [7:0] csrbank3_tuning_word3_r;
wire csrbank3_tuning_word3_we;
wire [7:0] csrbank3_tuning_word3_w;
wire csrbank3_tuning_word2_re;
wire [7:0] csrbank3_tuning_word2_r;
wire csrbank3_tuning_word2_we;
wire [7:0] csrbank3_tuning_word2_w;
wire csrbank3_tuning_word1_re;
wire [7:0] csrbank3_tuning_word1_r;
wire csrbank3_tuning_word1_we;
wire [7:0] csrbank3_tuning_word1_w;
wire csrbank3_tuning_word0_re;
wire [7:0] csrbank3_tuning_word0_r;
wire csrbank3_tuning_word0_we;
wire [7:0] csrbank3_tuning_word0_w;
wire csrbank3_sel;
wire [13:0] adr;
wire we;
wire [7:0] dat_w;
wire [7:0] dat_r;
reg [29:0] array_muxed0 = 30'd0;
reg [31:0] array_muxed1 = 32'd0;
reg [3:0] array_muxed2 = 4'd0;
reg array_muxed3 = 1'd0;
reg array_muxed4 = 1'd0;
reg array_muxed5 = 1'd0;
reg [2:0] array_muxed6 = 3'd0;
reg [1:0] array_muxed7 = 2'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg regs1 = 1'd0;
wire xilinxasyncresetsynchronizerimpl0;
wire xilinxasyncresetsynchronizerimpl0_rst_meta;
wire xilinxasyncresetsynchronizerimpl1_rst_meta;

assign cpu_reset = soccontroller_reset;
assign soccontroller_bus_error = error;
always @(*) begin
	cpu_interrupt <= 32'd0;
	cpu_interrupt[1] <= timer_irq;
	cpu_interrupt[0] <= uart_irq;
end
assign soccontroller_reset = soccontroller_reset_re;
assign soccontroller_bus_errors_status = soccontroller_bus_errors;
assign basesoc_adr = basesoc_ram_bus_adr[12:0];
assign basesoc_ram_bus_dat_r = basesoc_dat_r;
always @(*) begin
	sram0_we <= 4'd0;
	sram0_we[0] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[0]);
	sram0_we[1] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[1]);
	sram0_we[2] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[2]);
	sram0_we[3] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[3]);
end
assign sram0_adr = interface0_ram_bus_adr[9:0];
assign interface0_ram_bus_dat_r = sram0_dat_r;
assign sram0_dat_w = interface0_ram_bus_dat_w;
always @(*) begin
	sram1_we <= 4'd0;
	sram1_we[0] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[0]);
	sram1_we[1] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[1]);
	sram1_we[2] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[2]);
	sram1_we[3] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[3]);
end
assign sram1_adr = interface1_ram_bus_adr[14:0];
assign interface1_ram_bus_dat_r = sram1_dat_r;
assign sram1_dat_w = interface1_ram_bus_dat_w;
assign uart_uart_sink_valid = source_valid;
assign source_ready = uart_uart_sink_ready;
assign uart_uart_sink_first = source_first;
assign uart_uart_sink_last = source_last;
assign uart_uart_sink_payload_data = source_payload_data;
assign sink_valid = uart_uart_source_valid;
assign uart_uart_source_ready = sink_ready;
assign sink_first = uart_uart_source_first;
assign sink_last = uart_uart_source_last;
assign sink_payload_data = uart_uart_source_payload_data;
assign uart_tx_fifo_sink_valid = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_txfull_status = (~uart_tx_fifo_sink_ready);
assign uart_uart_source_valid = uart_tx_fifo_source_valid;
assign uart_tx_fifo_source_ready = uart_uart_source_ready;
assign uart_uart_source_first = uart_tx_fifo_source_first;
assign uart_uart_source_last = uart_tx_fifo_source_last;
assign uart_uart_source_payload_data = uart_tx_fifo_source_payload_data;
assign uart_tx_trigger = (~uart_tx_fifo_sink_ready);
assign uart_rx_fifo_sink_valid = uart_uart_sink_valid;
assign uart_uart_sink_ready = uart_rx_fifo_sink_ready;
assign uart_rx_fifo_sink_first = uart_uart_sink_first;
assign uart_rx_fifo_sink_last = uart_uart_sink_last;
assign uart_rx_fifo_sink_payload_data = uart_uart_sink_payload_data;
assign uart_rxempty_status = (~uart_rx_fifo_source_valid);
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ready = (uart_rx_clear | (1'd0 & uart_rxtx_we));
assign uart_rx_trigger = (~uart_rx_fifo_source_valid);
always @(*) begin
	uart_tx_clear <= 1'd0;
	if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[0])) begin
		uart_tx_clear <= 1'd1;
	end
end
always @(*) begin
	uart_eventmanager_status_w <= 2'd0;
	uart_eventmanager_status_w[0] <= uart_tx_status;
	uart_eventmanager_status_w[1] <= uart_rx_status;
end
always @(*) begin
	uart_rx_clear <= 1'd0;
	if ((uart_eventmanager_pending_re & uart_eventmanager_pending_r[1])) begin
		uart_rx_clear <= 1'd1;
	end
end
always @(*) begin
	uart_eventmanager_pending_w <= 2'd0;
	uart_eventmanager_pending_w[0] <= uart_tx_pending;
	uart_eventmanager_pending_w[1] <= uart_rx_pending;
end
assign uart_irq = ((uart_eventmanager_pending_w[0] & uart_eventmanager_storage[0]) | (uart_eventmanager_pending_w[1] & uart_eventmanager_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid;
assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first;
assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_valid = uart_tx_fifo_readable;
assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first;
assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_re = uart_tx_fifo_source_ready;
assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re));
assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable);
always @(*) begin
	uart_tx_fifo_wrport_adr <= 4'd0;
	if (uart_tx_fifo_replace) begin
		uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1);
	end else begin
		uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce;
	end
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid;
assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first;
assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_valid = uart_rx_fifo_readable;
assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first;
assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_re = uart_rx_fifo_source_ready;
assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re));
assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable);
always @(*) begin
	uart_rx_fifo_wrport_adr <= 4'd0;
	if (uart_rx_fifo_replace) begin
		uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1);
	end else begin
		uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce;
	end
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0);
assign timer_zero_trigger = (timer_value != 1'd0);
assign timer_eventmanager_status_w = timer_zero_status;
always @(*) begin
	timer_zero_clear <= 1'd0;
	if ((timer_eventmanager_pending_re & timer_eventmanager_pending_r)) begin
		timer_zero_clear <= 1'd1;
	end
end
assign timer_eventmanager_pending_w = timer_zero_pending;
assign timer_irq = (timer_eventmanager_pending_w & timer_eventmanager_storage);
assign timer_zero_status = timer_zero_trigger;
assign interface_dat_w = bus_wishbone_dat_w;
assign bus_wishbone_dat_r = interface_dat_r;
always @(*) begin
	next_state <= 1'd0;
	interface_adr <= 14'd0;
	interface_we <= 1'd0;
	bus_wishbone_ack <= 1'd0;
	next_state <= state;
	case (state)
		1'd1: begin
			bus_wishbone_ack <= 1'd1;
			next_state <= 1'd0;
		end
		default: begin
			if ((bus_wishbone_cyc & bus_wishbone_stb)) begin
				interface_adr <= bus_wishbone_adr;
				interface_we <= bus_wishbone_we;
				next_state <= 1'd1;
			end
		end
	endcase
end
assign ic_clk = sys_clk;
assign pll4x_clk = clkout0;
assign clk500_clk = clkout_buf;
assign shared_adr = array_muxed0;
assign shared_dat_w = array_muxed1;
assign shared_sel = array_muxed2;
assign shared_cyc = array_muxed3;
assign shared_stb = array_muxed4;
assign shared_we = array_muxed5;
assign shared_cti = array_muxed6;
assign shared_bte = array_muxed7;
assign cpu_ibus_dat_r = shared_dat_r;
assign cpu_dbus_dat_r = shared_dat_r;
assign cpu_ibus_ack = (shared_ack & (grant == 1'd0));
assign cpu_dbus_ack = (shared_ack & (grant == 1'd1));
assign cpu_ibus_err = (shared_err & (grant == 1'd0));
assign cpu_dbus_err = (shared_err & (grant == 1'd1));
assign request = {cpu_dbus_cyc, cpu_ibus_cyc};
always @(*) begin
	slave_sel <= 4'd0;
	slave_sel[0] <= (shared_adr[29:13] == 1'd0);
	slave_sel[1] <= (shared_adr[29:10] == 13'd4096);
	slave_sel[2] <= (shared_adr[29:15] == 14'd8192);
	slave_sel[3] <= (shared_adr[29:14] == 16'd33280);
end
assign basesoc_ram_bus_adr = shared_adr;
assign basesoc_ram_bus_dat_w = shared_dat_w;
assign basesoc_ram_bus_sel = shared_sel;
assign basesoc_ram_bus_stb = shared_stb;
assign basesoc_ram_bus_we = shared_we;
assign basesoc_ram_bus_cti = shared_cti;
assign basesoc_ram_bus_bte = shared_bte;
assign interface0_ram_bus_adr = shared_adr;
assign interface0_ram_bus_dat_w = shared_dat_w;
assign interface0_ram_bus_sel = shared_sel;
assign interface0_ram_bus_stb = shared_stb;
assign interface0_ram_bus_we = shared_we;
assign interface0_ram_bus_cti = shared_cti;
assign interface0_ram_bus_bte = shared_bte;
assign interface1_ram_bus_adr = shared_adr;
assign interface1_ram_bus_dat_w = shared_dat_w;
assign interface1_ram_bus_sel = shared_sel;
assign interface1_ram_bus_stb = shared_stb;
assign interface1_ram_bus_we = shared_we;
assign interface1_ram_bus_cti = shared_cti;
assign interface1_ram_bus_bte = shared_bte;
assign bus_wishbone_adr = shared_adr;
assign bus_wishbone_dat_w = shared_dat_w;
assign bus_wishbone_sel = shared_sel;
assign bus_wishbone_stb = shared_stb;
assign bus_wishbone_we = shared_we;
assign bus_wishbone_cti = shared_cti;
assign bus_wishbone_bte = shared_bte;
assign basesoc_ram_bus_cyc = (shared_cyc & slave_sel[0]);
assign interface0_ram_bus_cyc = (shared_cyc & slave_sel[1]);
assign interface1_ram_bus_cyc = (shared_cyc & slave_sel[2]);
assign bus_wishbone_cyc = (shared_cyc & slave_sel[3]);
assign shared_err = (((basesoc_ram_bus_err | interface0_ram_bus_err) | interface1_ram_bus_err) | bus_wishbone_err);
assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
always @(*) begin
	shared_ack <= 1'd0;
	error <= 1'd0;
	shared_dat_r <= 32'd0;
	shared_ack <= (((basesoc_ram_bus_ack | interface0_ram_bus_ack) | interface1_ram_bus_ack) | bus_wishbone_ack);
	shared_dat_r <= (((({32{slave_sel_r[0]}} & basesoc_ram_bus_dat_r) | ({32{slave_sel_r[1]}} & interface0_ram_bus_dat_r)) | ({32{slave_sel_r[2]}} & interface1_ram_bus_dat_r)) | ({32{slave_sel_r[3]}} & bus_wishbone_dat_r));
	if (done) begin
		shared_dat_r <= 32'd4294967295;
		shared_ack <= 1'd1;
		error <= 1'd1;
	end
end
assign done = (count == 1'd0);
assign csrbank0_sel = (interface0_bank_bus_adr[13:9] == 1'd0);
assign csrbank0_reset0_r = interface0_bank_bus_dat_w[0];
assign csrbank0_reset0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 1'd0));
assign csrbank0_reset0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 1'd0));
assign csrbank0_scratch3_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_scratch3_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 1'd1));
assign csrbank0_scratch3_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 1'd1));
assign csrbank0_scratch2_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_scratch2_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 2'd2));
assign csrbank0_scratch2_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 2'd2));
assign csrbank0_scratch1_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_scratch1_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 2'd3));
assign csrbank0_scratch1_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 2'd3));
assign csrbank0_scratch0_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_scratch0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 3'd4));
assign csrbank0_scratch0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 3'd4));
assign csrbank0_bus_errors3_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_bus_errors3_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 3'd5));
assign csrbank0_bus_errors3_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 3'd5));
assign csrbank0_bus_errors2_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_bus_errors2_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 3'd6));
assign csrbank0_bus_errors2_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 3'd6));
assign csrbank0_bus_errors1_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_bus_errors1_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 3'd7));
assign csrbank0_bus_errors1_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 3'd7));
assign csrbank0_bus_errors0_r = interface0_bank_bus_dat_w[7:0];
assign csrbank0_bus_errors0_re = ((csrbank0_sel & interface0_bank_bus_we) & (interface0_bank_bus_adr[3:0] == 4'd8));
assign csrbank0_bus_errors0_we = ((csrbank0_sel & (~interface0_bank_bus_we)) & (interface0_bank_bus_adr[3:0] == 4'd8));
assign csrbank0_reset0_w = soccontroller_reset_storage;
assign csrbank0_scratch3_w = soccontroller_scratch_storage[31:24];
assign csrbank0_scratch2_w = soccontroller_scratch_storage[23:16];
assign csrbank0_scratch1_w = soccontroller_scratch_storage[15:8];
assign csrbank0_scratch0_w = soccontroller_scratch_storage[7:0];
assign csrbank0_bus_errors3_w = soccontroller_bus_errors_status[31:24];
assign csrbank0_bus_errors2_w = soccontroller_bus_errors_status[23:16];
assign csrbank0_bus_errors1_w = soccontroller_bus_errors_status[15:8];
assign csrbank0_bus_errors0_w = soccontroller_bus_errors_status[7:0];
assign soccontroller_bus_errors_we = csrbank0_bus_errors0_we;
assign csrbank1_sel = (interface1_bank_bus_adr[13:9] == 3'd4);
assign csrbank1_load3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_load3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_load3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd0));
assign csrbank1_load2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_load2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbank1_load2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 1'd1));
assign csrbank1_load1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_load1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbank1_load1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd2));
assign csrbank1_load0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_load0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_load0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 2'd3));
assign csrbank1_reload3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_reload3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_reload3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd4));
assign csrbank1_reload2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_reload2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_reload2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd5));
assign csrbank1_reload1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_reload1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_reload1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd6));
assign csrbank1_reload0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_reload0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbank1_reload0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 3'd7));
assign csrbank1_en0_r = interface1_bank_bus_dat_w[0];
assign csrbank1_en0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbank1_en0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd8));
assign csrbank1_update_value0_r = interface1_bank_bus_dat_w[0];
assign csrbank1_update_value0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_update_value0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd9));
assign csrbank1_value3_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_value3_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_value3_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd10));
assign csrbank1_value2_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_value2_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_value2_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd11));
assign csrbank1_value1_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_value1_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_value1_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd12));
assign csrbank1_value0_r = interface1_bank_bus_dat_w[7:0];
assign csrbank1_value0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign csrbank1_value0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd13));
assign timer_eventmanager_status_r = interface1_bank_bus_dat_w[0];
assign timer_eventmanager_status_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign timer_eventmanager_status_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd14));
assign timer_eventmanager_pending_r = interface1_bank_bus_dat_w[0];
assign timer_eventmanager_pending_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign timer_eventmanager_pending_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 4'd15));
assign csrbank1_ev_enable0_r = interface1_bank_bus_dat_w[0];
assign csrbank1_ev_enable0_re = ((csrbank1_sel & interface1_bank_bus_we) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_ev_enable0_we = ((csrbank1_sel & (~interface1_bank_bus_we)) & (interface1_bank_bus_adr[4:0] == 5'd16));
assign csrbank1_load3_w = timer_load_storage[31:24];
assign csrbank1_load2_w = timer_load_storage[23:16];
assign csrbank1_load1_w = timer_load_storage[15:8];
assign csrbank1_load0_w = timer_load_storage[7:0];
assign csrbank1_reload3_w = timer_reload_storage[31:24];
assign csrbank1_reload2_w = timer_reload_storage[23:16];
assign csrbank1_reload1_w = timer_reload_storage[15:8];
assign csrbank1_reload0_w = timer_reload_storage[7:0];
assign csrbank1_en0_w = timer_en_storage;
assign csrbank1_update_value0_w = timer_update_value_storage;
assign csrbank1_value3_w = timer_value_status[31:24];
assign csrbank1_value2_w = timer_value_status[23:16];
assign csrbank1_value1_w = timer_value_status[15:8];
assign csrbank1_value0_w = timer_value_status[7:0];
assign timer_value_we = csrbank1_value0_we;
assign csrbank1_ev_enable0_w = timer_eventmanager_storage;
assign csrbank2_sel = (interface2_bank_bus_adr[13:9] == 2'd3);
assign uart_rxtx_r = interface2_bank_bus_dat_w[7:0];
assign uart_rxtx_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[2:0] == 1'd0));
assign uart_rxtx_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[2:0] == 1'd0));
assign csrbank2_txfull_r = interface2_bank_bus_dat_w[0];
assign csrbank2_txfull_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[2:0] == 1'd1));
assign csrbank2_txfull_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[2:0] == 1'd1));
assign csrbank2_rxempty_r = interface2_bank_bus_dat_w[0];
assign csrbank2_rxempty_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[2:0] == 2'd2));
assign csrbank2_rxempty_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[2:0] == 2'd2));
assign uart_eventmanager_status_r = interface2_bank_bus_dat_w[1:0];
assign uart_eventmanager_status_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[2:0] == 2'd3));
assign uart_eventmanager_status_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[2:0] == 2'd3));
assign uart_eventmanager_pending_r = interface2_bank_bus_dat_w[1:0];
assign uart_eventmanager_pending_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[2:0] == 3'd4));
assign uart_eventmanager_pending_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[2:0] == 3'd4));
assign csrbank2_ev_enable0_r = interface2_bank_bus_dat_w[1:0];
assign csrbank2_ev_enable0_re = ((csrbank2_sel & interface2_bank_bus_we) & (interface2_bank_bus_adr[2:0] == 3'd5));
assign csrbank2_ev_enable0_we = ((csrbank2_sel & (~interface2_bank_bus_we)) & (interface2_bank_bus_adr[2:0] == 3'd5));
assign csrbank2_txfull_w = uart_txfull_status;
assign uart_txfull_we = csrbank2_txfull_we;
assign csrbank2_rxempty_w = uart_rxempty_status;
assign uart_rxempty_we = csrbank2_rxempty_we;
assign csrbank2_ev_enable0_w = uart_eventmanager_storage[1:0];
assign csrbank3_sel = (interface3_bank_bus_adr[13:9] == 2'd2);
assign csrbank3_tuning_word3_r = interface3_bank_bus_dat_w[7:0];
assign csrbank3_tuning_word3_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[1:0] == 1'd0));
assign csrbank3_tuning_word3_we = ((csrbank3_sel & (~interface3_bank_bus_we)) & (interface3_bank_bus_adr[1:0] == 1'd0));
assign csrbank3_tuning_word2_r = interface3_bank_bus_dat_w[7:0];
assign csrbank3_tuning_word2_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[1:0] == 1'd1));
assign csrbank3_tuning_word2_we = ((csrbank3_sel & (~interface3_bank_bus_we)) & (interface3_bank_bus_adr[1:0] == 1'd1));
assign csrbank3_tuning_word1_r = interface3_bank_bus_dat_w[7:0];
assign csrbank3_tuning_word1_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[1:0] == 2'd2));
assign csrbank3_tuning_word1_we = ((csrbank3_sel & (~interface3_bank_bus_we)) & (interface3_bank_bus_adr[1:0] == 2'd2));
assign csrbank3_tuning_word0_r = interface3_bank_bus_dat_w[7:0];
assign csrbank3_tuning_word0_re = ((csrbank3_sel & interface3_bank_bus_we) & (interface3_bank_bus_adr[1:0] == 2'd3));
assign csrbank3_tuning_word0_we = ((csrbank3_sel & (~interface3_bank_bus_we)) & (interface3_bank_bus_adr[1:0] == 2'd3));
assign csrbank3_tuning_word3_w = storage[31:24];
assign csrbank3_tuning_word2_w = storage[23:16];
assign csrbank3_tuning_word1_w = storage[15:8];
assign csrbank3_tuning_word0_w = storage[7:0];
assign adr = interface_adr;
assign we = interface_we;
assign dat_w = interface_dat_w;
assign interface_dat_r = dat_r;
assign interface0_bank_bus_adr = adr;
assign interface1_bank_bus_adr = adr;
assign interface2_bank_bus_adr = adr;
assign interface3_bank_bus_adr = adr;
assign interface0_bank_bus_we = we;
assign interface1_bank_bus_we = we;
assign interface2_bank_bus_we = we;
assign interface3_bank_bus_we = we;
assign interface0_bank_bus_dat_w = dat_w;
assign interface1_bank_bus_dat_w = dat_w;
assign interface2_bank_bus_dat_w = dat_w;
assign interface3_bank_bus_dat_w = dat_w;
assign dat_r = (((interface0_bank_bus_dat_r | interface1_bank_bus_dat_r) | interface2_bank_bus_dat_r) | interface3_bank_bus_dat_r);
always @(*) begin
	array_muxed0 <= 30'd0;
	case (grant)
		1'd0: begin
			array_muxed0 <= cpu_ibus_adr;
		end
		default: begin
			array_muxed0 <= cpu_dbus_adr;
		end
	endcase
end
always @(*) begin
	array_muxed1 <= 32'd0;
	case (grant)
		1'd0: begin
			array_muxed1 <= cpu_ibus_dat_w;
		end
		default: begin
			array_muxed1 <= cpu_dbus_dat_w;
		end
	endcase
end
always @(*) begin
	array_muxed2 <= 4'd0;
	case (grant)
		1'd0: begin
			array_muxed2 <= cpu_ibus_sel;
		end
		default: begin
			array_muxed2 <= cpu_dbus_sel;
		end
	endcase
end
always @(*) begin
	array_muxed3 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed3 <= cpu_ibus_cyc;
		end
		default: begin
			array_muxed3 <= cpu_dbus_cyc;
		end
	endcase
end
always @(*) begin
	array_muxed4 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed4 <= cpu_ibus_stb;
		end
		default: begin
			array_muxed4 <= cpu_dbus_stb;
		end
	endcase
end
always @(*) begin
	array_muxed5 <= 1'd0;
	case (grant)
		1'd0: begin
			array_muxed5 <= cpu_ibus_we;
		end
		default: begin
			array_muxed5 <= cpu_dbus_we;
		end
	endcase
end
always @(*) begin
	array_muxed6 <= 3'd0;
	case (grant)
		1'd0: begin
			array_muxed6 <= cpu_ibus_cti;
		end
		default: begin
			array_muxed6 <= cpu_dbus_cti;
		end
	endcase
end
always @(*) begin
	array_muxed7 <= 2'd0;
	case (grant)
		1'd0: begin
			array_muxed7 <= cpu_ibus_bte;
		end
		default: begin
			array_muxed7 <= cpu_dbus_bte;
		end
	endcase
end
assign rx = regs1;
assign xilinxasyncresetsynchronizerimpl0 = (~locked);

always @(posedge clk500_clk) begin
	if ((ic_reset_counter != 1'd0)) begin
		ic_reset_counter <= (ic_reset_counter - 1'd1);
	end else begin
		ic_reset <= 1'd0;
	end
	if (clk500_rst) begin
		ic_reset_counter <= 6'd63;
		ic_reset <= 1'd1;
	end
end

always @(posedge ic_clk) begin
	if (ic_rdy) begin
		if ((ic_rdy_counter != 1'd0)) begin
			ic_rdy_counter <= (ic_rdy_counter - 1'd1);
		end else begin
			sys_rst <= 1'd0;
		end
	end
	if (ic_rst) begin
		sys_rst <= 1'd1;
		ic_rdy_counter <= 6'd63;
	end
end

always @(posedge sys_clk) begin
	if ((soccontroller_bus_errors != 32'd4294967295)) begin
		if (soccontroller_bus_error) begin
			soccontroller_bus_errors <= (soccontroller_bus_errors + 1'd1);
		end
	end
	basesoc_ram_bus_ack <= 1'd0;
	if (((basesoc_ram_bus_cyc & basesoc_ram_bus_stb) & (~basesoc_ram_bus_ack))) begin
		basesoc_ram_bus_ack <= 1'd1;
	end
	interface0_ram_bus_ack <= 1'd0;
	if (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & (~interface0_ram_bus_ack))) begin
		interface0_ram_bus_ack <= 1'd1;
	end
	interface1_ram_bus_ack <= 1'd0;
	if (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & (~interface1_ram_bus_ack))) begin
		interface1_ram_bus_ack <= 1'd1;
	end
	sink_ready <= 1'd0;
	if (((sink_valid & (~tx_busy)) & (~sink_ready))) begin
		tx_reg <= sink_payload_data;
		tx_bitcount <= 1'd0;
		tx_busy <= 1'd1;
		serial_tx <= 1'd0;
	end else begin
		if ((uart_clk_txen & tx_busy)) begin
			tx_bitcount <= (tx_bitcount + 1'd1);
			if ((tx_bitcount == 4'd8)) begin
				serial_tx <= 1'd1;
			end else begin
				if ((tx_bitcount == 4'd9)) begin
					serial_tx <= 1'd1;
					tx_busy <= 1'd0;
					sink_ready <= 1'd1;
				end else begin
					serial_tx <= tx_reg[0];
					tx_reg <= {1'd0, tx_reg[7:1]};
				end
			end
		end
	end
	if (tx_busy) begin
		{uart_clk_txen, phase_accumulator_tx} <= (phase_accumulator_tx + storage);
	end else begin
		{uart_clk_txen, phase_accumulator_tx} <= 1'd0;
	end
	source_valid <= 1'd0;
	rx_r <= rx;
	if ((~rx_busy)) begin
		if (((~rx) & rx_r)) begin
			rx_busy <= 1'd1;
			rx_bitcount <= 1'd0;
		end
	end else begin
		if (uart_clk_rxen) begin
			rx_bitcount <= (rx_bitcount + 1'd1);
			if ((rx_bitcount == 1'd0)) begin
				if (rx) begin
					rx_busy <= 1'd0;
				end
			end else begin
				if ((rx_bitcount == 4'd9)) begin
					rx_busy <= 1'd0;
					if (rx) begin
						source_payload_data <= rx_reg;
						source_valid <= 1'd1;
					end
				end else begin
					rx_reg <= {rx, rx_reg[7:1]};
				end
			end
		end
	end
	if (rx_busy) begin
		{uart_clk_rxen, phase_accumulator_rx} <= (phase_accumulator_rx + storage);
	end else begin
		{uart_clk_rxen, phase_accumulator_rx} <= 32'd2147483648;
	end
	if (uart_tx_clear) begin
		uart_tx_pending <= 1'd0;
	end
	uart_tx_old_trigger <= uart_tx_trigger;
	if (((~uart_tx_trigger) & uart_tx_old_trigger)) begin
		uart_tx_pending <= 1'd1;
	end
	if (uart_rx_clear) begin
		uart_rx_pending <= 1'd0;
	end
	uart_rx_old_trigger <= uart_rx_trigger;
	if (((~uart_rx_trigger) & uart_rx_old_trigger)) begin
		uart_rx_pending <= 1'd1;
	end
	if (uart_tx_fifo_syncfifo_re) begin
		uart_tx_fifo_readable <= 1'd1;
	end else begin
		if (uart_tx_fifo_re) begin
			uart_tx_fifo_readable <= 1'd0;
		end
	end
	if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
		uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
	end
	if (uart_tx_fifo_do_read) begin
		uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
	end
	if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
		if ((~uart_tx_fifo_do_read)) begin
			uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1);
		end
	end else begin
		if (uart_tx_fifo_do_read) begin
			uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1);
		end
	end
	if (uart_rx_fifo_syncfifo_re) begin
		uart_rx_fifo_readable <= 1'd1;
	end else begin
		if (uart_rx_fifo_re) begin
			uart_rx_fifo_readable <= 1'd0;
		end
	end
	if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
		uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
	end
	if (uart_rx_fifo_do_read) begin
		uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
	end
	if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
		if ((~uart_rx_fifo_do_read)) begin
			uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1);
		end
	end else begin
		if (uart_rx_fifo_do_read) begin
			uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1);
		end
	end
	if (uart_reset) begin
		uart_tx_pending <= 1'd0;
		uart_tx_old_trigger <= 1'd0;
		uart_rx_pending <= 1'd0;
		uart_rx_old_trigger <= 1'd0;
		uart_tx_fifo_readable <= 1'd0;
		uart_tx_fifo_level0 <= 5'd0;
		uart_tx_fifo_produce <= 4'd0;
		uart_tx_fifo_consume <= 4'd0;
		uart_rx_fifo_readable <= 1'd0;
		uart_rx_fifo_level0 <= 5'd0;
		uart_rx_fifo_produce <= 4'd0;
		uart_rx_fifo_consume <= 4'd0;
	end
	if (timer_en_storage) begin
		if ((timer_value == 1'd0)) begin
			timer_value <= timer_reload_storage;
		end else begin
			timer_value <= (timer_value - 1'd1);
		end
	end else begin
		timer_value <= timer_load_storage;
	end
	if (timer_update_value_re) begin
		timer_value_status <= timer_value;
	end
	if (timer_zero_clear) begin
		timer_zero_pending <= 1'd0;
	end
	timer_zero_old_trigger <= timer_zero_trigger;
	if (((~timer_zero_trigger) & timer_zero_old_trigger)) begin
		timer_zero_pending <= 1'd1;
	end
	state <= next_state;
	case (grant)
		1'd0: begin
			if ((~request[0])) begin
				if (request[1]) begin
					grant <= 1'd1;
				end
			end
		end
		1'd1: begin
			if ((~request[1])) begin
				if (request[0]) begin
					grant <= 1'd0;
				end
			end
		end
	endcase
	slave_sel_r <= slave_sel;
	if (wait_1) begin
		if ((~done)) begin
			count <= (count - 1'd1);
		end
	end else begin
		count <= 20'd1000000;
	end
	interface0_bank_bus_dat_r <= 1'd0;
	if (csrbank0_sel) begin
		case (interface0_bank_bus_adr[3:0])
			1'd0: begin
				interface0_bank_bus_dat_r <= csrbank0_reset0_w;
			end
			1'd1: begin
				interface0_bank_bus_dat_r <= csrbank0_scratch3_w;
			end
			2'd2: begin
				interface0_bank_bus_dat_r <= csrbank0_scratch2_w;
			end
			2'd3: begin
				interface0_bank_bus_dat_r <= csrbank0_scratch1_w;
			end
			3'd4: begin
				interface0_bank_bus_dat_r <= csrbank0_scratch0_w;
			end
			3'd5: begin
				interface0_bank_bus_dat_r <= csrbank0_bus_errors3_w;
			end
			3'd6: begin
				interface0_bank_bus_dat_r <= csrbank0_bus_errors2_w;
			end
			3'd7: begin
				interface0_bank_bus_dat_r <= csrbank0_bus_errors1_w;
			end
			4'd8: begin
				interface0_bank_bus_dat_r <= csrbank0_bus_errors0_w;
			end
		endcase
	end
	if (csrbank0_reset0_re) begin
		soccontroller_reset_storage <= csrbank0_reset0_r;
	end
	soccontroller_reset_re <= csrbank0_reset0_re;
	if (csrbank0_scratch3_re) begin
		soccontroller_scratch_storage[31:24] <= csrbank0_scratch3_r;
	end
	if (csrbank0_scratch2_re) begin
		soccontroller_scratch_storage[23:16] <= csrbank0_scratch2_r;
	end
	if (csrbank0_scratch1_re) begin
		soccontroller_scratch_storage[15:8] <= csrbank0_scratch1_r;
	end
	if (csrbank0_scratch0_re) begin
		soccontroller_scratch_storage[7:0] <= csrbank0_scratch0_r;
	end
	soccontroller_scratch_re <= csrbank0_scratch0_re;
	interface1_bank_bus_dat_r <= 1'd0;
	if (csrbank1_sel) begin
		case (interface1_bank_bus_adr[4:0])
			1'd0: begin
				interface1_bank_bus_dat_r <= csrbank1_load3_w;
			end
			1'd1: begin
				interface1_bank_bus_dat_r <= csrbank1_load2_w;
			end
			2'd2: begin
				interface1_bank_bus_dat_r <= csrbank1_load1_w;
			end
			2'd3: begin
				interface1_bank_bus_dat_r <= csrbank1_load0_w;
			end
			3'd4: begin
				interface1_bank_bus_dat_r <= csrbank1_reload3_w;
			end
			3'd5: begin
				interface1_bank_bus_dat_r <= csrbank1_reload2_w;
			end
			3'd6: begin
				interface1_bank_bus_dat_r <= csrbank1_reload1_w;
			end
			3'd7: begin
				interface1_bank_bus_dat_r <= csrbank1_reload0_w;
			end
			4'd8: begin
				interface1_bank_bus_dat_r <= csrbank1_en0_w;
			end
			4'd9: begin
				interface1_bank_bus_dat_r <= csrbank1_update_value0_w;
			end
			4'd10: begin
				interface1_bank_bus_dat_r <= csrbank1_value3_w;
			end
			4'd11: begin
				interface1_bank_bus_dat_r <= csrbank1_value2_w;
			end
			4'd12: begin
				interface1_bank_bus_dat_r <= csrbank1_value1_w;
			end
			4'd13: begin
				interface1_bank_bus_dat_r <= csrbank1_value0_w;
			end
			4'd14: begin
				interface1_bank_bus_dat_r <= timer_eventmanager_status_w;
			end
			4'd15: begin
				interface1_bank_bus_dat_r <= timer_eventmanager_pending_w;
			end
			5'd16: begin
				interface1_bank_bus_dat_r <= csrbank1_ev_enable0_w;
			end
		endcase
	end
	if (csrbank1_load3_re) begin
		timer_load_storage[31:24] <= csrbank1_load3_r;
	end
	if (csrbank1_load2_re) begin
		timer_load_storage[23:16] <= csrbank1_load2_r;
	end
	if (csrbank1_load1_re) begin
		timer_load_storage[15:8] <= csrbank1_load1_r;
	end
	if (csrbank1_load0_re) begin
		timer_load_storage[7:0] <= csrbank1_load0_r;
	end
	timer_load_re <= csrbank1_load0_re;
	if (csrbank1_reload3_re) begin
		timer_reload_storage[31:24] <= csrbank1_reload3_r;
	end
	if (csrbank1_reload2_re) begin
		timer_reload_storage[23:16] <= csrbank1_reload2_r;
	end
	if (csrbank1_reload1_re) begin
		timer_reload_storage[15:8] <= csrbank1_reload1_r;
	end
	if (csrbank1_reload0_re) begin
		timer_reload_storage[7:0] <= csrbank1_reload0_r;
	end
	timer_reload_re <= csrbank1_reload0_re;
	if (csrbank1_en0_re) begin
		timer_en_storage <= csrbank1_en0_r;
	end
	timer_en_re <= csrbank1_en0_re;
	if (csrbank1_update_value0_re) begin
		timer_update_value_storage <= csrbank1_update_value0_r;
	end
	timer_update_value_re <= csrbank1_update_value0_re;
	if (csrbank1_ev_enable0_re) begin
		timer_eventmanager_storage <= csrbank1_ev_enable0_r;
	end
	timer_eventmanager_re <= csrbank1_ev_enable0_re;
	interface2_bank_bus_dat_r <= 1'd0;
	if (csrbank2_sel) begin
		case (interface2_bank_bus_adr[2:0])
			1'd0: begin
				interface2_bank_bus_dat_r <= uart_rxtx_w;
			end
			1'd1: begin
				interface2_bank_bus_dat_r <= csrbank2_txfull_w;
			end
			2'd2: begin
				interface2_bank_bus_dat_r <= csrbank2_rxempty_w;
			end
			2'd3: begin
				interface2_bank_bus_dat_r <= uart_eventmanager_status_w;
			end
			3'd4: begin
				interface2_bank_bus_dat_r <= uart_eventmanager_pending_w;
			end
			3'd5: begin
				interface2_bank_bus_dat_r <= csrbank2_ev_enable0_w;
			end
		endcase
	end
	if (csrbank2_ev_enable0_re) begin
		uart_eventmanager_storage[1:0] <= csrbank2_ev_enable0_r;
	end
	uart_eventmanager_re <= csrbank2_ev_enable0_re;
	interface3_bank_bus_dat_r <= 1'd0;
	if (csrbank3_sel) begin
		case (interface3_bank_bus_adr[1:0])
			1'd0: begin
				interface3_bank_bus_dat_r <= csrbank3_tuning_word3_w;
			end
			1'd1: begin
				interface3_bank_bus_dat_r <= csrbank3_tuning_word2_w;
			end
			2'd2: begin
				interface3_bank_bus_dat_r <= csrbank3_tuning_word1_w;
			end
			2'd3: begin
				interface3_bank_bus_dat_r <= csrbank3_tuning_word0_w;
			end
		endcase
	end
	if (csrbank3_tuning_word3_re) begin
		storage[31:24] <= csrbank3_tuning_word3_r;
	end
	if (csrbank3_tuning_word2_re) begin
		storage[23:16] <= csrbank3_tuning_word2_r;
	end
	if (csrbank3_tuning_word1_re) begin
		storage[15:8] <= csrbank3_tuning_word1_r;
	end
	if (csrbank3_tuning_word0_re) begin
		storage[7:0] <= csrbank3_tuning_word0_r;
	end
	re <= csrbank3_tuning_word0_re;
	if (sys_rst) begin
		soccontroller_reset_storage <= 1'd0;
		soccontroller_reset_re <= 1'd0;
		soccontroller_scratch_storage <= 32'd305419896;
		soccontroller_scratch_re <= 1'd0;
		soccontroller_bus_errors <= 32'd0;
		basesoc_ram_bus_ack <= 1'd0;
		interface0_ram_bus_ack <= 1'd0;
		interface1_ram_bus_ack <= 1'd0;
		serial_tx <= 1'd1;
		storage <= 32'd3958241;
		re <= 1'd0;
		sink_ready <= 1'd0;
		uart_clk_txen <= 1'd0;
		phase_accumulator_tx <= 32'd0;
		tx_reg <= 8'd0;
		tx_bitcount <= 4'd0;
		tx_busy <= 1'd0;
		source_valid <= 1'd0;
		source_payload_data <= 8'd0;
		uart_clk_rxen <= 1'd0;
		phase_accumulator_rx <= 32'd0;
		rx_r <= 1'd0;
		rx_reg <= 8'd0;
		rx_bitcount <= 4'd0;
		rx_busy <= 1'd0;
		uart_tx_pending <= 1'd0;
		uart_tx_old_trigger <= 1'd0;
		uart_rx_pending <= 1'd0;
		uart_rx_old_trigger <= 1'd0;
		uart_eventmanager_storage <= 2'd0;
		uart_eventmanager_re <= 1'd0;
		uart_tx_fifo_readable <= 1'd0;
		uart_tx_fifo_level0 <= 5'd0;
		uart_tx_fifo_produce <= 4'd0;
		uart_tx_fifo_consume <= 4'd0;
		uart_rx_fifo_readable <= 1'd0;
		uart_rx_fifo_level0 <= 5'd0;
		uart_rx_fifo_produce <= 4'd0;
		uart_rx_fifo_consume <= 4'd0;
		timer_load_storage <= 32'd0;
		timer_load_re <= 1'd0;
		timer_reload_storage <= 32'd0;
		timer_reload_re <= 1'd0;
		timer_en_storage <= 1'd0;
		timer_en_re <= 1'd0;
		timer_update_value_storage <= 1'd0;
		timer_update_value_re <= 1'd0;
		timer_value_status <= 32'd0;
		timer_zero_pending <= 1'd0;
		timer_zero_old_trigger <= 1'd0;
		timer_eventmanager_storage <= 1'd0;
		timer_eventmanager_re <= 1'd0;
		timer_value <= 32'd0;
		state <= 1'd0;
		grant <= 1'd0;
		slave_sel_r <= 4'd0;
		count <= 20'd1000000;
		interface0_bank_bus_dat_r <= 8'd0;
		interface1_bank_bus_dat_r <= 8'd0;
		interface2_bank_bus_dat_r <= 8'd0;
		interface3_bank_bus_dat_r <= 8'd0;
	end
	regs0 <= serial_rx;
	regs1 <= regs0;
end

reg [31:0] mem[0:8191];
reg [31:0] memdat;
always @(posedge sys_clk) begin
	memdat <= mem[basesoc_adr];
end

assign basesoc_dat_r = memdat;

initial begin
	$readmemh("mem.init", mem);
end

reg [31:0] mem_1[0:1023];
reg [9:0] memadr;
always @(posedge sys_clk) begin
	if (sram0_we[0])
		mem_1[sram0_adr][7:0] <= sram0_dat_w[7:0];
	if (sram0_we[1])
		mem_1[sram0_adr][15:8] <= sram0_dat_w[15:8];
	if (sram0_we[2])
		mem_1[sram0_adr][23:16] <= sram0_dat_w[23:16];
	if (sram0_we[3])
		mem_1[sram0_adr][31:24] <= sram0_dat_w[31:24];
	memadr <= sram0_adr;
end

assign sram0_dat_r = mem_1[memadr];

initial begin
	$readmemh("mem_1.init", mem_1);
end

reg [31:0] mem_2[0:32767];
reg [14:0] memadr_1;
always @(posedge sys_clk) begin
	if (sram1_we[0])
		mem_2[sram1_adr][7:0] <= sram1_dat_w[7:0];
	if (sram1_we[1])
		mem_2[sram1_adr][15:8] <= sram1_dat_w[15:8];
	if (sram1_we[2])
		mem_2[sram1_adr][23:16] <= sram1_dat_w[23:16];
	if (sram1_we[3])
		mem_2[sram1_adr][31:24] <= sram1_dat_w[31:24];
	memadr_1 <= sram1_adr;
end

assign sram1_dat_r = mem_2[memadr_1];

initial begin
	$readmemh("mem_2.init", mem_2);
end

reg [9:0] storage_1[0:15];
reg [9:0] memdat_1;
reg [9:0] memdat_2;
always @(posedge sys_clk) begin
	if (uart_tx_fifo_wrport_we)
		storage_1[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
	memdat_1 <= storage_1[uart_tx_fifo_wrport_adr];
end

always @(posedge sys_clk) begin
	if (uart_tx_fifo_rdport_re)
		memdat_2 <= storage_1[uart_tx_fifo_rdport_adr];
end

assign uart_tx_fifo_wrport_dat_r = memdat_1;
assign uart_tx_fifo_rdport_dat_r = memdat_2;

reg [9:0] storage_2[0:15];
reg [9:0] memdat_3;
reg [9:0] memdat_4;
always @(posedge sys_clk) begin
	if (uart_rx_fifo_wrport_we)
		storage_2[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
	memdat_3 <= storage_2[uart_rx_fifo_wrport_adr];
end

always @(posedge sys_clk) begin
	if (uart_rx_fifo_rdport_re)
		memdat_4 <= storage_2[uart_rx_fifo_rdport_adr];
end

assign uart_rx_fifo_wrport_dat_r = memdat_3;
assign uart_rx_fifo_rdport_dat_r = memdat_4;

BUFG BUFG(
	.I(clkout1),
	.O(clkout_buf)
);

BUFGCE_DIV #(
	.BUFGCE_DIVIDE(3'd4)
) main_bufgce_div (
	.CE(1'd1),
	.I(pll4x_clk),
	.O(sys_clk)
);

BUFGCE main_bufgce(
	.CE(1'd1),
	.I(pll4x_clk),
	.O(sys4x_clk)
);

IDELAYCTRL #(
	.SIM_DEVICE("ULTRASCALE")
) IDELAYCTRL (
	.REFCLK(clk500_clk),
	.RST(ic_reset),
	.RDY(ic_rdy)
);

VexRiscv VexRiscv(
	.clk(sys_clk),
	.dBusWishbone_ACK(cpu_dbus_ack),
	.dBusWishbone_DAT_MISO(cpu_dbus_dat_r),
	.dBusWishbone_ERR(cpu_dbus_err),
	.externalInterruptArray(cpu_interrupt),
	.externalResetVector(vexriscv),
	.iBusWishbone_ACK(cpu_ibus_ack),
	.iBusWishbone_DAT_MISO(cpu_ibus_dat_r),
	.iBusWishbone_ERR(cpu_ibus_err),
	.reset((sys_rst | cpu_reset)),
	.softwareInterrupt(1'd0),
	.timerInterrupt(1'd0),
	.dBusWishbone_ADR(cpu_dbus_adr),
	.dBusWishbone_BTE(cpu_dbus_bte),
	.dBusWishbone_CTI(cpu_dbus_cti),
	.dBusWishbone_CYC(cpu_dbus_cyc),
	.dBusWishbone_DAT_MOSI(cpu_dbus_dat_w),
	.dBusWishbone_SEL(cpu_dbus_sel),
	.dBusWishbone_STB(cpu_dbus_stb),
	.dBusWishbone_WE(cpu_dbus_we),
	.iBusWishbone_ADR(cpu_ibus_adr),
	.iBusWishbone_BTE(cpu_ibus_bte),
	.iBusWishbone_CTI(cpu_ibus_cti),
	.iBusWishbone_CYC(cpu_ibus_cyc),
	.iBusWishbone_DAT_MOSI(cpu_ibus_dat_w),
	.iBusWishbone_SEL(cpu_ibus_sel),
	.iBusWishbone_STB(cpu_ibus_stb),
	.iBusWishbone_WE(cpu_ibus_we)
);

MMCME2_ADV #(
	.BANDWIDTH("OPTIMIZED"),
	.CLKFBOUT_MULT_F(4'd8),
	.CLKIN1_PERIOD(8.0),
	.CLKOUT0_DIVIDE_F(2'd2),
	.CLKOUT0_PHASE(1'd0),
	.CLKOUT1_DIVIDE(2'd2),
	.CLKOUT1_PHASE(1'd0),
	.DIVCLK_DIVIDE(1'd1),
	.REF_JITTER1(0.01)
) MMCME2_ADV (
	.CLKFBIN(mmcm_fb),
	.CLKIN1(clkin),
	.RST(reset),
	.CLKFBOUT(mmcm_fb),
	.CLKOUT0(clkout0),
	.CLKOUT1(clkout1),
	.LOCKED(locked)
);

IBUFDS IBUFDS(
	.I(clk125_p),
	.IB(clk125_n),
	.O(clkin)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE (
	.C(clk500_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_1 (
	.C(clk500_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(clk500_rst)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_2 (
	.C(ic_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(ic_reset),
	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_3 (
	.C(ic_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
	.PRE(ic_reset),
	.Q(ic_rst)
);

endmodule