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| ], |
| [ |
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| { |
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| [ |
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| ], |
| [ |
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| ], |
| [ |
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| ], |
| [ |
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| ], |
| [ |
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| ], |
| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| "IMUX_L8" |
| ], |
| [ |
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| ], |
| [ |
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| [ |
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| "NE2END3" |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| "WL1BEG1" |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| "WW4BEG2" |
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| [ |
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| "WW4BEG3" |
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| [ |
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| "WW4A0" |
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| [ |
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| "WW4A1" |
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| [ |
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| [ |
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| "WW4A3" |
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| [ |
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| [ |
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| "WW4B1" |
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| [ |
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| [ |
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| "WW4B3" |
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| [ |
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| "WW4C0" |
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| [ |
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| "WW4C1" |
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| [ |
| "CLBLL_WW4END2", |
| "WW4C2" |
| ], |
| [ |
| "CLBLL_WW4END3", |
| "WW4C3" |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| "CLBLL_NE4C3" |
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| [ |
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| [ |
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| [ |
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| [ |
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| "CLBLL_NW4END3" |
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| [ |
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| "CLBLL_SE2A0" |
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| [ |
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| "CLBLL_SE2A1" |
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| [ |
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| "CLBLL_SE2A2" |
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| [ |
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| "CLBLL_SE2A3" |
| ], |
| [ |
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| "CLBLL_SE4BEG0" |
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| [ |
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| "CLBLL_SE4BEG1" |
| ], |
| [ |
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| "CLBLL_SE4BEG2" |
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| [ |
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| "CLBLL_SE4BEG3" |
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| [ |
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| [ |
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| [ |
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| "CLBLL_SE4C2" |
| ], |
| [ |
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| "CLBLL_SE4C3" |
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| [ |
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| [ |
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| [ |
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| "CLBLL_SW2A2" |
| ], |
| [ |
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| "CLBLL_SW2A3" |
| ], |
| [ |
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| "CLBLL_SW4A0" |
| ], |
| [ |
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| "CLBLL_SW4A1" |
| ], |
| [ |
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| "CLBLL_SW4A2" |
| ], |
| [ |
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| "CLBLL_SW4A3" |
| ], |
| [ |
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| "CLBLL_SW4END0" |
| ], |
| [ |
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| "CLBLL_SW4END1" |
| ], |
| [ |
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| "CLBLL_SW4END2" |
| ], |
| [ |
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| "CLBLL_SW4END3" |
| ], |
| [ |
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| "CLBLL_WL1END0" |
| ], |
| [ |
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| [ |
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| "CLBLL_WL1END2" |
| ], |
| [ |
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| "CLBLL_WL1END3" |
| ], |
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| ], |
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| ], |
| [ |
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| "CLBLL_WR1END2" |
| ], |
| [ |
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| "CLBLL_WR1END3" |
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| [ |
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| ], |
| [ |
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| "CLBLL_WW2A1" |
| ], |
| [ |
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| "CLBLL_WW2A2" |
| ], |
| [ |
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| "CLBLL_WW2A3" |
| ], |
| [ |
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| "CLBLL_WW2END0" |
| ], |
| [ |
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| "CLBLL_WW2END1" |
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| "CLBLL_WW2END2" |
| ], |
| [ |
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| "CLBLL_WW2END3" |
| ], |
| [ |
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| "CLBLL_WW4A0" |
| ], |
| [ |
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| "CLBLL_WW4A1" |
| ], |
| [ |
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| "CLBLL_WW4A2" |
| ], |
| [ |
| "CLBLL_WW4A3", |
| "CLBLL_WW4A3" |
| ], |
| [ |
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| "CLBLL_WW4B0" |
| ], |
| [ |
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| "CLBLL_WW4B1" |
| ], |
| [ |
| "CLBLL_WW4B2", |
| "CLBLL_WW4B2" |
| ], |
| [ |
| "CLBLL_WW4B3", |
| "CLBLL_WW4B3" |
| ], |
| [ |
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| "CLBLL_WW4C0" |
| ], |
| [ |
| "CLBLL_WW4C1", |
| "CLBLL_WW4C1" |
| ], |
| [ |
| "CLBLL_WW4C2", |
| "CLBLL_WW4C2" |
| ], |
| [ |
| "CLBLL_WW4C3", |
| "CLBLL_WW4C3" |
| ], |
| [ |
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| "CLBLL_WW4END0" |
| ], |
| [ |
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| "CLBLL_WW4END1" |
| ], |
| [ |
| "CLBLL_WW4END2", |
| "CLBLL_WW4END2" |
| ], |
| [ |
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| "CLBLL_WW4END3" |
| ] |
| ] |
| }, |
| { |
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| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLL_R", |
| "CLBLL_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLL_LL_CIN", |
| "CLBLL_LL_COUT_N" |
| ], |
| [ |
| "CLBLL_L_CIN", |
| "CLBLL_L_COUT_N" |
| ] |
| ] |
| }, |
| { |
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| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLL_R", |
| "HCLK_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLL_LL_CIN", |
| "HCLK_CLB_COUT1_R" |
| ], |
| [ |
| "CLBLL_L_CIN", |
| "HCLK_CLB_COUT0_R" |
| ] |
| ] |
| }, |
| { |
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| 1, |
| 0 |
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| "tile_types": [ |
| "CLBLL_R", |
| "VFRAME" |
| ], |
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| [ |
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| ], |
| [ |
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| "VFRAME_EE2A2" |
| ], |
| [ |
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| "VFRAME_EE2A3" |
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| ], |
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| "VFRAME_EE2BEG1" |
| ], |
| [ |
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| "VFRAME_EE2BEG2" |
| ], |
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| ], |
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| ], |
| [ |
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| ], |
| [ |
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| "VFRAME_EE4A3" |
| ], |
| [ |
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| "VFRAME_EE4B0" |
| ], |
| [ |
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| "VFRAME_EE4B1" |
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| [ |
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| "VFRAME_EE4B2" |
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| [ |
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| "VFRAME_EE4B3" |
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| "VFRAME_EE4BEG0" |
| ], |
| [ |
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| [ |
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| "VFRAME_EE4BEG3" |
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| "VFRAME_EL1BEG2" |
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| "VFRAME_EL1BEG3" |
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| "VFRAME_ER1BEG3" |
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| "VFRAME_LH1" |
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| [ |
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| "VFRAME_LH10" |
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| [ |
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| "VFRAME_LH11" |
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| [ |
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| "VFRAME_LH12" |
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| [ |
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| "VFRAME_LH2" |
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| [ |
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| "VFRAME_LH3" |
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| [ |
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| "VFRAME_LH4" |
| ], |
| [ |
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| "VFRAME_LH5" |
| ], |
| [ |
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| "VFRAME_LH6" |
| ], |
| [ |
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| "VFRAME_LH7" |
| ], |
| [ |
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| "VFRAME_LH8" |
| ], |
| [ |
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| "VFRAME_LH9" |
| ], |
| [ |
| "CLBLL_NE2A0", |
| "VFRAME_NE2A0" |
| ], |
| [ |
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| "VFRAME_NE2A1" |
| ], |
| [ |
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| "VFRAME_NE2A2" |
| ], |
| [ |
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| "VFRAME_NE2A3" |
| ], |
| [ |
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| "VFRAME_NE4BEG0" |
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| [ |
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| "VFRAME_NE4BEG1" |
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| [ |
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| "VFRAME_NE4BEG2" |
| ], |
| [ |
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| "VFRAME_NE4BEG3" |
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| "VFRAME_NE4C0" |
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| [ |
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| "VFRAME_NE4C1" |
| ], |
| [ |
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| "VFRAME_NE4C2" |
| ], |
| [ |
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| "VFRAME_NE4C3" |
| ], |
| [ |
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| "VFRAME_NW2A0" |
| ], |
| [ |
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| "VFRAME_NW2A1" |
| ], |
| [ |
| "CLBLL_NW2A2", |
| "VFRAME_NW2A2" |
| ], |
| [ |
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| "VFRAME_NW2A3" |
| ], |
| [ |
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| "VFRAME_NW4A0" |
| ], |
| [ |
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| "VFRAME_NW4A1" |
| ], |
| [ |
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| "VFRAME_NW4A2" |
| ], |
| [ |
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| "VFRAME_NW4A3" |
| ], |
| [ |
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| "VFRAME_NW4END0" |
| ], |
| [ |
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| "VFRAME_NW4END1" |
| ], |
| [ |
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| "VFRAME_NW4END2" |
| ], |
| [ |
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| "VFRAME_NW4END3" |
| ], |
| [ |
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| "VFRAME_SE2A0" |
| ], |
| [ |
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| "VFRAME_SE2A1" |
| ], |
| [ |
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| "VFRAME_SE2A2" |
| ], |
| [ |
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| "VFRAME_SE2A3" |
| ], |
| [ |
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| "VFRAME_SE4BEG0" |
| ], |
| [ |
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| "VFRAME_SE4BEG1" |
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| [ |
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| "VFRAME_SE4BEG2" |
| ], |
| [ |
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| "VFRAME_SE4BEG3" |
| ], |
| [ |
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| "VFRAME_SE4C0" |
| ], |
| [ |
| "CLBLL_SE4C1", |
| "VFRAME_SE4C1" |
| ], |
| [ |
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| "VFRAME_SE4C2" |
| ], |
| [ |
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| "VFRAME_SE4C3" |
| ], |
| [ |
| "CLBLL_SW2A0", |
| "VFRAME_SW2A0" |
| ], |
| [ |
| "CLBLL_SW2A1", |
| "VFRAME_SW2A1" |
| ], |
| [ |
| "CLBLL_SW2A2", |
| "VFRAME_SW2A2" |
| ], |
| [ |
| "CLBLL_SW2A3", |
| "VFRAME_SW2A3" |
| ], |
| [ |
| "CLBLL_SW4A0", |
| "VFRAME_SW4A0" |
| ], |
| [ |
| "CLBLL_SW4A1", |
| "VFRAME_SW4A1" |
| ], |
| [ |
| "CLBLL_SW4A2", |
| "VFRAME_SW4A2" |
| ], |
| [ |
| "CLBLL_SW4A3", |
| "VFRAME_SW4A3" |
| ], |
| [ |
| "CLBLL_SW4END0", |
| "VFRAME_SW4END0" |
| ], |
| [ |
| "CLBLL_SW4END1", |
| "VFRAME_SW4END1" |
| ], |
| [ |
| "CLBLL_SW4END2", |
| "VFRAME_SW4END2" |
| ], |
| [ |
| "CLBLL_SW4END3", |
| "VFRAME_SW4END3" |
| ], |
| [ |
| "CLBLL_WL1END0", |
| "VFRAME_WL1END0" |
| ], |
| [ |
| "CLBLL_WL1END1", |
| "VFRAME_WL1END1" |
| ], |
| [ |
| "CLBLL_WL1END2", |
| "VFRAME_WL1END2" |
| ], |
| [ |
| "CLBLL_WL1END3", |
| "VFRAME_WL1END3" |
| ], |
| [ |
| "CLBLL_WR1END0", |
| "VFRAME_WR1END0" |
| ], |
| [ |
| "CLBLL_WR1END1", |
| "VFRAME_WR1END1" |
| ], |
| [ |
| "CLBLL_WR1END2", |
| "VFRAME_WR1END2" |
| ], |
| [ |
| "CLBLL_WR1END3", |
| "VFRAME_WR1END3" |
| ], |
| [ |
| "CLBLL_WW2A0", |
| "VFRAME_WW2A0" |
| ], |
| [ |
| "CLBLL_WW2A1", |
| "VFRAME_WW2A1" |
| ], |
| [ |
| "CLBLL_WW2A2", |
| "VFRAME_WW2A2" |
| ], |
| [ |
| "CLBLL_WW2A3", |
| "VFRAME_WW2A3" |
| ], |
| [ |
| "CLBLL_WW2END0", |
| "VFRAME_WW2END0" |
| ], |
| [ |
| "CLBLL_WW2END1", |
| "VFRAME_WW2END1" |
| ], |
| [ |
| "CLBLL_WW2END2", |
| "VFRAME_WW2END2" |
| ], |
| [ |
| "CLBLL_WW2END3", |
| "VFRAME_WW2END3" |
| ], |
| [ |
| "CLBLL_WW4A0", |
| "VFRAME_WW4A0" |
| ], |
| [ |
| "CLBLL_WW4A1", |
| "VFRAME_WW4A1" |
| ], |
| [ |
| "CLBLL_WW4A2", |
| "VFRAME_WW4A2" |
| ], |
| [ |
| "CLBLL_WW4A3", |
| "VFRAME_WW4A3" |
| ], |
| [ |
| "CLBLL_WW4B0", |
| "VFRAME_WW4B0" |
| ], |
| [ |
| "CLBLL_WW4B1", |
| "VFRAME_WW4B1" |
| ], |
| [ |
| "CLBLL_WW4B2", |
| "VFRAME_WW4B2" |
| ], |
| [ |
| "CLBLL_WW4B3", |
| "VFRAME_WW4B3" |
| ], |
| [ |
| "CLBLL_WW4C0", |
| "VFRAME_WW4C0" |
| ], |
| [ |
| "CLBLL_WW4C1", |
| "VFRAME_WW4C1" |
| ], |
| [ |
| "CLBLL_WW4C2", |
| "VFRAME_WW4C2" |
| ], |
| [ |
| "CLBLL_WW4C3", |
| "VFRAME_WW4C3" |
| ], |
| [ |
| "CLBLL_WW4END0", |
| "VFRAME_WW4END0" |
| ], |
| [ |
| "CLBLL_WW4END1", |
| "VFRAME_WW4END1" |
| ], |
| [ |
| "CLBLL_WW4END2", |
| "VFRAME_WW4END2" |
| ], |
| [ |
| "CLBLL_WW4END3", |
| "VFRAME_WW4END3" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLM_L", |
| "BRKH_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_L_CIN", |
| "BRKH_CLB_COUT1_L" |
| ], |
| [ |
| "CLBLM_M_CIN", |
| "BRKH_CLB_COUT0_L" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLM_L", |
| "CLBLM_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_L_CIN", |
| "CLBLM_L_COUT_N" |
| ], |
| [ |
| "CLBLM_M_CIN", |
| "CLBLM_M_COUT_N" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLM_L", |
| "HCLK_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_L_CIN", |
| "HCLK_CLB_COUT1_L" |
| ], |
| [ |
| "CLBLM_M_CIN", |
| "HCLK_CLB_COUT0_L" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "CLBLM_L", |
| "INT_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_BYP0", |
| "BYP_L0" |
| ], |
| [ |
| "CLBLM_BYP1", |
| "BYP_L1" |
| ], |
| [ |
| "CLBLM_BYP2", |
| "BYP_L2" |
| ], |
| [ |
| "CLBLM_BYP3", |
| "BYP_L3" |
| ], |
| [ |
| "CLBLM_BYP4", |
| "BYP_L4" |
| ], |
| [ |
| "CLBLM_BYP5", |
| "BYP_L5" |
| ], |
| [ |
| "CLBLM_BYP6", |
| "BYP_L6" |
| ], |
| [ |
| "CLBLM_BYP7", |
| "BYP_L7" |
| ], |
| [ |
| "CLBLM_CLK0", |
| "CLK_L0" |
| ], |
| [ |
| "CLBLM_CLK1", |
| "CLK_L1" |
| ], |
| [ |
| "CLBLM_CTRL0", |
| "CTRL_L0" |
| ], |
| [ |
| "CLBLM_CTRL1", |
| "CTRL_L1" |
| ], |
| [ |
| "CLBLM_EE2A0", |
| "EE2END0" |
| ], |
| [ |
| "CLBLM_EE2A1", |
| "EE2END1" |
| ], |
| [ |
| "CLBLM_EE2A2", |
| "EE2END2" |
| ], |
| [ |
| "CLBLM_EE2A3", |
| "EE2END3" |
| ], |
| [ |
| "CLBLM_EE2BEG0", |
| "EE2A0" |
| ], |
| [ |
| "CLBLM_EE2BEG1", |
| "EE2A1" |
| ], |
| [ |
| "CLBLM_EE2BEG2", |
| "EE2A2" |
| ], |
| [ |
| "CLBLM_EE2BEG3", |
| "EE2A3" |
| ], |
| [ |
| "CLBLM_EE4A0", |
| "EE4B0" |
| ], |
| [ |
| "CLBLM_EE4A1", |
| "EE4B1" |
| ], |
| [ |
| "CLBLM_EE4A2", |
| "EE4B2" |
| ], |
| [ |
| "CLBLM_EE4A3", |
| "EE4B3" |
| ], |
| [ |
| "CLBLM_EE4B0", |
| "EE4C0" |
| ], |
| [ |
| "CLBLM_EE4B1", |
| "EE4C1" |
| ], |
| [ |
| "CLBLM_EE4B2", |
| "EE4C2" |
| ], |
| [ |
| "CLBLM_EE4B3", |
| "EE4C3" |
| ], |
| [ |
| "CLBLM_EE4BEG0", |
| "EE4A0" |
| ], |
| [ |
| "CLBLM_EE4BEG1", |
| "EE4A1" |
| ], |
| [ |
| "CLBLM_EE4BEG2", |
| "EE4A2" |
| ], |
| [ |
| "CLBLM_EE4BEG3", |
| "EE4A3" |
| ], |
| [ |
| "CLBLM_EE4C0", |
| "EE4END0" |
| ], |
| [ |
| "CLBLM_EE4C1", |
| "EE4END1" |
| ], |
| [ |
| "CLBLM_EE4C2", |
| "EE4END2" |
| ], |
| [ |
| "CLBLM_EE4C3", |
| "EE4END3" |
| ], |
| [ |
| "CLBLM_EL1BEG0", |
| "EL1END0" |
| ], |
| [ |
| "CLBLM_EL1BEG1", |
| "EL1END1" |
| ], |
| [ |
| "CLBLM_EL1BEG2", |
| "EL1END2" |
| ], |
| [ |
| "CLBLM_EL1BEG3", |
| "EL1END3" |
| ], |
| [ |
| "CLBLM_ER1BEG0", |
| "ER1END0" |
| ], |
| [ |
| "CLBLM_ER1BEG1", |
| "ER1END1" |
| ], |
| [ |
| "CLBLM_ER1BEG2", |
| "ER1END2" |
| ], |
| [ |
| "CLBLM_FAN0", |
| "FAN_L0" |
| ], |
| [ |
| "CLBLM_FAN1", |
| "FAN_L1" |
| ], |
| [ |
| "CLBLM_FAN2", |
| "FAN_L2" |
| ], |
| [ |
| "CLBLM_FAN3", |
| "FAN_L3" |
| ], |
| [ |
| "CLBLM_FAN4", |
| "FAN_L4" |
| ], |
| [ |
| "CLBLM_FAN5", |
| "FAN_L5" |
| ], |
| [ |
| "CLBLM_FAN6", |
| "FAN_L6" |
| ], |
| [ |
| "CLBLM_FAN7", |
| "FAN_L7" |
| ], |
| [ |
| "CLBLM_IMUX0", |
| "IMUX_L0" |
| ], |
| [ |
| "CLBLM_IMUX1", |
| "IMUX_L1" |
| ], |
| [ |
| "CLBLM_IMUX10", |
| "IMUX_L10" |
| ], |
| [ |
| "CLBLM_IMUX11", |
| "IMUX_L11" |
| ], |
| [ |
| "CLBLM_IMUX12", |
| "IMUX_L12" |
| ], |
| [ |
| "CLBLM_IMUX13", |
| "IMUX_L13" |
| ], |
| [ |
| "CLBLM_IMUX14", |
| "IMUX_L14" |
| ], |
| [ |
| "CLBLM_IMUX15", |
| "IMUX_L15" |
| ], |
| [ |
| "CLBLM_IMUX16", |
| "IMUX_L16" |
| ], |
| [ |
| "CLBLM_IMUX17", |
| "IMUX_L17" |
| ], |
| [ |
| "CLBLM_IMUX18", |
| "IMUX_L18" |
| ], |
| [ |
| "CLBLM_IMUX19", |
| "IMUX_L19" |
| ], |
| [ |
| "CLBLM_IMUX2", |
| "IMUX_L2" |
| ], |
| [ |
| "CLBLM_IMUX20", |
| "IMUX_L20" |
| ], |
| [ |
| "CLBLM_IMUX21", |
| "IMUX_L21" |
| ], |
| [ |
| "CLBLM_IMUX22", |
| "IMUX_L22" |
| ], |
| [ |
| "CLBLM_IMUX23", |
| "IMUX_L23" |
| ], |
| [ |
| "CLBLM_IMUX24", |
| "IMUX_L24" |
| ], |
| [ |
| "CLBLM_IMUX25", |
| "IMUX_L25" |
| ], |
| [ |
| "CLBLM_IMUX26", |
| "IMUX_L26" |
| ], |
| [ |
| "CLBLM_IMUX27", |
| "IMUX_L27" |
| ], |
| [ |
| "CLBLM_IMUX28", |
| "IMUX_L28" |
| ], |
| [ |
| "CLBLM_IMUX29", |
| "IMUX_L29" |
| ], |
| [ |
| "CLBLM_IMUX3", |
| "IMUX_L3" |
| ], |
| [ |
| "CLBLM_IMUX30", |
| "IMUX_L30" |
| ], |
| [ |
| "CLBLM_IMUX31", |
| "IMUX_L31" |
| ], |
| [ |
| "CLBLM_IMUX32", |
| "IMUX_L32" |
| ], |
| [ |
| "CLBLM_IMUX33", |
| "IMUX_L33" |
| ], |
| [ |
| "CLBLM_IMUX34", |
| "IMUX_L34" |
| ], |
| [ |
| "CLBLM_IMUX35", |
| "IMUX_L35" |
| ], |
| [ |
| "CLBLM_IMUX36", |
| "IMUX_L36" |
| ], |
| [ |
| "CLBLM_IMUX37", |
| "IMUX_L37" |
| ], |
| [ |
| "CLBLM_IMUX38", |
| "IMUX_L38" |
| ], |
| [ |
| "CLBLM_IMUX39", |
| "IMUX_L39" |
| ], |
| [ |
| "CLBLM_IMUX4", |
| "IMUX_L4" |
| ], |
| [ |
| "CLBLM_IMUX40", |
| "IMUX_L40" |
| ], |
| [ |
| "CLBLM_IMUX41", |
| "IMUX_L41" |
| ], |
| [ |
| "CLBLM_IMUX42", |
| "IMUX_L42" |
| ], |
| [ |
| "CLBLM_IMUX43", |
| "IMUX_L43" |
| ], |
| [ |
| "CLBLM_IMUX44", |
| "IMUX_L44" |
| ], |
| [ |
| "CLBLM_IMUX45", |
| "IMUX_L45" |
| ], |
| [ |
| "CLBLM_IMUX46", |
| "IMUX_L46" |
| ], |
| [ |
| "CLBLM_IMUX47", |
| "IMUX_L47" |
| ], |
| [ |
| "CLBLM_IMUX5", |
| "IMUX_L5" |
| ], |
| [ |
| "CLBLM_IMUX6", |
| "IMUX_L6" |
| ], |
| [ |
| "CLBLM_IMUX7", |
| "IMUX_L7" |
| ], |
| [ |
| "CLBLM_IMUX8", |
| "IMUX_L8" |
| ], |
| [ |
| "CLBLM_IMUX9", |
| "IMUX_L9" |
| ], |
| [ |
| "CLBLM_LH1", |
| "LH0" |
| ], |
| [ |
| "CLBLM_LH10", |
| "LH9" |
| ], |
| [ |
| "CLBLM_LH11", |
| "LH10" |
| ], |
| [ |
| "CLBLM_LH12", |
| "LH11" |
| ], |
| [ |
| "CLBLM_LH2", |
| "LH1" |
| ], |
| [ |
| "CLBLM_LH3", |
| "LH2" |
| ], |
| [ |
| "CLBLM_LH4", |
| "LH3" |
| ], |
| [ |
| "CLBLM_LH5", |
| "LH4" |
| ], |
| [ |
| "CLBLM_LH6", |
| "LH5" |
| ], |
| [ |
| "CLBLM_LH7", |
| "LH6" |
| ], |
| [ |
| "CLBLM_LH8", |
| "LH7" |
| ], |
| [ |
| "CLBLM_LH9", |
| "LH8" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS0", |
| "LOGIC_OUTS_L0" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS1", |
| "LOGIC_OUTS_L1" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS10", |
| "LOGIC_OUTS_L10" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS11", |
| "LOGIC_OUTS_L11" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS12", |
| "LOGIC_OUTS_L12" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS13", |
| "LOGIC_OUTS_L13" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS14", |
| "LOGIC_OUTS_L14" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS15", |
| "LOGIC_OUTS_L15" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS16", |
| "LOGIC_OUTS_L16" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS17", |
| "LOGIC_OUTS_L17" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS18", |
| "LOGIC_OUTS_L18" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS19", |
| "LOGIC_OUTS_L19" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS2", |
| "LOGIC_OUTS_L2" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS20", |
| "LOGIC_OUTS_L20" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS21", |
| "LOGIC_OUTS_L21" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS22", |
| "LOGIC_OUTS_L22" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS23", |
| "LOGIC_OUTS_L23" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS3", |
| "LOGIC_OUTS_L3" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS4", |
| "LOGIC_OUTS_L4" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS5", |
| "LOGIC_OUTS_L5" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS6", |
| "LOGIC_OUTS_L6" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS7", |
| "LOGIC_OUTS_L7" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS8", |
| "LOGIC_OUTS_L8" |
| ], |
| [ |
| "CLBLM_LOGIC_OUTS9", |
| "LOGIC_OUTS_L9" |
| ], |
| [ |
| "CLBLM_NE2A0", |
| "NE2END0" |
| ], |
| [ |
| "CLBLM_NE2A1", |
| "NE2END1" |
| ], |
| [ |
| "CLBLM_NE2A2", |
| "NE2END2" |
| ], |
| [ |
| "CLBLM_NE2A3", |
| "NE2END3" |
| ], |
| [ |
| "CLBLM_NE4C0", |
| "NE6END0" |
| ], |
| [ |
| "CLBLM_NE4C1", |
| "NE6END1" |
| ], |
| [ |
| "CLBLM_NE4C2", |
| "NE6END2" |
| ], |
| [ |
| "CLBLM_NE4C3", |
| "NE6END3" |
| ], |
| [ |
| "CLBLM_NW2A0", |
| "NW2A0" |
| ], |
| [ |
| "CLBLM_NW2A1", |
| "NW2A1" |
| ], |
| [ |
| "CLBLM_NW2A2", |
| "NW2A2" |
| ], |
| [ |
| "CLBLM_NW2A3", |
| "NW2A3" |
| ], |
| [ |
| "CLBLM_NW4A0", |
| "NW6BEG0" |
| ], |
| [ |
| "CLBLM_NW4A1", |
| "NW6BEG1" |
| ], |
| [ |
| "CLBLM_NW4A2", |
| "NW6BEG2" |
| ], |
| [ |
| "CLBLM_NW4A3", |
| "NW6BEG3" |
| ], |
| [ |
| "CLBLM_NW4END0", |
| "NW6E0" |
| ], |
| [ |
| "CLBLM_NW4END1", |
| "NW6E1" |
| ], |
| [ |
| "CLBLM_NW4END2", |
| "NW6E2" |
| ], |
| [ |
| "CLBLM_NW4END3", |
| "NW6E3" |
| ], |
| [ |
| "CLBLM_SE2A0", |
| "SE2END0" |
| ], |
| [ |
| "CLBLM_SE2A1", |
| "SE2END1" |
| ], |
| [ |
| "CLBLM_SE2A2", |
| "SE2END2" |
| ], |
| [ |
| "CLBLM_SE2A3", |
| "SE2END3" |
| ], |
| [ |
| "CLBLM_SE4BEG0", |
| "SE6A0" |
| ], |
| [ |
| "CLBLM_SE4BEG1", |
| "SE6A1" |
| ], |
| [ |
| "CLBLM_SE4BEG2", |
| "SE6A2" |
| ], |
| [ |
| "CLBLM_SE4BEG3", |
| "SE6A3" |
| ], |
| [ |
| "CLBLM_SE4C0", |
| "SE6END0" |
| ], |
| [ |
| "CLBLM_SE4C1", |
| "SE6END1" |
| ], |
| [ |
| "CLBLM_SE4C2", |
| "SE6END2" |
| ], |
| [ |
| "CLBLM_SE4C3", |
| "SE6END3" |
| ], |
| [ |
| "CLBLM_SW2A0", |
| "SW2A0" |
| ], |
| [ |
| "CLBLM_SW2A1", |
| "SW2A1" |
| ], |
| [ |
| "CLBLM_SW2A2", |
| "SW2A2" |
| ], |
| [ |
| "CLBLM_SW2A3", |
| "SW2A3" |
| ], |
| [ |
| "CLBLM_SW4A0", |
| "SW6BEG0" |
| ], |
| [ |
| "CLBLM_SW4A1", |
| "SW6BEG1" |
| ], |
| [ |
| "CLBLM_SW4A2", |
| "SW6BEG2" |
| ], |
| [ |
| "CLBLM_SW4A3", |
| "SW6BEG3" |
| ], |
| [ |
| "CLBLM_SW4END0", |
| "SW6E0" |
| ], |
| [ |
| "CLBLM_SW4END1", |
| "SW6E1" |
| ], |
| [ |
| "CLBLM_SW4END2", |
| "SW6E2" |
| ], |
| [ |
| "CLBLM_SW4END3", |
| "SW6E3" |
| ], |
| [ |
| "CLBLM_WL1END0", |
| "WL1BEG0" |
| ], |
| [ |
| "CLBLM_WL1END1", |
| "WL1BEG1" |
| ], |
| [ |
| "CLBLM_WL1END2", |
| "WL1BEG2" |
| ], |
| [ |
| "CLBLM_WL1END3", |
| "WL1BEG3" |
| ], |
| [ |
| "CLBLM_WR1END0", |
| "WR1BEG0" |
| ], |
| [ |
| "CLBLM_WR1END1", |
| "WR1BEG1" |
| ], |
| [ |
| "CLBLM_WR1END2", |
| "WR1BEG2" |
| ], |
| [ |
| "CLBLM_WR1END3", |
| "WR1BEG3" |
| ], |
| [ |
| "CLBLM_WW2A0", |
| "WW2BEG0" |
| ], |
| [ |
| "CLBLM_WW2A1", |
| "WW2BEG1" |
| ], |
| [ |
| "CLBLM_WW2A2", |
| "WW2BEG2" |
| ], |
| [ |
| "CLBLM_WW2A3", |
| "WW2BEG3" |
| ], |
| [ |
| "CLBLM_WW2END0", |
| "WW2A0" |
| ], |
| [ |
| "CLBLM_WW2END1", |
| "WW2A1" |
| ], |
| [ |
| "CLBLM_WW2END2", |
| "WW2A2" |
| ], |
| [ |
| "CLBLM_WW2END3", |
| "WW2A3" |
| ], |
| [ |
| "CLBLM_WW4A0", |
| "WW4BEG0" |
| ], |
| [ |
| "CLBLM_WW4A1", |
| "WW4BEG1" |
| ], |
| [ |
| "CLBLM_WW4A2", |
| "WW4BEG2" |
| ], |
| [ |
| "CLBLM_WW4A3", |
| "WW4BEG3" |
| ], |
| [ |
| "CLBLM_WW4B0", |
| "WW4A0" |
| ], |
| [ |
| "CLBLM_WW4B1", |
| "WW4A1" |
| ], |
| [ |
| "CLBLM_WW4B2", |
| "WW4A2" |
| ], |
| [ |
| "CLBLM_WW4B3", |
| "WW4A3" |
| ], |
| [ |
| "CLBLM_WW4C0", |
| "WW4B0" |
| ], |
| [ |
| "CLBLM_WW4C1", |
| "WW4B1" |
| ], |
| [ |
| "CLBLM_WW4C2", |
| "WW4B2" |
| ], |
| [ |
| "CLBLM_WW4C3", |
| "WW4B3" |
| ], |
| [ |
| "CLBLM_WW4END0", |
| "WW4C0" |
| ], |
| [ |
| "CLBLM_WW4END1", |
| "WW4C1" |
| ], |
| [ |
| "CLBLM_WW4END2", |
| "WW4C2" |
| ], |
| [ |
| "CLBLM_WW4END3", |
| "WW4C3" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLM_R", |
| "BRKH_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_L_CIN", |
| "BRKH_CLB_COUT0_R" |
| ], |
| [ |
| "CLBLM_M_CIN", |
| "BRKH_CLB_COUT1_R" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLM_R", |
| "CLBLM_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_L_CIN", |
| "CLBLM_L_COUT_N" |
| ], |
| [ |
| "CLBLM_M_CIN", |
| "CLBLM_M_COUT_N" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "CLBLM_R", |
| "HCLK_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_L_CIN", |
| "HCLK_CLB_COUT0_R" |
| ], |
| [ |
| "CLBLM_M_CIN", |
| "HCLK_CLB_COUT1_R" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "CLBLM_R", |
| "VBRK" |
| ], |
| "wire_pairs": [ |
| [ |
| "CLBLM_EE2A0", |
| "VBRK_EE2A0" |
| ], |
| [ |
| "CLBLM_EE2A1", |
| "VBRK_EE2A1" |
| ], |
| [ |
| "CLBLM_EE2A2", |
| "VBRK_EE2A2" |
| ], |
| [ |
| "CLBLM_EE2A3", |
| "VBRK_EE2A3" |
| ], |
| [ |
| "CLBLM_EE2BEG0", |
| "VBRK_EE2BEG0" |
| ], |
| [ |
| "CLBLM_EE2BEG1", |
| "VBRK_EE2BEG1" |
| ], |
| [ |
| "CLBLM_EE2BEG2", |
| "VBRK_EE2BEG2" |
| ], |
| [ |
| "CLBLM_EE2BEG3", |
| "VBRK_EE2BEG3" |
| ], |
| [ |
| "CLBLM_EE4A0", |
| "VBRK_EE4A0" |
| ], |
| [ |
| "CLBLM_EE4A1", |
| "VBRK_EE4A1" |
| ], |
| [ |
| "CLBLM_EE4A2", |
| "VBRK_EE4A2" |
| ], |
| [ |
| "CLBLM_EE4A3", |
| "VBRK_EE4A3" |
| ], |
| [ |
| "CLBLM_EE4B0", |
| "VBRK_EE4B0" |
| ], |
| [ |
| "CLBLM_EE4B1", |
| "VBRK_EE4B1" |
| ], |
| [ |
| "CLBLM_EE4B2", |
| "VBRK_EE4B2" |
| ], |
| [ |
| "CLBLM_EE4B3", |
| "VBRK_EE4B3" |
| ], |
| [ |
| "CLBLM_EE4BEG0", |
| "VBRK_EE4BEG0" |
| ], |
| [ |
| "CLBLM_EE4BEG1", |
| "VBRK_EE4BEG1" |
| ], |
| [ |
| "CLBLM_EE4BEG2", |
| "VBRK_EE4BEG2" |
| ], |
| [ |
| "CLBLM_EE4BEG3", |
| "VBRK_EE4BEG3" |
| ], |
| [ |
| "CLBLM_EE4C0", |
| "VBRK_EE4C0" |
| ], |
| [ |
| "CLBLM_EE4C1", |
| "VBRK_EE4C1" |
| ], |
| [ |
| "CLBLM_EE4C2", |
| "VBRK_EE4C2" |
| ], |
| [ |
| "CLBLM_EE4C3", |
| "VBRK_EE4C3" |
| ], |
| [ |
| "CLBLM_EL1BEG0", |
| "VBRK_EL1BEG0" |
| ], |
| [ |
| "CLBLM_EL1BEG1", |
| "VBRK_EL1BEG1" |
| ], |
| [ |
| "CLBLM_EL1BEG2", |
| "VBRK_EL1BEG2" |
| ], |
| [ |
| "CLBLM_EL1BEG3", |
| "VBRK_EL1BEG3" |
| ], |
| [ |
| "CLBLM_ER1BEG0", |
| "VBRK_ER1BEG0" |
| ], |
| [ |
| "CLBLM_ER1BEG1", |
| "VBRK_ER1BEG1" |
| ], |
| [ |
| "CLBLM_ER1BEG2", |
| "VBRK_ER1BEG2" |
| ], |
| [ |
| "CLBLM_ER1BEG3", |
| "VBRK_ER1BEG3" |
| ], |
| [ |
| "CLBLM_LH1", |
| "VBRK_LH1" |
| ], |
| [ |
| "CLBLM_LH10", |
| "VBRK_LH10" |
| ], |
| [ |
| "CLBLM_LH11", |
| "VBRK_LH11" |
| ], |
| [ |
| "CLBLM_LH12", |
| "VBRK_LH12" |
| ], |
| [ |
| "CLBLM_LH2", |
| "VBRK_LH2" |
| ], |
| [ |
| "CLBLM_LH3", |
| "VBRK_LH3" |
| ], |
| [ |
| "CLBLM_LH4", |
| "VBRK_LH4" |
| ], |
| [ |
| "CLBLM_LH5", |
| "VBRK_LH5" |
| ], |
| [ |
| "CLBLM_LH6", |
| "VBRK_LH6" |
| ], |
| [ |
| "CLBLM_LH7", |
| "VBRK_LH7" |
| ], |
| [ |
| "CLBLM_LH8", |
| "VBRK_LH8" |
| ], |
| [ |
| "CLBLM_LH9", |
| "VBRK_LH9" |
| ], |
| [ |
| "CLBLM_NE2A0", |
| "VBRK_NE2A0" |
| ], |
| [ |
| "CLBLM_NE2A1", |
| "VBRK_NE2A1" |
| ], |
| [ |
| "CLBLM_NE2A2", |
| "VBRK_NE2A2" |
| ], |
| [ |
| "CLBLM_NE2A3", |
| "VBRK_NE2A3" |
| ], |
| [ |
| "CLBLM_NE4BEG0", |
| "VBRK_NE4BEG0" |
| ], |
| [ |
| "CLBLM_NE4BEG1", |
| "VBRK_NE4BEG1" |
| ], |
| [ |
| "CLBLM_NE4BEG2", |
| "VBRK_NE4BEG2" |
| ], |
| [ |
| "CLBLM_NE4BEG3", |
| "VBRK_NE4BEG3" |
| ], |
| [ |
| "CLBLM_NE4C0", |
| "VBRK_NE4C0" |
| ], |
| [ |
| "CLBLM_NE4C1", |
| "VBRK_NE4C1" |
| ], |
| [ |
| "CLBLM_NE4C2", |
| "VBRK_NE4C2" |
| ], |
| [ |
| "CLBLM_NE4C3", |
| "VBRK_NE4C3" |
| ], |
| [ |
| "CLBLM_NW2A0", |
| "VBRK_NW2A0" |
| ], |
| [ |
| "CLBLM_NW2A1", |
| "VBRK_NW2A1" |
| ], |
| [ |
| "CLBLM_NW2A2", |
| "VBRK_NW2A2" |
| ], |
| [ |
| "CLBLM_NW2A3", |
| "VBRK_NW2A3" |
| ], |
| [ |
| "CLBLM_NW4A0", |
| "VBRK_NW4A0" |
| ], |
| [ |
| "CLBLM_NW4A1", |
| "VBRK_NW4A1" |
| ], |
| [ |
| "CLBLM_NW4A2", |
| "VBRK_NW4A2" |
| ], |
| [ |
| "CLBLM_NW4A3", |
| "VBRK_NW4A3" |
| ], |
| [ |
| "CLBLM_NW4END0", |
| "VBRK_NW4END0" |
| ], |
| [ |
| "CLBLM_NW4END1", |
| "VBRK_NW4END1" |
| ], |
| [ |
| "CLBLM_NW4END2", |
| "VBRK_NW4END2" |
| ], |
| [ |
| "CLBLM_NW4END3", |
| "VBRK_NW4END3" |
| ], |
| [ |
| "CLBLM_SE2A0", |
| "VBRK_SE2A0" |
| ], |
| [ |
| "CLBLM_SE2A1", |
| "VBRK_SE2A1" |
| ], |
| [ |
| "CLBLM_SE2A2", |
| "VBRK_SE2A2" |
| ], |
| [ |
| "CLBLM_SE2A3", |
| "VBRK_SE2A3" |
| ], |
| [ |
| "CLBLM_SE4BEG0", |
| "VBRK_SE4BEG0" |
| ], |
| [ |
| "CLBLM_SE4BEG1", |
| "VBRK_SE4BEG1" |
| ], |
| [ |
| "CLBLM_SE4BEG2", |
| "VBRK_SE4BEG2" |
| ], |
| [ |
| "CLBLM_SE4BEG3", |
| "VBRK_SE4BEG3" |
| ], |
| [ |
| "CLBLM_SE4C0", |
| "VBRK_SE4C0" |
| ], |
| [ |
| "CLBLM_SE4C1", |
| "VBRK_SE4C1" |
| ], |
| [ |
| "CLBLM_SE4C2", |
| "VBRK_SE4C2" |
| ], |
| [ |
| "CLBLM_SE4C3", |
| "VBRK_SE4C3" |
| ], |
| [ |
| "CLBLM_SW2A0", |
| "VBRK_SW2A0" |
| ], |
| [ |
| "CLBLM_SW2A1", |
| "VBRK_SW2A1" |
| ], |
| [ |
| "CLBLM_SW2A2", |
| "VBRK_SW2A2" |
| ], |
| [ |
| "CLBLM_SW2A3", |
| "VBRK_SW2A3" |
| ], |
| [ |
| "CLBLM_SW4A0", |
| "VBRK_SW4A0" |
| ], |
| [ |
| "CLBLM_SW4A1", |
| "VBRK_SW4A1" |
| ], |
| [ |
| "CLBLM_SW4A2", |
| "VBRK_SW4A2" |
| ], |
| [ |
| "CLBLM_SW4A3", |
| "VBRK_SW4A3" |
| ], |
| [ |
| "CLBLM_SW4END0", |
| "VBRK_SW4END0" |
| ], |
| [ |
| "CLBLM_SW4END1", |
| "VBRK_SW4END1" |
| ], |
| [ |
| "CLBLM_SW4END2", |
| "VBRK_SW4END2" |
| ], |
| [ |
| "CLBLM_SW4END3", |
| "VBRK_SW4END3" |
| ], |
| [ |
| "CLBLM_WL1END0", |
| "VBRK_WL1END0" |
| ], |
| [ |
| "CLBLM_WL1END1", |
| "VBRK_WL1END1" |
| ], |
| [ |
| "CLBLM_WL1END2", |
| "VBRK_WL1END2" |
| ], |
| [ |
| "CLBLM_WL1END3", |
| "VBRK_WL1END3" |
| ], |
| [ |
| "CLBLM_WR1END0", |
| "VBRK_WR1END0" |
| ], |
| [ |
| "CLBLM_WR1END1", |
| "VBRK_WR1END1" |
| ], |
| [ |
| "CLBLM_WR1END2", |
| "VBRK_WR1END2" |
| ], |
| [ |
| "CLBLM_WR1END3", |
| "VBRK_WR1END3" |
| ], |
| [ |
| "CLBLM_WW2A0", |
| "VBRK_WW2A0" |
| ], |
| [ |
| "CLBLM_WW2A1", |
| "VBRK_WW2A1" |
| ], |
| [ |
| "CLBLM_WW2A2", |
| "VBRK_WW2A2" |
| ], |
| [ |
| "CLBLM_WW2A3", |
| "VBRK_WW2A3" |
| ], |
| [ |
| "CLBLM_WW2END0", |
| "VBRK_WW2END0" |
| ], |
| [ |
| "CLBLM_WW2END1", |
| "VBRK_WW2END1" |
| ], |
| [ |
| "CLBLM_WW2END2", |
| "VBRK_WW2END2" |
| ], |
| [ |
| "CLBLM_WW2END3", |
| "VBRK_WW2END3" |
| ], |
| [ |
| "CLBLM_WW4A0", |
| "VBRK_WW4A0" |
| ], |
| [ |
| "CLBLM_WW4A1", |
| "VBRK_WW4A1" |
| ], |
| [ |
| "CLBLM_WW4A2", |
| "VBRK_WW4A2" |
| ], |
| [ |
| "CLBLM_WW4A3", |
| "VBRK_WW4A3" |
| ], |
| [ |
| "CLBLM_WW4B0", |
| "VBRK_WW4B0" |
| ], |
| [ |
| "CLBLM_WW4B1", |
| "VBRK_WW4B1" |
| ], |
| [ |
| "CLBLM_WW4B2", |
| "VBRK_WW4B2" |
| ], |
| [ |
| "CLBLM_WW4B3", |
| "VBRK_WW4B3" |
| ], |
| [ |
| "CLBLM_WW4C0", |
| "VBRK_WW4C0" |
| ], |
| [ |
| "CLBLM_WW4C1", |
| "VBRK_WW4C1" |
| ], |
| [ |
| "CLBLM_WW4C2", |
| "VBRK_WW4C2" |
| ], |
| [ |
| "CLBLM_WW4C3", |
| "VBRK_WW4C3" |
| ], |
| [ |
| "CLBLM_WW4END0", |
| "VBRK_WW4END0" |
| ], |
| [ |
| "CLBLM_WW4END1", |
| "VBRK_WW4END1" |
| ], |
| [ |
| "CLBLM_WW4END2", |
| "VBRK_WW4END2" |
| ], |
| [ |
| "CLBLM_WW4END3", |
| "VBRK_WW4END3" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "CLBLL_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_COUT0_L", |
| "CLBLL_LL_COUT_N" |
| ], |
| [ |
| "HCLK_CLB_COUT1_L", |
| "CLBLL_L_COUT_N" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "CLBLL_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_COUT0_R", |
| "CLBLL_L_COUT_N" |
| ], |
| [ |
| "HCLK_CLB_COUT1_R", |
| "CLBLL_LL_COUT_N" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "CLBLM_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_COUT0_L", |
| "CLBLM_M_COUT_N" |
| ], |
| [ |
| "HCLK_CLB_COUT1_L", |
| "CLBLM_L_COUT_N" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "CLBLM_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_COUT0_R", |
| "CLBLM_L_COUT_N" |
| ], |
| [ |
| "HCLK_CLB_COUT1_R", |
| "CLBLM_M_COUT_N" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "HCLK_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_CK_BUFHCLK0", |
| "HCLK_CLB_CK_BUFHCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK1", |
| "HCLK_CLB_CK_BUFHCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK10", |
| "HCLK_CLB_CK_BUFHCLK10" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK11", |
| "HCLK_CLB_CK_BUFHCLK11" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK2", |
| "HCLK_CLB_CK_BUFHCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK3", |
| "HCLK_CLB_CK_BUFHCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK4", |
| "HCLK_CLB_CK_BUFHCLK4" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK5", |
| "HCLK_CLB_CK_BUFHCLK5" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK6", |
| "HCLK_CLB_CK_BUFHCLK6" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK7", |
| "HCLK_CLB_CK_BUFHCLK7" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK8", |
| "HCLK_CLB_CK_BUFHCLK8" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK9", |
| "HCLK_CLB_CK_BUFHCLK9" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK0", |
| "HCLK_CLB_CK_BUFRCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK1", |
| "HCLK_CLB_CK_BUFRCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK2", |
| "HCLK_CLB_CK_BUFRCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK3", |
| "HCLK_CLB_CK_BUFRCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN0", |
| "HCLK_CLB_CK_IN0" |
| ], |
| [ |
| "HCLK_CLB_CK_IN1", |
| "HCLK_CLB_CK_IN1" |
| ], |
| [ |
| "HCLK_CLB_CK_IN10", |
| "HCLK_CLB_CK_IN10" |
| ], |
| [ |
| "HCLK_CLB_CK_IN11", |
| "HCLK_CLB_CK_IN11" |
| ], |
| [ |
| "HCLK_CLB_CK_IN12", |
| "HCLK_CLB_CK_IN12" |
| ], |
| [ |
| "HCLK_CLB_CK_IN13", |
| "HCLK_CLB_CK_IN13" |
| ], |
| [ |
| "HCLK_CLB_CK_IN2", |
| "HCLK_CLB_CK_IN2" |
| ], |
| [ |
| "HCLK_CLB_CK_IN3", |
| "HCLK_CLB_CK_IN3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN4", |
| "HCLK_CLB_CK_IN4" |
| ], |
| [ |
| "HCLK_CLB_CK_IN5", |
| "HCLK_CLB_CK_IN5" |
| ], |
| [ |
| "HCLK_CLB_CK_IN6", |
| "HCLK_CLB_CK_IN6" |
| ], |
| [ |
| "HCLK_CLB_CK_IN7", |
| "HCLK_CLB_CK_IN7" |
| ], |
| [ |
| "HCLK_CLB_CK_IN8", |
| "HCLK_CLB_CK_IN8" |
| ], |
| [ |
| "HCLK_CLB_CK_IN9", |
| "HCLK_CLB_CK_IN9" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "HCLK_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_CK_BUFHCLK0", |
| "HCLK_CK_BUFHCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK1", |
| "HCLK_CK_BUFHCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK10", |
| "HCLK_CK_BUFHCLK10" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK11", |
| "HCLK_CK_BUFHCLK11" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK2", |
| "HCLK_CK_BUFHCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK3", |
| "HCLK_CK_BUFHCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK4", |
| "HCLK_CK_BUFHCLK4" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK5", |
| "HCLK_CK_BUFHCLK5" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK6", |
| "HCLK_CK_BUFHCLK6" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK7", |
| "HCLK_CK_BUFHCLK7" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK8", |
| "HCLK_CK_BUFHCLK8" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK9", |
| "HCLK_CK_BUFHCLK9" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK0", |
| "HCLK_CK_BUFRCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK1", |
| "HCLK_CK_BUFRCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK2", |
| "HCLK_CK_BUFRCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK3", |
| "HCLK_CK_BUFRCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN0", |
| "HCLK_CK_IN0" |
| ], |
| [ |
| "HCLK_CLB_CK_IN1", |
| "HCLK_CK_IN1" |
| ], |
| [ |
| "HCLK_CLB_CK_IN10", |
| "HCLK_CK_IN10" |
| ], |
| [ |
| "HCLK_CLB_CK_IN11", |
| "HCLK_CK_IN11" |
| ], |
| [ |
| "HCLK_CLB_CK_IN12", |
| "HCLK_CK_IN12" |
| ], |
| [ |
| "HCLK_CLB_CK_IN13", |
| "HCLK_CK_IN13" |
| ], |
| [ |
| "HCLK_CLB_CK_IN2", |
| "HCLK_CK_IN2" |
| ], |
| [ |
| "HCLK_CLB_CK_IN3", |
| "HCLK_CK_IN3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN4", |
| "HCLK_CK_IN4" |
| ], |
| [ |
| "HCLK_CLB_CK_IN5", |
| "HCLK_CK_IN5" |
| ], |
| [ |
| "HCLK_CLB_CK_IN6", |
| "HCLK_CK_IN6" |
| ], |
| [ |
| "HCLK_CLB_CK_IN7", |
| "HCLK_CK_IN7" |
| ], |
| [ |
| "HCLK_CLB_CK_IN8", |
| "HCLK_CK_IN8" |
| ], |
| [ |
| "HCLK_CLB_CK_IN9", |
| "HCLK_CK_IN9" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "HCLK_VBRK" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_CK_BUFHCLK0", |
| "HCLK_VBRK_CK_BUFHCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK1", |
| "HCLK_VBRK_CK_BUFHCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK10", |
| "HCLK_VBRK_CK_BUFHCLK10" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK11", |
| "HCLK_VBRK_CK_BUFHCLK11" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK2", |
| "HCLK_VBRK_CK_BUFHCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK3", |
| "HCLK_VBRK_CK_BUFHCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK4", |
| "HCLK_VBRK_CK_BUFHCLK4" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK5", |
| "HCLK_VBRK_CK_BUFHCLK5" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK6", |
| "HCLK_VBRK_CK_BUFHCLK6" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK7", |
| "HCLK_VBRK_CK_BUFHCLK7" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK8", |
| "HCLK_VBRK_CK_BUFHCLK8" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK9", |
| "HCLK_VBRK_CK_BUFHCLK9" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK0", |
| "HCLK_VBRK_CK_BUFRCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK1", |
| "HCLK_VBRK_CK_BUFRCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK2", |
| "HCLK_VBRK_CK_BUFRCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK3", |
| "HCLK_VBRK_CK_BUFRCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN0", |
| "HCLK_VBRK_MUX_CLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_IN1", |
| "HCLK_VBRK_MUX_CLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_IN10", |
| "HCLK_VBRK_MUX_CLK10" |
| ], |
| [ |
| "HCLK_CLB_CK_IN11", |
| "HCLK_VBRK_MUX_CLK11" |
| ], |
| [ |
| "HCLK_CLB_CK_IN12", |
| "HCLK_VBRK_MUX_CLK12" |
| ], |
| [ |
| "HCLK_CLB_CK_IN13", |
| "HCLK_VBRK_MUX_CLK13" |
| ], |
| [ |
| "HCLK_CLB_CK_IN2", |
| "HCLK_VBRK_MUX_CLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_IN3", |
| "HCLK_VBRK_MUX_CLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN4", |
| "HCLK_VBRK_MUX_CLK4" |
| ], |
| [ |
| "HCLK_CLB_CK_IN5", |
| "HCLK_VBRK_MUX_CLK5" |
| ], |
| [ |
| "HCLK_CLB_CK_IN6", |
| "HCLK_VBRK_MUX_CLK6" |
| ], |
| [ |
| "HCLK_CLB_CK_IN7", |
| "HCLK_VBRK_MUX_CLK7" |
| ], |
| [ |
| "HCLK_CLB_CK_IN8", |
| "HCLK_VBRK_MUX_CLK8" |
| ], |
| [ |
| "HCLK_CLB_CK_IN9", |
| "HCLK_VBRK_MUX_CLK9" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "HCLK_CLB", |
| "HCLK_VFRAME" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CLB_CK_BUFHCLK0", |
| "HCLK_VFRAME_CK_BUFHCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK1", |
| "HCLK_VFRAME_CK_BUFHCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK10", |
| "HCLK_VFRAME_CK_BUFHCLK10" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK11", |
| "HCLK_VFRAME_CK_BUFHCLK11" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK2", |
| "HCLK_VFRAME_CK_BUFHCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK3", |
| "HCLK_VFRAME_CK_BUFHCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK4", |
| "HCLK_VFRAME_CK_BUFHCLK4" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK5", |
| "HCLK_VFRAME_CK_BUFHCLK5" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK6", |
| "HCLK_VFRAME_CK_BUFHCLK6" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK7", |
| "HCLK_VFRAME_CK_BUFHCLK7" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK8", |
| "HCLK_VFRAME_CK_BUFHCLK8" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFHCLK9", |
| "HCLK_VFRAME_CK_BUFHCLK9" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK0", |
| "HCLK_VFRAME_CK_BUFRCLK0" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK1", |
| "HCLK_VFRAME_CK_BUFRCLK1" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK2", |
| "HCLK_VFRAME_CK_BUFRCLK2" |
| ], |
| [ |
| "HCLK_CLB_CK_BUFRCLK3", |
| "HCLK_VFRAME_CK_BUFRCLK3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN0", |
| "HCLK_VFRAME_CK_IN0" |
| ], |
| [ |
| "HCLK_CLB_CK_IN1", |
| "HCLK_VFRAME_CK_IN1" |
| ], |
| [ |
| "HCLK_CLB_CK_IN10", |
| "HCLK_VFRAME_CK_IN10" |
| ], |
| [ |
| "HCLK_CLB_CK_IN11", |
| "HCLK_VFRAME_CK_IN11" |
| ], |
| [ |
| "HCLK_CLB_CK_IN12", |
| "HCLK_VFRAME_CK_IN12" |
| ], |
| [ |
| "HCLK_CLB_CK_IN13", |
| "HCLK_VFRAME_CK_IN13" |
| ], |
| [ |
| "HCLK_CLB_CK_IN2", |
| "HCLK_VFRAME_CK_IN2" |
| ], |
| [ |
| "HCLK_CLB_CK_IN3", |
| "HCLK_VFRAME_CK_IN3" |
| ], |
| [ |
| "HCLK_CLB_CK_IN4", |
| "HCLK_VFRAME_CK_IN4" |
| ], |
| [ |
| "HCLK_CLB_CK_IN5", |
| "HCLK_VFRAME_CK_IN5" |
| ], |
| [ |
| "HCLK_CLB_CK_IN6", |
| "HCLK_VFRAME_CK_IN6" |
| ], |
| [ |
| "HCLK_CLB_CK_IN7", |
| "HCLK_VFRAME_CK_IN7" |
| ], |
| [ |
| "HCLK_CLB_CK_IN8", |
| "HCLK_VFRAME_CK_IN8" |
| ], |
| [ |
| "HCLK_CLB_CK_IN9", |
| "HCLK_VFRAME_CK_IN9" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "HCLK_L", |
| "HCLK_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CK_BUFHCLK0", |
| "HCLK_CK_BUFHCLK0" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK1", |
| "HCLK_CK_BUFHCLK1" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK10", |
| "HCLK_CK_BUFHCLK10" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK11", |
| "HCLK_CK_BUFHCLK11" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK2", |
| "HCLK_CK_BUFHCLK2" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK3", |
| "HCLK_CK_BUFHCLK3" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK4", |
| "HCLK_CK_BUFHCLK4" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK5", |
| "HCLK_CK_BUFHCLK5" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK6", |
| "HCLK_CK_BUFHCLK6" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK7", |
| "HCLK_CK_BUFHCLK7" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK8", |
| "HCLK_CK_BUFHCLK8" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK9", |
| "HCLK_CK_BUFHCLK9" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK0", |
| "HCLK_CK_BUFRCLK0" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK1", |
| "HCLK_CK_BUFRCLK1" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK2", |
| "HCLK_CK_BUFRCLK2" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK3", |
| "HCLK_CK_BUFRCLK3" |
| ], |
| [ |
| "HCLK_CK_IN0", |
| "HCLK_CK_IN0" |
| ], |
| [ |
| "HCLK_CK_IN1", |
| "HCLK_CK_IN1" |
| ], |
| [ |
| "HCLK_CK_IN10", |
| "HCLK_CK_IN10" |
| ], |
| [ |
| "HCLK_CK_IN11", |
| "HCLK_CK_IN11" |
| ], |
| [ |
| "HCLK_CK_IN12", |
| "HCLK_CK_IN12" |
| ], |
| [ |
| "HCLK_CK_IN13", |
| "HCLK_CK_IN13" |
| ], |
| [ |
| "HCLK_CK_IN2", |
| "HCLK_CK_IN2" |
| ], |
| [ |
| "HCLK_CK_IN3", |
| "HCLK_CK_IN3" |
| ], |
| [ |
| "HCLK_CK_IN4", |
| "HCLK_CK_IN4" |
| ], |
| [ |
| "HCLK_CK_IN5", |
| "HCLK_CK_IN5" |
| ], |
| [ |
| "HCLK_CK_IN6", |
| "HCLK_CK_IN6" |
| ], |
| [ |
| "HCLK_CK_IN7", |
| "HCLK_CK_IN7" |
| ], |
| [ |
| "HCLK_CK_IN8", |
| "HCLK_CK_IN8" |
| ], |
| [ |
| "HCLK_CK_IN9", |
| "HCLK_CK_IN9" |
| ], |
| [ |
| "HCLK_CK_INOUT_L0", |
| "HCLK_CK_OUTIN_R4" |
| ], |
| [ |
| "HCLK_CK_INOUT_L1", |
| "HCLK_CK_OUTIN_R5" |
| ], |
| [ |
| "HCLK_CK_INOUT_L2", |
| "HCLK_CK_OUTIN_R6" |
| ], |
| [ |
| "HCLK_CK_INOUT_L3", |
| "HCLK_CK_OUTIN_R7" |
| ], |
| [ |
| "HCLK_CK_INOUT_L4", |
| "HCLK_CK_OUTIN_R0" |
| ], |
| [ |
| "HCLK_CK_INOUT_L5", |
| "HCLK_CK_OUTIN_R1" |
| ], |
| [ |
| "HCLK_CK_INOUT_L6", |
| "HCLK_CK_OUTIN_R2" |
| ], |
| [ |
| "HCLK_CK_INOUT_L7", |
| "HCLK_CK_OUTIN_R3" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L0", |
| "HCLK_CK_INOUT_R0" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L1", |
| "HCLK_CK_INOUT_R1" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L2", |
| "HCLK_CK_INOUT_R2" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L3", |
| "HCLK_CK_INOUT_R3" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L4", |
| "HCLK_CK_INOUT_R4" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L5", |
| "HCLK_CK_INOUT_R5" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L6", |
| "HCLK_CK_INOUT_R6" |
| ], |
| [ |
| "HCLK_CK_OUTIN_L7", |
| "HCLK_CK_INOUT_R7" |
| ], |
| [ |
| "HCLK_NE2BEG0", |
| "HCLK_NE2END_S3_0" |
| ], |
| [ |
| "HCLK_NW2END_S0_0", |
| "HCLK_NW2A0" |
| ], |
| [ |
| "HCLK_NW6END_S0_0", |
| "HCLK_NW6D0" |
| ], |
| [ |
| "HCLK_SW2END_N0_3", |
| "HCLK_SW2A3" |
| ], |
| [ |
| "HCLK_SW6END3", |
| "HCLK_SW6E3" |
| ], |
| [ |
| "HCLK_WL1END3", |
| "HCLK_WL1BEG3" |
| ], |
| [ |
| "HCLK_WR1END_S1_0", |
| "HCLK_WR1BEG_S0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "HCLK_L", |
| "INT_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_BYP_BOUNCE2", |
| "BYP_BOUNCE2" |
| ], |
| [ |
| "HCLK_BYP_BOUNCE3", |
| "BYP_BOUNCE3" |
| ], |
| [ |
| "HCLK_BYP_BOUNCE6", |
| "BYP_BOUNCE6" |
| ], |
| [ |
| "HCLK_BYP_BOUNCE7", |
| "BYP_BOUNCE7" |
| ], |
| [ |
| "HCLK_EL1BEG3", |
| "EL1BEG3" |
| ], |
| [ |
| "HCLK_EL1END_S3_0", |
| "EL1END_S3_0" |
| ], |
| [ |
| "HCLK_ER1BEG_S0", |
| "ER1BEG_S0" |
| ], |
| [ |
| "HCLK_ER1END3", |
| "ER1END3" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_0", |
| "FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_2", |
| "FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_4", |
| "FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_6", |
| "FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOTL0", |
| "GCLK_L_B6" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOTL1", |
| "GCLK_L_B7" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOTL2", |
| "GCLK_L_B8" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOTL3", |
| "GCLK_L_B9" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOTL4", |
| "GCLK_L_B10" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOTL5", |
| "GCLK_L_B11" |
| ], |
| [ |
| "HCLK_LV0", |
| "LV_L0" |
| ], |
| [ |
| "HCLK_LV1", |
| "LV_L1" |
| ], |
| [ |
| "HCLK_LV10", |
| "LV_L10" |
| ], |
| [ |
| "HCLK_LV11", |
| "LV_L11" |
| ], |
| [ |
| "HCLK_LV12", |
| "LV_L12" |
| ], |
| [ |
| "HCLK_LV13", |
| "LV_L13" |
| ], |
| [ |
| "HCLK_LV14", |
| "LV_L14" |
| ], |
| [ |
| "HCLK_LV15", |
| "LV_L15" |
| ], |
| [ |
| "HCLK_LV16", |
| "LV_L16" |
| ], |
| [ |
| "HCLK_LV17", |
| "LV_L17" |
| ], |
| [ |
| "HCLK_LV2", |
| "LV_L2" |
| ], |
| [ |
| "HCLK_LV3", |
| "LV_L3" |
| ], |
| [ |
| "HCLK_LV4", |
| "LV_L4" |
| ], |
| [ |
| "HCLK_LV5", |
| "LV_L5" |
| ], |
| [ |
| "HCLK_LV6", |
| "LV_L6" |
| ], |
| [ |
| "HCLK_LV7", |
| "LV_L7" |
| ], |
| [ |
| "HCLK_LV8", |
| "LV_L8" |
| ], |
| [ |
| "HCLK_LV9", |
| "LV_L9" |
| ], |
| [ |
| "HCLK_LVB1", |
| "LVB_L0" |
| ], |
| [ |
| "HCLK_LVB10", |
| "LVB_L9" |
| ], |
| [ |
| "HCLK_LVB11", |
| "LVB_L10" |
| ], |
| [ |
| "HCLK_LVB12", |
| "LVB_L11" |
| ], |
| [ |
| "HCLK_LVB2", |
| "LVB_L1" |
| ], |
| [ |
| "HCLK_LVB3", |
| "LVB_L2" |
| ], |
| [ |
| "HCLK_LVB4", |
| "LVB_L3" |
| ], |
| [ |
| "HCLK_LVB5", |
| "LVB_L4" |
| ], |
| [ |
| "HCLK_LVB6", |
| "LVB_L5" |
| ], |
| [ |
| "HCLK_LVB7", |
| "LVB_L6" |
| ], |
| [ |
| "HCLK_LVB8", |
| "LVB_L7" |
| ], |
| [ |
| "HCLK_LVB9", |
| "LVB_L8" |
| ], |
| [ |
| "HCLK_NE2BEG0", |
| "NE2BEG0" |
| ], |
| [ |
| "HCLK_NE2BEG1", |
| "NE2BEG1" |
| ], |
| [ |
| "HCLK_NE2BEG2", |
| "NE2BEG2" |
| ], |
| [ |
| "HCLK_NE2BEG3", |
| "NE2BEG3" |
| ], |
| [ |
| "HCLK_NE2END_S3_0", |
| "NE2END_S3_0" |
| ], |
| [ |
| "HCLK_NE6A0", |
| "NE6A0" |
| ], |
| [ |
| "HCLK_NE6A1", |
| "NE6A1" |
| ], |
| [ |
| "HCLK_NE6A2", |
| "NE6A2" |
| ], |
| [ |
| "HCLK_NE6A3", |
| "NE6A3" |
| ], |
| [ |
| "HCLK_NE6B0", |
| "NE6B0" |
| ], |
| [ |
| "HCLK_NE6B1", |
| "NE6B1" |
| ], |
| [ |
| "HCLK_NE6B2", |
| "NE6B2" |
| ], |
| [ |
| "HCLK_NE6B3", |
| "NE6B3" |
| ], |
| [ |
| "HCLK_NE6C0", |
| "NE6C0" |
| ], |
| [ |
| "HCLK_NE6C1", |
| "NE6C1" |
| ], |
| [ |
| "HCLK_NE6C2", |
| "NE6C2" |
| ], |
| [ |
| "HCLK_NE6C3", |
| "NE6C3" |
| ], |
| [ |
| "HCLK_NE6D0", |
| "NE6D0" |
| ], |
| [ |
| "HCLK_NE6D1", |
| "NE6D1" |
| ], |
| [ |
| "HCLK_NE6D2", |
| "NE6D2" |
| ], |
| [ |
| "HCLK_NE6D3", |
| "NE6D3" |
| ], |
| [ |
| "HCLK_NL1BEG1", |
| "NL1BEG1" |
| ], |
| [ |
| "HCLK_NL1BEG2", |
| "NL1BEG2" |
| ], |
| [ |
| "HCLK_NL1END_S3_0", |
| "NL1END_S3_0" |
| ], |
| [ |
| "HCLK_NN2A1", |
| "NN2A1" |
| ], |
| [ |
| "HCLK_NN2A2", |
| "NN2A2" |
| ], |
| [ |
| "HCLK_NN2A3", |
| "NN2A3" |
| ], |
| [ |
| "HCLK_NN2BEG0", |
| "NN2BEG0" |
| ], |
| [ |
| "HCLK_NN2BEG1", |
| "NN2BEG1" |
| ], |
| [ |
| "HCLK_NN2BEG2", |
| "NN2BEG2" |
| ], |
| [ |
| "HCLK_NN2BEG3", |
| "NN2BEG3" |
| ], |
| [ |
| "HCLK_NN2END_S2_0", |
| "NN2A0" |
| ], |
| [ |
| "HCLK_NN6A0", |
| "NN6A0" |
| ], |
| [ |
| "HCLK_NN6A1", |
| "NN6A1" |
| ], |
| [ |
| "HCLK_NN6A2", |
| "NN6A2" |
| ], |
| [ |
| "HCLK_NN6A3", |
| "NN6A3" |
| ], |
| [ |
| "HCLK_NN6B0", |
| "NN6B0" |
| ], |
| [ |
| "HCLK_NN6B1", |
| "NN6B1" |
| ], |
| [ |
| "HCLK_NN6B2", |
| "NN6B2" |
| ], |
| [ |
| "HCLK_NN6B3", |
| "NN6B3" |
| ], |
| [ |
| "HCLK_NN6BEG0", |
| "NN6BEG0" |
| ], |
| [ |
| "HCLK_NN6BEG1", |
| "NN6BEG1" |
| ], |
| [ |
| "HCLK_NN6BEG2", |
| "NN6BEG2" |
| ], |
| [ |
| "HCLK_NN6BEG3", |
| "NN6BEG3" |
| ], |
| [ |
| "HCLK_NN6C0", |
| "NN6C0" |
| ], |
| [ |
| "HCLK_NN6C1", |
| "NN6C1" |
| ], |
| [ |
| "HCLK_NN6C2", |
| "NN6C2" |
| ], |
| [ |
| "HCLK_NN6C3", |
| "NN6C3" |
| ], |
| [ |
| "HCLK_NN6D0", |
| "NN6D0" |
| ], |
| [ |
| "HCLK_NN6D1", |
| "NN6D1" |
| ], |
| [ |
| "HCLK_NN6D2", |
| "NN6D2" |
| ], |
| [ |
| "HCLK_NN6D3", |
| "NN6D3" |
| ], |
| [ |
| "HCLK_NN6E1", |
| "NN6E1" |
| ], |
| [ |
| "HCLK_NN6E2", |
| "NN6E2" |
| ], |
| [ |
| "HCLK_NN6E3", |
| "NN6E3" |
| ], |
| [ |
| "HCLK_NN6END_S1_0", |
| "NN6E0" |
| ], |
| [ |
| "HCLK_NR1BEG0", |
| "NR1BEG0" |
| ], |
| [ |
| "HCLK_NR1BEG1", |
| "NR1BEG1" |
| ], |
| [ |
| "HCLK_NR1BEG2", |
| "NR1BEG2" |
| ], |
| [ |
| "HCLK_NR1BEG3", |
| "NR1BEG3" |
| ], |
| [ |
| "HCLK_NW2A0", |
| "NW2BEG0" |
| ], |
| [ |
| "HCLK_NW2A1", |
| "NW2BEG1" |
| ], |
| [ |
| "HCLK_NW2A2", |
| "NW2BEG2" |
| ], |
| [ |
| "HCLK_NW2A3", |
| "NW2BEG3" |
| ], |
| [ |
| "HCLK_NW2END_S0_0", |
| "NW2END_S0_0" |
| ], |
| [ |
| "HCLK_NW6A0", |
| "NW6A0" |
| ], |
| [ |
| "HCLK_NW6A1", |
| "NW6A1" |
| ], |
| [ |
| "HCLK_NW6A2", |
| "NW6A2" |
| ], |
| [ |
| "HCLK_NW6A3", |
| "NW6A3" |
| ], |
| [ |
| "HCLK_NW6B0", |
| "NW6B0" |
| ], |
| [ |
| "HCLK_NW6B1", |
| "NW6B1" |
| ], |
| [ |
| "HCLK_NW6B2", |
| "NW6B2" |
| ], |
| [ |
| "HCLK_NW6B3", |
| "NW6B3" |
| ], |
| [ |
| "HCLK_NW6C0", |
| "NW6C0" |
| ], |
| [ |
| "HCLK_NW6C1", |
| "NW6C1" |
| ], |
| [ |
| "HCLK_NW6C2", |
| "NW6C2" |
| ], |
| [ |
| "HCLK_NW6C3", |
| "NW6C3" |
| ], |
| [ |
| "HCLK_NW6D0", |
| "NW6D0" |
| ], |
| [ |
| "HCLK_NW6D1", |
| "NW6D1" |
| ], |
| [ |
| "HCLK_NW6D2", |
| "NW6D2" |
| ], |
| [ |
| "HCLK_NW6D3", |
| "NW6D3" |
| ], |
| [ |
| "HCLK_NW6END_S0_0", |
| "NW6END_S0_0" |
| ], |
| [ |
| "HCLK_SE2A0", |
| "SE2A0" |
| ], |
| [ |
| "HCLK_SE2A1", |
| "SE2A1" |
| ], |
| [ |
| "HCLK_SE2A2", |
| "SE2A2" |
| ], |
| [ |
| "HCLK_SE2A3", |
| "SE2A3" |
| ], |
| [ |
| "HCLK_SE6B0", |
| "SE6B0" |
| ], |
| [ |
| "HCLK_SE6B1", |
| "SE6B1" |
| ], |
| [ |
| "HCLK_SE6B2", |
| "SE6B2" |
| ], |
| [ |
| "HCLK_SE6B3", |
| "SE6B3" |
| ], |
| [ |
| "HCLK_SE6C0", |
| "SE6C0" |
| ], |
| [ |
| "HCLK_SE6C1", |
| "SE6C1" |
| ], |
| [ |
| "HCLK_SE6C2", |
| "SE6C2" |
| ], |
| [ |
| "HCLK_SE6C3", |
| "SE6C3" |
| ], |
| [ |
| "HCLK_SE6D0", |
| "SE6D0" |
| ], |
| [ |
| "HCLK_SE6D1", |
| "SE6D1" |
| ], |
| [ |
| "HCLK_SE6D2", |
| "SE6D2" |
| ], |
| [ |
| "HCLK_SE6D3", |
| "SE6D3" |
| ], |
| [ |
| "HCLK_SE6E0", |
| "SE6E0" |
| ], |
| [ |
| "HCLK_SE6E1", |
| "SE6E1" |
| ], |
| [ |
| "HCLK_SE6E2", |
| "SE6E2" |
| ], |
| [ |
| "HCLK_SE6E3", |
| "SE6E3" |
| ], |
| [ |
| "HCLK_SL1END0", |
| "SL1END0" |
| ], |
| [ |
| "HCLK_SL1END1", |
| "SL1END1" |
| ], |
| [ |
| "HCLK_SL1END2", |
| "SL1END2" |
| ], |
| [ |
| "HCLK_SL1END3", |
| "SL1END3" |
| ], |
| [ |
| "HCLK_SR1END1", |
| "SR1END1" |
| ], |
| [ |
| "HCLK_SR1END2", |
| "SR1END2" |
| ], |
| [ |
| "HCLK_SR1END_N3_3", |
| "SR1END3" |
| ], |
| [ |
| "HCLK_SS2A0", |
| "SS2A0" |
| ], |
| [ |
| "HCLK_SS2A1", |
| "SS2A1" |
| ], |
| [ |
| "HCLK_SS2A2", |
| "SS2A2" |
| ], |
| [ |
| "HCLK_SS2BEG3", |
| "SS2A3" |
| ], |
| [ |
| "HCLK_SS2END0", |
| "SS2END0" |
| ], |
| [ |
| "HCLK_SS2END1", |
| "SS2END1" |
| ], |
| [ |
| "HCLK_SS2END2", |
| "SS2END2" |
| ], |
| [ |
| "HCLK_SS2END_N0_3", |
| "SS2END3" |
| ], |
| [ |
| "HCLK_SS6A0", |
| "SS6A0" |
| ], |
| [ |
| "HCLK_SS6A1", |
| "SS6A1" |
| ], |
| [ |
| "HCLK_SS6A2", |
| "SS6A2" |
| ], |
| [ |
| "HCLK_SS6A3", |
| "SS6A3" |
| ], |
| [ |
| "HCLK_SS6B0", |
| "SS6B0" |
| ], |
| [ |
| "HCLK_SS6B1", |
| "SS6B1" |
| ], |
| [ |
| "HCLK_SS6B2", |
| "SS6B2" |
| ], |
| [ |
| "HCLK_SS6B3", |
| "SS6B3" |
| ], |
| [ |
| "HCLK_SS6C0", |
| "SS6C0" |
| ], |
| [ |
| "HCLK_SS6C1", |
| "SS6C1" |
| ], |
| [ |
| "HCLK_SS6C2", |
| "SS6C2" |
| ], |
| [ |
| "HCLK_SS6C3", |
| "SS6C3" |
| ], |
| [ |
| "HCLK_SS6D0", |
| "SS6D0" |
| ], |
| [ |
| "HCLK_SS6D1", |
| "SS6D1" |
| ], |
| [ |
| "HCLK_SS6D2", |
| "SS6D2" |
| ], |
| [ |
| "HCLK_SS6D3", |
| "SS6D3" |
| ], |
| [ |
| "HCLK_SS6E0", |
| "SS6E0" |
| ], |
| [ |
| "HCLK_SS6E1", |
| "SS6E1" |
| ], |
| [ |
| "HCLK_SS6E2", |
| "SS6E2" |
| ], |
| [ |
| "HCLK_SS6E3", |
| "SS6E3" |
| ], |
| [ |
| "HCLK_SS6END0", |
| "SS6END0" |
| ], |
| [ |
| "HCLK_SS6END1", |
| "SS6END1" |
| ], |
| [ |
| "HCLK_SS6END2", |
| "SS6END2" |
| ], |
| [ |
| "HCLK_SS6END_N0_3", |
| "SS6END3" |
| ], |
| [ |
| "HCLK_SW2A3", |
| "SW2A3" |
| ], |
| [ |
| "HCLK_SW2END0", |
| "SW2A0" |
| ], |
| [ |
| "HCLK_SW2END1", |
| "SW2A1" |
| ], |
| [ |
| "HCLK_SW2END2", |
| "SW2A2" |
| ], |
| [ |
| "HCLK_SW2END_N0_3", |
| "SW2END3" |
| ], |
| [ |
| "HCLK_SW6B0", |
| "SW6B0" |
| ], |
| [ |
| "HCLK_SW6B1", |
| "SW6B1" |
| ], |
| [ |
| "HCLK_SW6B2", |
| "SW6B2" |
| ], |
| [ |
| "HCLK_SW6B3", |
| "SW6B3" |
| ], |
| [ |
| "HCLK_SW6C0", |
| "SW6C0" |
| ], |
| [ |
| "HCLK_SW6C1", |
| "SW6C1" |
| ], |
| [ |
| "HCLK_SW6C2", |
| "SW6C2" |
| ], |
| [ |
| "HCLK_SW6C3", |
| "SW6C3" |
| ], |
| [ |
| "HCLK_SW6D0", |
| "SW6D0" |
| ], |
| [ |
| "HCLK_SW6D1", |
| "SW6D1" |
| ], |
| [ |
| "HCLK_SW6D2", |
| "SW6D2" |
| ], |
| [ |
| "HCLK_SW6D3", |
| "SW6D3" |
| ], |
| [ |
| "HCLK_SW6E0", |
| "SW6E0" |
| ], |
| [ |
| "HCLK_SW6E1", |
| "SW6E1" |
| ], |
| [ |
| "HCLK_SW6E2", |
| "SW6E2" |
| ], |
| [ |
| "HCLK_SW6E3", |
| "SW6E3" |
| ], |
| [ |
| "HCLK_SW6END3", |
| "SW6END3" |
| ], |
| [ |
| "HCLK_WL1BEG3", |
| "WL1BEG3" |
| ], |
| [ |
| "HCLK_WL1END3", |
| "WL1END3" |
| ], |
| [ |
| "HCLK_WR1BEG_S0", |
| "WR1BEG_S0" |
| ], |
| [ |
| "HCLK_WR1END_S1_0", |
| "WR1END_S1_0" |
| ], |
| [ |
| "HCLK_WW2END3", |
| "WW2END3" |
| ], |
| [ |
| "HCLK_WW4END_S0_0", |
| "WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "HCLK_R", |
| "HCLK_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_CK_BUFHCLK0", |
| "HCLK_CLB_CK_BUFHCLK0" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK1", |
| "HCLK_CLB_CK_BUFHCLK1" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK10", |
| "HCLK_CLB_CK_BUFHCLK10" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK11", |
| "HCLK_CLB_CK_BUFHCLK11" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK2", |
| "HCLK_CLB_CK_BUFHCLK2" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK3", |
| "HCLK_CLB_CK_BUFHCLK3" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK4", |
| "HCLK_CLB_CK_BUFHCLK4" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK5", |
| "HCLK_CLB_CK_BUFHCLK5" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK6", |
| "HCLK_CLB_CK_BUFHCLK6" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK7", |
| "HCLK_CLB_CK_BUFHCLK7" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK8", |
| "HCLK_CLB_CK_BUFHCLK8" |
| ], |
| [ |
| "HCLK_CK_BUFHCLK9", |
| "HCLK_CLB_CK_BUFHCLK9" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK0", |
| "HCLK_CLB_CK_BUFRCLK0" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK1", |
| "HCLK_CLB_CK_BUFRCLK1" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK2", |
| "HCLK_CLB_CK_BUFRCLK2" |
| ], |
| [ |
| "HCLK_CK_BUFRCLK3", |
| "HCLK_CLB_CK_BUFRCLK3" |
| ], |
| [ |
| "HCLK_CK_IN0", |
| "HCLK_CLB_CK_IN0" |
| ], |
| [ |
| "HCLK_CK_IN1", |
| "HCLK_CLB_CK_IN1" |
| ], |
| [ |
| "HCLK_CK_IN10", |
| "HCLK_CLB_CK_IN10" |
| ], |
| [ |
| "HCLK_CK_IN11", |
| "HCLK_CLB_CK_IN11" |
| ], |
| [ |
| "HCLK_CK_IN12", |
| "HCLK_CLB_CK_IN12" |
| ], |
| [ |
| "HCLK_CK_IN13", |
| "HCLK_CLB_CK_IN13" |
| ], |
| [ |
| "HCLK_CK_IN2", |
| "HCLK_CLB_CK_IN2" |
| ], |
| [ |
| "HCLK_CK_IN3", |
| "HCLK_CLB_CK_IN3" |
| ], |
| [ |
| "HCLK_CK_IN4", |
| "HCLK_CLB_CK_IN4" |
| ], |
| [ |
| "HCLK_CK_IN5", |
| "HCLK_CLB_CK_IN5" |
| ], |
| [ |
| "HCLK_CK_IN6", |
| "HCLK_CLB_CK_IN6" |
| ], |
| [ |
| "HCLK_CK_IN7", |
| "HCLK_CLB_CK_IN7" |
| ], |
| [ |
| "HCLK_CK_IN8", |
| "HCLK_CLB_CK_IN8" |
| ], |
| [ |
| "HCLK_CK_IN9", |
| "HCLK_CLB_CK_IN9" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "HCLK_R", |
| "INT_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_BYP_BOUNCE2", |
| "BYP_BOUNCE2" |
| ], |
| [ |
| "HCLK_BYP_BOUNCE3", |
| "BYP_BOUNCE3" |
| ], |
| [ |
| "HCLK_BYP_BOUNCE6", |
| "BYP_BOUNCE6" |
| ], |
| [ |
| "HCLK_BYP_BOUNCE7", |
| "BYP_BOUNCE7" |
| ], |
| [ |
| "HCLK_EL1BEG3", |
| "EL1BEG3" |
| ], |
| [ |
| "HCLK_EL1END_S3_0", |
| "EL1END_S3_0" |
| ], |
| [ |
| "HCLK_ER1BEG_S0", |
| "ER1BEG_S0" |
| ], |
| [ |
| "HCLK_ER1END3", |
| "ER1END3" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_0", |
| "FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_2", |
| "FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_4", |
| "FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "HCLK_FAN_BOUNCE_S3_6", |
| "FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOT0", |
| "GCLK_B0" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOT1", |
| "GCLK_B1" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOT2", |
| "GCLK_B2" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOT3", |
| "GCLK_B3" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOT4", |
| "GCLK_B4" |
| ], |
| [ |
| "HCLK_LEAF_CLK_B_BOT5", |
| "GCLK_B5" |
| ], |
| [ |
| "HCLK_LV0", |
| "LV0" |
| ], |
| [ |
| "HCLK_LV1", |
| "LV1" |
| ], |
| [ |
| "HCLK_LV10", |
| "LV10" |
| ], |
| [ |
| "HCLK_LV11", |
| "LV11" |
| ], |
| [ |
| "HCLK_LV12", |
| "LV12" |
| ], |
| [ |
| "HCLK_LV13", |
| "LV13" |
| ], |
| [ |
| "HCLK_LV14", |
| "LV14" |
| ], |
| [ |
| "HCLK_LV15", |
| "LV15" |
| ], |
| [ |
| "HCLK_LV16", |
| "LV16" |
| ], |
| [ |
| "HCLK_LV17", |
| "LV17" |
| ], |
| [ |
| "HCLK_LV2", |
| "LV2" |
| ], |
| [ |
| "HCLK_LV3", |
| "LV3" |
| ], |
| [ |
| "HCLK_LV4", |
| "LV4" |
| ], |
| [ |
| "HCLK_LV5", |
| "LV5" |
| ], |
| [ |
| "HCLK_LV6", |
| "LV6" |
| ], |
| [ |
| "HCLK_LV7", |
| "LV7" |
| ], |
| [ |
| "HCLK_LV8", |
| "LV8" |
| ], |
| [ |
| "HCLK_LV9", |
| "LV9" |
| ], |
| [ |
| "HCLK_LVB1", |
| "LVB0" |
| ], |
| [ |
| "HCLK_LVB10", |
| "LVB9" |
| ], |
| [ |
| "HCLK_LVB11", |
| "LVB10" |
| ], |
| [ |
| "HCLK_LVB12", |
| "LVB11" |
| ], |
| [ |
| "HCLK_LVB2", |
| "LVB1" |
| ], |
| [ |
| "HCLK_LVB3", |
| "LVB2" |
| ], |
| [ |
| "HCLK_LVB4", |
| "LVB3" |
| ], |
| [ |
| "HCLK_LVB5", |
| "LVB4" |
| ], |
| [ |
| "HCLK_LVB6", |
| "LVB5" |
| ], |
| [ |
| "HCLK_LVB7", |
| "LVB6" |
| ], |
| [ |
| "HCLK_LVB8", |
| "LVB7" |
| ], |
| [ |
| "HCLK_LVB9", |
| "LVB8" |
| ], |
| [ |
| "HCLK_NE2BEG0", |
| "NE2BEG0" |
| ], |
| [ |
| "HCLK_NE2BEG1", |
| "NE2BEG1" |
| ], |
| [ |
| "HCLK_NE2BEG2", |
| "NE2BEG2" |
| ], |
| [ |
| "HCLK_NE2BEG3", |
| "NE2BEG3" |
| ], |
| [ |
| "HCLK_NE2END_S3_0", |
| "NE2END_S3_0" |
| ], |
| [ |
| "HCLK_NE6A0", |
| "NE6A0" |
| ], |
| [ |
| "HCLK_NE6A1", |
| "NE6A1" |
| ], |
| [ |
| "HCLK_NE6A2", |
| "NE6A2" |
| ], |
| [ |
| "HCLK_NE6A3", |
| "NE6A3" |
| ], |
| [ |
| "HCLK_NE6B0", |
| "NE6B0" |
| ], |
| [ |
| "HCLK_NE6B1", |
| "NE6B1" |
| ], |
| [ |
| "HCLK_NE6B2", |
| "NE6B2" |
| ], |
| [ |
| "HCLK_NE6B3", |
| "NE6B3" |
| ], |
| [ |
| "HCLK_NE6C0", |
| "NE6C0" |
| ], |
| [ |
| "HCLK_NE6C1", |
| "NE6C1" |
| ], |
| [ |
| "HCLK_NE6C2", |
| "NE6C2" |
| ], |
| [ |
| "HCLK_NE6C3", |
| "NE6C3" |
| ], |
| [ |
| "HCLK_NE6D0", |
| "NE6D0" |
| ], |
| [ |
| "HCLK_NE6D1", |
| "NE6D1" |
| ], |
| [ |
| "HCLK_NE6D2", |
| "NE6D2" |
| ], |
| [ |
| "HCLK_NE6D3", |
| "NE6D3" |
| ], |
| [ |
| "HCLK_NL1BEG1", |
| "NL1BEG1" |
| ], |
| [ |
| "HCLK_NL1BEG2", |
| "NL1BEG2" |
| ], |
| [ |
| "HCLK_NL1END_S3_0", |
| "NL1END_S3_0" |
| ], |
| [ |
| "HCLK_NN2A1", |
| "NN2A1" |
| ], |
| [ |
| "HCLK_NN2A2", |
| "NN2A2" |
| ], |
| [ |
| "HCLK_NN2A3", |
| "NN2A3" |
| ], |
| [ |
| "HCLK_NN2BEG0", |
| "NN2BEG0" |
| ], |
| [ |
| "HCLK_NN2BEG1", |
| "NN2BEG1" |
| ], |
| [ |
| "HCLK_NN2BEG2", |
| "NN2BEG2" |
| ], |
| [ |
| "HCLK_NN2BEG3", |
| "NN2BEG3" |
| ], |
| [ |
| "HCLK_NN2END_S2_0", |
| "NN2A0" |
| ], |
| [ |
| "HCLK_NN6A0", |
| "NN6A0" |
| ], |
| [ |
| "HCLK_NN6A1", |
| "NN6A1" |
| ], |
| [ |
| "HCLK_NN6A2", |
| "NN6A2" |
| ], |
| [ |
| "HCLK_NN6A3", |
| "NN6A3" |
| ], |
| [ |
| "HCLK_NN6B0", |
| "NN6B0" |
| ], |
| [ |
| "HCLK_NN6B1", |
| "NN6B1" |
| ], |
| [ |
| "HCLK_NN6B2", |
| "NN6B2" |
| ], |
| [ |
| "HCLK_NN6B3", |
| "NN6B3" |
| ], |
| [ |
| "HCLK_NN6BEG0", |
| "NN6BEG0" |
| ], |
| [ |
| "HCLK_NN6BEG1", |
| "NN6BEG1" |
| ], |
| [ |
| "HCLK_NN6BEG2", |
| "NN6BEG2" |
| ], |
| [ |
| "HCLK_NN6BEG3", |
| "NN6BEG3" |
| ], |
| [ |
| "HCLK_NN6C0", |
| "NN6C0" |
| ], |
| [ |
| "HCLK_NN6C1", |
| "NN6C1" |
| ], |
| [ |
| "HCLK_NN6C2", |
| "NN6C2" |
| ], |
| [ |
| "HCLK_NN6C3", |
| "NN6C3" |
| ], |
| [ |
| "HCLK_NN6D0", |
| "NN6D0" |
| ], |
| [ |
| "HCLK_NN6D1", |
| "NN6D1" |
| ], |
| [ |
| "HCLK_NN6D2", |
| "NN6D2" |
| ], |
| [ |
| "HCLK_NN6D3", |
| "NN6D3" |
| ], |
| [ |
| "HCLK_NN6E1", |
| "NN6E1" |
| ], |
| [ |
| "HCLK_NN6E2", |
| "NN6E2" |
| ], |
| [ |
| "HCLK_NN6E3", |
| "NN6E3" |
| ], |
| [ |
| "HCLK_NN6END_S1_0", |
| "NN6E0" |
| ], |
| [ |
| "HCLK_NR1BEG0", |
| "NR1BEG0" |
| ], |
| [ |
| "HCLK_NR1BEG1", |
| "NR1BEG1" |
| ], |
| [ |
| "HCLK_NR1BEG2", |
| "NR1BEG2" |
| ], |
| [ |
| "HCLK_NR1BEG3", |
| "NR1BEG3" |
| ], |
| [ |
| "HCLK_NW2A0", |
| "NW2BEG0" |
| ], |
| [ |
| "HCLK_NW2A1", |
| "NW2BEG1" |
| ], |
| [ |
| "HCLK_NW2A2", |
| "NW2BEG2" |
| ], |
| [ |
| "HCLK_NW2A3", |
| "NW2BEG3" |
| ], |
| [ |
| "HCLK_NW2END_S0_0", |
| "NW2END_S0_0" |
| ], |
| [ |
| "HCLK_NW6A0", |
| "NW6A0" |
| ], |
| [ |
| "HCLK_NW6A1", |
| "NW6A1" |
| ], |
| [ |
| "HCLK_NW6A2", |
| "NW6A2" |
| ], |
| [ |
| "HCLK_NW6A3", |
| "NW6A3" |
| ], |
| [ |
| "HCLK_NW6B0", |
| "NW6B0" |
| ], |
| [ |
| "HCLK_NW6B1", |
| "NW6B1" |
| ], |
| [ |
| "HCLK_NW6B2", |
| "NW6B2" |
| ], |
| [ |
| "HCLK_NW6B3", |
| "NW6B3" |
| ], |
| [ |
| "HCLK_NW6C0", |
| "NW6C0" |
| ], |
| [ |
| "HCLK_NW6C1", |
| "NW6C1" |
| ], |
| [ |
| "HCLK_NW6C2", |
| "NW6C2" |
| ], |
| [ |
| "HCLK_NW6C3", |
| "NW6C3" |
| ], |
| [ |
| "HCLK_NW6D0", |
| "NW6D0" |
| ], |
| [ |
| "HCLK_NW6D1", |
| "NW6D1" |
| ], |
| [ |
| "HCLK_NW6D2", |
| "NW6D2" |
| ], |
| [ |
| "HCLK_NW6D3", |
| "NW6D3" |
| ], |
| [ |
| "HCLK_NW6END_S0_0", |
| "NW6END_S0_0" |
| ], |
| [ |
| "HCLK_SE2A0", |
| "SE2A0" |
| ], |
| [ |
| "HCLK_SE2A1", |
| "SE2A1" |
| ], |
| [ |
| "HCLK_SE2A2", |
| "SE2A2" |
| ], |
| [ |
| "HCLK_SE2A3", |
| "SE2A3" |
| ], |
| [ |
| "HCLK_SE6B0", |
| "SE6B0" |
| ], |
| [ |
| "HCLK_SE6B1", |
| "SE6B1" |
| ], |
| [ |
| "HCLK_SE6B2", |
| "SE6B2" |
| ], |
| [ |
| "HCLK_SE6B3", |
| "SE6B3" |
| ], |
| [ |
| "HCLK_SE6C0", |
| "SE6C0" |
| ], |
| [ |
| "HCLK_SE6C1", |
| "SE6C1" |
| ], |
| [ |
| "HCLK_SE6C2", |
| "SE6C2" |
| ], |
| [ |
| "HCLK_SE6C3", |
| "SE6C3" |
| ], |
| [ |
| "HCLK_SE6D0", |
| "SE6D0" |
| ], |
| [ |
| "HCLK_SE6D1", |
| "SE6D1" |
| ], |
| [ |
| "HCLK_SE6D2", |
| "SE6D2" |
| ], |
| [ |
| "HCLK_SE6D3", |
| "SE6D3" |
| ], |
| [ |
| "HCLK_SE6E0", |
| "SE6E0" |
| ], |
| [ |
| "HCLK_SE6E1", |
| "SE6E1" |
| ], |
| [ |
| "HCLK_SE6E2", |
| "SE6E2" |
| ], |
| [ |
| "HCLK_SE6E3", |
| "SE6E3" |
| ], |
| [ |
| "HCLK_SL1END0", |
| "SL1END0" |
| ], |
| [ |
| "HCLK_SL1END1", |
| "SL1END1" |
| ], |
| [ |
| "HCLK_SL1END2", |
| "SL1END2" |
| ], |
| [ |
| "HCLK_SL1END3", |
| "SL1END3" |
| ], |
| [ |
| "HCLK_SR1END1", |
| "SR1END1" |
| ], |
| [ |
| "HCLK_SR1END2", |
| "SR1END2" |
| ], |
| [ |
| "HCLK_SR1END_N3_3", |
| "SR1END3" |
| ], |
| [ |
| "HCLK_SS2A0", |
| "SS2A0" |
| ], |
| [ |
| "HCLK_SS2A1", |
| "SS2A1" |
| ], |
| [ |
| "HCLK_SS2A2", |
| "SS2A2" |
| ], |
| [ |
| "HCLK_SS2BEG3", |
| "SS2A3" |
| ], |
| [ |
| "HCLK_SS2END0", |
| "SS2END0" |
| ], |
| [ |
| "HCLK_SS2END1", |
| "SS2END1" |
| ], |
| [ |
| "HCLK_SS2END2", |
| "SS2END2" |
| ], |
| [ |
| "HCLK_SS2END_N0_3", |
| "SS2END3" |
| ], |
| [ |
| "HCLK_SS6A0", |
| "SS6A0" |
| ], |
| [ |
| "HCLK_SS6A1", |
| "SS6A1" |
| ], |
| [ |
| "HCLK_SS6A2", |
| "SS6A2" |
| ], |
| [ |
| "HCLK_SS6A3", |
| "SS6A3" |
| ], |
| [ |
| "HCLK_SS6B0", |
| "SS6B0" |
| ], |
| [ |
| "HCLK_SS6B1", |
| "SS6B1" |
| ], |
| [ |
| "HCLK_SS6B2", |
| "SS6B2" |
| ], |
| [ |
| "HCLK_SS6B3", |
| "SS6B3" |
| ], |
| [ |
| "HCLK_SS6C0", |
| "SS6C0" |
| ], |
| [ |
| "HCLK_SS6C1", |
| "SS6C1" |
| ], |
| [ |
| "HCLK_SS6C2", |
| "SS6C2" |
| ], |
| [ |
| "HCLK_SS6C3", |
| "SS6C3" |
| ], |
| [ |
| "HCLK_SS6D0", |
| "SS6D0" |
| ], |
| [ |
| "HCLK_SS6D1", |
| "SS6D1" |
| ], |
| [ |
| "HCLK_SS6D2", |
| "SS6D2" |
| ], |
| [ |
| "HCLK_SS6D3", |
| "SS6D3" |
| ], |
| [ |
| "HCLK_SS6E0", |
| "SS6E0" |
| ], |
| [ |
| "HCLK_SS6E1", |
| "SS6E1" |
| ], |
| [ |
| "HCLK_SS6E2", |
| "SS6E2" |
| ], |
| [ |
| "HCLK_SS6E3", |
| "SS6E3" |
| ], |
| [ |
| "HCLK_SS6END0", |
| "SS6END0" |
| ], |
| [ |
| "HCLK_SS6END1", |
| "SS6END1" |
| ], |
| [ |
| "HCLK_SS6END2", |
| "SS6END2" |
| ], |
| [ |
| "HCLK_SS6END_N0_3", |
| "SS6END3" |
| ], |
| [ |
| "HCLK_SW2A3", |
| "SW2A3" |
| ], |
| [ |
| "HCLK_SW2END0", |
| "SW2A0" |
| ], |
| [ |
| "HCLK_SW2END1", |
| "SW2A1" |
| ], |
| [ |
| "HCLK_SW2END2", |
| "SW2A2" |
| ], |
| [ |
| "HCLK_SW2END_N0_3", |
| "SW2END3" |
| ], |
| [ |
| "HCLK_SW6B0", |
| "SW6B0" |
| ], |
| [ |
| "HCLK_SW6B1", |
| "SW6B1" |
| ], |
| [ |
| "HCLK_SW6B2", |
| "SW6B2" |
| ], |
| [ |
| "HCLK_SW6B3", |
| "SW6B3" |
| ], |
| [ |
| "HCLK_SW6C0", |
| "SW6C0" |
| ], |
| [ |
| "HCLK_SW6C1", |
| "SW6C1" |
| ], |
| [ |
| "HCLK_SW6C2", |
| "SW6C2" |
| ], |
| [ |
| "HCLK_SW6C3", |
| "SW6C3" |
| ], |
| [ |
| "HCLK_SW6D0", |
| "SW6D0" |
| ], |
| [ |
| "HCLK_SW6D1", |
| "SW6D1" |
| ], |
| [ |
| "HCLK_SW6D2", |
| "SW6D2" |
| ], |
| [ |
| "HCLK_SW6D3", |
| "SW6D3" |
| ], |
| [ |
| "HCLK_SW6E0", |
| "SW6E0" |
| ], |
| [ |
| "HCLK_SW6E1", |
| "SW6E1" |
| ], |
| [ |
| "HCLK_SW6E2", |
| "SW6E2" |
| ], |
| [ |
| "HCLK_SW6E3", |
| "SW6E3" |
| ], |
| [ |
| "HCLK_SW6END3", |
| "SW6END3" |
| ], |
| [ |
| "HCLK_WL1BEG3", |
| "WL1BEG3" |
| ], |
| [ |
| "HCLK_WL1END3", |
| "WL1END3" |
| ], |
| [ |
| "HCLK_WR1BEG_S0", |
| "WR1BEG_S0" |
| ], |
| [ |
| "HCLK_WR1END_S1_0", |
| "WR1END_S1_0" |
| ], |
| [ |
| "HCLK_WW2END3", |
| "WW2END3" |
| ], |
| [ |
| "HCLK_WW4END_S0_0", |
| "WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "HCLK_VBRK", |
| "HCLK_CLB" |
| ], |
| "wire_pairs": [ |
| [ |
| "HCLK_VBRK_CK_BUFHCLK0", |
| "HCLK_CLB_CK_BUFHCLK0" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK1", |
| "HCLK_CLB_CK_BUFHCLK1" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK10", |
| "HCLK_CLB_CK_BUFHCLK10" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK11", |
| "HCLK_CLB_CK_BUFHCLK11" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK2", |
| "HCLK_CLB_CK_BUFHCLK2" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK3", |
| "HCLK_CLB_CK_BUFHCLK3" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK4", |
| "HCLK_CLB_CK_BUFHCLK4" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK5", |
| "HCLK_CLB_CK_BUFHCLK5" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK6", |
| "HCLK_CLB_CK_BUFHCLK6" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK7", |
| "HCLK_CLB_CK_BUFHCLK7" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK8", |
| "HCLK_CLB_CK_BUFHCLK8" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFHCLK9", |
| "HCLK_CLB_CK_BUFHCLK9" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFRCLK0", |
| "HCLK_CLB_CK_BUFRCLK0" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFRCLK1", |
| "HCLK_CLB_CK_BUFRCLK1" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFRCLK2", |
| "HCLK_CLB_CK_BUFRCLK2" |
| ], |
| [ |
| "HCLK_VBRK_CK_BUFRCLK3", |
| "HCLK_CLB_CK_BUFRCLK3" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK0", |
| "HCLK_CLB_CK_IN0" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK1", |
| "HCLK_CLB_CK_IN1" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK10", |
| "HCLK_CLB_CK_IN10" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK11", |
| "HCLK_CLB_CK_IN11" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK12", |
| "HCLK_CLB_CK_IN12" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK13", |
| "HCLK_CLB_CK_IN13" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK2", |
| "HCLK_CLB_CK_IN2" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK3", |
| "HCLK_CLB_CK_IN3" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK4", |
| "HCLK_CLB_CK_IN4" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK5", |
| "HCLK_CLB_CK_IN5" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK6", |
| "HCLK_CLB_CK_IN6" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK7", |
| "HCLK_CLB_CK_IN7" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK8", |
| "HCLK_CLB_CK_IN8" |
| ], |
| [ |
| "HCLK_VBRK_MUX_CLK9", |
| "HCLK_CLB_CK_IN9" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "INT_L", |
| "BRKH_B_TERM_INT" |
| ], |
| "wire_pairs": [ |
| [ |
| "BYP_BOUNCE_N3_2", |
| "B_TERM_UTURN_INT_FAN_BOUNCE6" |
| ], |
| [ |
| "BYP_BOUNCE_N3_3", |
| "B_TERM_UTURN_INT_FAN_BOUNCE2" |
| ], |
| [ |
| "BYP_BOUNCE_N3_6", |
| "B_TERM_UTURN_INT_FAN_BOUNCE4" |
| ], |
| [ |
| "BYP_BOUNCE_N3_7", |
| "B_TERM_UTURN_INT_FAN_BOUNCE0" |
| ], |
| [ |
| "ER1BEG0", |
| "B_TERM_UTURN_INT_ER1BEG0" |
| ], |
| [ |
| "ER1END_N3_3", |
| "B_TERM_UTURN_INT_ER1END_N3_3" |
| ], |
| [ |
| "LVB_L1", |
| "B_TERM_UTURN_INT_LVB_L0" |
| ], |
| [ |
| "LVB_L10", |
| "B_TERM_UTURN_INT_LVB_L2" |
| ], |
| [ |
| "LVB_L11", |
| "B_TERM_UTURN_INT_LVB_L1" |
| ], |
| [ |
| "LVB_L7", |
| "B_TERM_UTURN_INT_LVB_L5" |
| ], |
| [ |
| "LVB_L8", |
| "B_TERM_UTURN_INT_LVB_L4" |
| ], |
| [ |
| "LVB_L9", |
| "B_TERM_UTURN_INT_LVB_L3" |
| ], |
| [ |
| "LV_L1", |
| "B_TERM_UTURN_INT_LV_L18" |
| ], |
| [ |
| "LV_L10", |
| "B_TERM_UTURN_INT_LV_L9" |
| ], |
| [ |
| "LV_L11", |
| "B_TERM_UTURN_INT_LV_L8" |
| ], |
| [ |
| "LV_L12", |
| "B_TERM_UTURN_INT_LV_L7" |
| ], |
| [ |
| "LV_L13", |
| "B_TERM_UTURN_INT_LV_L6" |
| ], |
| [ |
| "LV_L14", |
| "B_TERM_UTURN_INT_LV_L5" |
| ], |
| [ |
| "LV_L15", |
| "B_TERM_UTURN_INT_LV_L4" |
| ], |
| [ |
| "LV_L16", |
| "B_TERM_UTURN_INT_LV_L3" |
| ], |
| [ |
| "LV_L17", |
| "B_TERM_UTURN_INT_LV_L2" |
| ], |
| [ |
| "NE2A0", |
| "B_TERM_UTURN_INT_SE2BEG3" |
| ], |
| [ |
| "NE2A1", |
| "B_TERM_UTURN_INT_SE2BEG2" |
| ], |
| [ |
| "NE2A2", |
| "B_TERM_UTURN_INT_SE2BEG1" |
| ], |
| [ |
| "NE2A3", |
| "B_TERM_UTURN_INT_SE2BEG0" |
| ], |
| [ |
| "NE6B0", |
| "B_TERM_UTURN_INT_SE6A3" |
| ], |
| [ |
| "NE6B1", |
| "B_TERM_UTURN_INT_SE6A2" |
| ], |
| [ |
| "NE6B2", |
| "B_TERM_UTURN_INT_SE6A1" |
| ], |
| [ |
| "NE6B3", |
| "B_TERM_UTURN_INT_SE6A0" |
| ], |
| [ |
| "NE6C0", |
| "B_TERM_UTURN_INT_SE6B3" |
| ], |
| [ |
| "NE6C1", |
| "B_TERM_UTURN_INT_SE6B2" |
| ], |
| [ |
| "NE6C2", |
| "B_TERM_UTURN_INT_SE6B1" |
| ], |
| [ |
| "NE6C3", |
| "B_TERM_UTURN_INT_SE6B0" |
| ], |
| [ |
| "NE6D0", |
| "B_TERM_UTURN_INT_SE6C3" |
| ], |
| [ |
| "NE6D1", |
| "B_TERM_UTURN_INT_SE6C2" |
| ], |
| [ |
| "NE6D2", |
| "B_TERM_UTURN_INT_SE6C1" |
| ], |
| [ |
| "NE6D3", |
| "B_TERM_UTURN_INT_SE6C0" |
| ], |
| [ |
| "NE6E0", |
| "B_TERM_UTURN_INT_SE6D3" |
| ], |
| [ |
| "NE6E1", |
| "B_TERM_UTURN_INT_SE6D2" |
| ], |
| [ |
| "NE6E2", |
| "B_TERM_UTURN_INT_SE6D1" |
| ], |
| [ |
| "NE6E3", |
| "B_TERM_UTURN_INT_SE6D0" |
| ], |
| [ |
| "NL1END0", |
| "B_TERM_UTURN_INT_SR1BEG3" |
| ], |
| [ |
| "NL1END1", |
| "B_TERM_UTURN_INT_SR1BEG2" |
| ], |
| [ |
| "NL1END2", |
| "B_TERM_UTURN_INT_SR1BEG1" |
| ], |
| [ |
| "NN2A0", |
| "B_TERM_UTURN_INT_SS2BEG3" |
| ], |
| [ |
| "NN2A1", |
| "B_TERM_UTURN_INT_SS2BEG2" |
| ], |
| [ |
| "NN2A2", |
| "B_TERM_UTURN_INT_SS2BEG1" |
| ], |
| [ |
| "NN2A3", |
| "B_TERM_UTURN_INT_SS2BEG0" |
| ], |
| [ |
| "NN6A0", |
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| ], |
| [ |
| "NN6A1", |
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| ], |
| [ |
| "NN6A2", |
| "B_TERM_UTURN_INT_SS6BEG1" |
| ], |
| [ |
| "NN6A3", |
| "B_TERM_UTURN_INT_SS6BEG0" |
| ], |
| [ |
| "NN6B0", |
| "B_TERM_UTURN_INT_SS6A3" |
| ], |
| [ |
| "NN6B1", |
| "B_TERM_UTURN_INT_SS6A2" |
| ], |
| [ |
| "NN6B2", |
| "B_TERM_UTURN_INT_SS6A1" |
| ], |
| [ |
| "NN6B3", |
| "B_TERM_UTURN_INT_SS6A0" |
| ], |
| [ |
| "NN6C0", |
| "B_TERM_UTURN_INT_SS6B3" |
| ], |
| [ |
| "NN6C1", |
| "B_TERM_UTURN_INT_SS6B2" |
| ], |
| [ |
| "NN6C2", |
| "B_TERM_UTURN_INT_SS6B1" |
| ], |
| [ |
| "NN6C3", |
| "B_TERM_UTURN_INT_SS6B0" |
| ], |
| [ |
| "NN6D0", |
| "B_TERM_UTURN_INT_SS6C3" |
| ], |
| [ |
| "NN6D1", |
| "B_TERM_UTURN_INT_SS6C2" |
| ], |
| [ |
| "NN6D2", |
| "B_TERM_UTURN_INT_SS6C1" |
| ], |
| [ |
| "NN6D3", |
| "B_TERM_UTURN_INT_SS6C0" |
| ], |
| [ |
| "NN6E0", |
| "B_TERM_UTURN_INT_SS6D3" |
| ], |
| [ |
| "NN6E1", |
| "B_TERM_UTURN_INT_SS6D2" |
| ], |
| [ |
| "NN6E2", |
| "B_TERM_UTURN_INT_SS6D1" |
| ], |
| [ |
| "NN6E3", |
| "B_TERM_UTURN_INT_SS6D0" |
| ], |
| [ |
| "NR1END0", |
| "B_TERM_UTURN_INT_SL1BEG3" |
| ], |
| [ |
| "NR1END1", |
| "B_TERM_UTURN_INT_SL1BEG2" |
| ], |
| [ |
| "NR1END2", |
| "B_TERM_UTURN_INT_SL1BEG1" |
| ], |
| [ |
| "NR1END3", |
| "B_TERM_UTURN_INT_SL1BEG0" |
| ], |
| [ |
| "NW2A0", |
| "B_TERM_UTURN_INT_SW2BEG3" |
| ], |
| [ |
| "NW2A1", |
| "B_TERM_UTURN_INT_SW2BEG2" |
| ], |
| [ |
| "NW2A2", |
| "B_TERM_UTURN_INT_SW2BEG1" |
| ], |
| [ |
| "NW2A3", |
| "B_TERM_UTURN_INT_SW2BEG0" |
| ], |
| [ |
| "NW6B0", |
| "B_TERM_UTURN_INT_SW6A3" |
| ], |
| [ |
| "NW6B1", |
| "B_TERM_UTURN_INT_SW6A2" |
| ], |
| [ |
| "NW6B2", |
| "B_TERM_UTURN_INT_SW6A1" |
| ], |
| [ |
| "NW6B3", |
| "B_TERM_UTURN_INT_SW6A0" |
| ], |
| [ |
| "NW6C0", |
| "B_TERM_UTURN_INT_SW6B3" |
| ], |
| [ |
| "NW6C1", |
| "B_TERM_UTURN_INT_SW6B2" |
| ], |
| [ |
| "NW6C2", |
| "B_TERM_UTURN_INT_SW6B1" |
| ], |
| [ |
| "NW6C3", |
| "B_TERM_UTURN_INT_SW6B0" |
| ], |
| [ |
| "NW6D0", |
| "B_TERM_UTURN_INT_SW6C3" |
| ], |
| [ |
| "NW6D1", |
| "B_TERM_UTURN_INT_SW6C2" |
| ], |
| [ |
| "NW6D2", |
| "B_TERM_UTURN_INT_SW6C1" |
| ], |
| [ |
| "NW6D3", |
| "B_TERM_UTURN_INT_SW6C0" |
| ], |
| [ |
| "NW6E0", |
| "B_TERM_UTURN_INT_SW6D3" |
| ], |
| [ |
| "NW6E1", |
| "B_TERM_UTURN_INT_SW6D2" |
| ], |
| [ |
| "NW6E2", |
| "B_TERM_UTURN_INT_SW6D1" |
| ], |
| [ |
| "NW6E3", |
| "B_TERM_UTURN_INT_SW6D0" |
| ], |
| [ |
| "SS2A0", |
| "B_TERM_UTURN_INT_SS2A0" |
| ], |
| [ |
| "SS2A1", |
| "B_TERM_UTURN_INT_SS2A1" |
| ], |
| [ |
| "SS2A2", |
| "B_TERM_UTURN_INT_SS2A2" |
| ], |
| [ |
| "SS2A3", |
| "B_TERM_UTURN_INT_SS2A3" |
| ], |
| [ |
| "SS6E0", |
| "B_TERM_UTURN_INT_SS6E0" |
| ], |
| [ |
| "SS6E1", |
| "B_TERM_UTURN_INT_SS6E1" |
| ], |
| [ |
| "SS6E2", |
| "B_TERM_UTURN_INT_SS6E2" |
| ], |
| [ |
| "SS6E3", |
| "B_TERM_UTURN_INT_SS6E3" |
| ], |
| [ |
| "SW6END_N0_3", |
| "B_TERM_UTURN_INT_SW6END_N0_3" |
| ], |
| [ |
| "WL1END_N1_3", |
| "B_TERM_UTURN_INT_WR1END0" |
| ], |
| [ |
| "WR1BEG0", |
| "B_TERM_UTURN_INT_WR1BEG0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "INT_L", |
| "BRKH_INT" |
| ], |
| "wire_pairs": [ |
| [ |
| "BYP_BOUNCE_N3_2", |
| "BRKH_INT_BYP_BOUNCE2" |
| ], |
| [ |
| "BYP_BOUNCE_N3_3", |
| "BRKH_INT_BYP_BOUNCE3" |
| ], |
| [ |
| "BYP_BOUNCE_N3_6", |
| "BRKH_INT_BYP_BOUNCE6" |
| ], |
| [ |
| "BYP_BOUNCE_N3_7", |
| "BRKH_INT_BYP_BOUNCE7" |
| ], |
| [ |
| "EL1BEG_N3", |
| "BRKH_INT_EL1BEG3" |
| ], |
| [ |
| "EL1END0", |
| "BRKH_INT_EL1END_S3_0" |
| ], |
| [ |
| "ER1BEG0", |
| "BRKH_INT_ER1BEG_S0" |
| ], |
| [ |
| "ER1END_N3_3", |
| "BRKH_INT_ER1END3" |
| ], |
| [ |
| "FAN_BOUNCE0", |
| "BRKH_INT_FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "FAN_BOUNCE2", |
| "BRKH_INT_FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "FAN_BOUNCE4", |
| "BRKH_INT_FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "FAN_BOUNCE6", |
| "BRKH_INT_FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "LVB_L1", |
| "BRKH_INT_LVB_L1" |
| ], |
| [ |
| "LVB_L10", |
| "BRKH_INT_LVB_L10" |
| ], |
| [ |
| "LVB_L11", |
| "BRKH_INT_LVB_L11" |
| ], |
| [ |
| "LVB_L12", |
| "BRKH_INT_LVB_L12" |
| ], |
| [ |
| "LVB_L2", |
| "BRKH_INT_LVB_L2" |
| ], |
| [ |
| "LVB_L3", |
| "BRKH_INT_LVB_L3" |
| ], |
| [ |
| "LVB_L4", |
| "BRKH_INT_LVB_L4" |
| ], |
| [ |
| "LVB_L5", |
| "BRKH_INT_LVB_L5" |
| ], |
| [ |
| "LVB_L6", |
| "BRKH_INT_LVB_L6" |
| ], |
| [ |
| "LVB_L7", |
| "BRKH_INT_LVB_L7" |
| ], |
| [ |
| "LVB_L8", |
| "BRKH_INT_LVB_L8" |
| ], |
| [ |
| "LVB_L9", |
| "BRKH_INT_LVB_L9" |
| ], |
| [ |
| "LV_L1", |
| "BRKH_INT_L_LV0" |
| ], |
| [ |
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| "BRKH_INT_L_LV9" |
| ], |
| [ |
| "LV_L11", |
| "BRKH_INT_L_LV10" |
| ], |
| [ |
| "LV_L12", |
| "BRKH_INT_L_LV11" |
| ], |
| [ |
| "LV_L13", |
| "BRKH_INT_L_LV12" |
| ], |
| [ |
| "LV_L14", |
| "BRKH_INT_L_LV13" |
| ], |
| [ |
| "LV_L15", |
| "BRKH_INT_L_LV14" |
| ], |
| [ |
| "LV_L16", |
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| ], |
| [ |
| "LV_L17", |
| "BRKH_INT_L_LV16" |
| ], |
| [ |
| "LV_L18", |
| "BRKH_INT_L_LV17" |
| ], |
| [ |
| "LV_L2", |
| "BRKH_INT_L_LV1" |
| ], |
| [ |
| "LV_L3", |
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| ], |
| [ |
| "LV_L4", |
| "BRKH_INT_L_LV3" |
| ], |
| [ |
| "LV_L5", |
| "BRKH_INT_L_LV4" |
| ], |
| [ |
| "LV_L6", |
| "BRKH_INT_L_LV5" |
| ], |
| [ |
| "LV_L7", |
| "BRKH_INT_L_LV6" |
| ], |
| [ |
| "LV_L8", |
| "BRKH_INT_L_LV7" |
| ], |
| [ |
| "LV_L9", |
| "BRKH_INT_L_LV8" |
| ], |
| [ |
| "NE2A0", |
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| ], |
| [ |
| "NE2A1", |
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| ], |
| [ |
| "NE2A2", |
| "BRKH_INT_NE2BEG2" |
| ], |
| [ |
| "NE2A3", |
| "BRKH_INT_NE2BEG3" |
| ], |
| [ |
| "NE2END0", |
| "BRKH_INT_NE2END_S3_0" |
| ], |
| [ |
| "NE6B0", |
| "BRKH_INT_NE6A0" |
| ], |
| [ |
| "NE6B1", |
| "BRKH_INT_NE6A1" |
| ], |
| [ |
| "NE6B2", |
| "BRKH_INT_NE6A2" |
| ], |
| [ |
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| ], |
| [ |
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| "BRKH_INT_NE6B0" |
| ], |
| [ |
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| [ |
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| ], |
| [ |
| "NE6C3", |
| "BRKH_INT_NE6B3" |
| ], |
| [ |
| "NE6D0", |
| "BRKH_INT_NE6C0" |
| ], |
| [ |
| "NE6D1", |
| "BRKH_INT_NE6C1" |
| ], |
| [ |
| "NE6D2", |
| "BRKH_INT_NE6C2" |
| ], |
| [ |
| "NE6D3", |
| "BRKH_INT_NE6C3" |
| ], |
| [ |
| "NE6E0", |
| "BRKH_INT_NE6D0" |
| ], |
| [ |
| "NE6E1", |
| "BRKH_INT_NE6D1" |
| ], |
| [ |
| "NE6E2", |
| "BRKH_INT_NE6D2" |
| ], |
| [ |
| "NE6E3", |
| "BRKH_INT_NE6D3" |
| ], |
| [ |
| "NL1END0", |
| "BRKH_INT_NL1END_S3_0" |
| ], |
| [ |
| "NL1END1", |
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| ], |
| [ |
| "NL1END2", |
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| ], |
| [ |
| "NN2A0", |
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| ], |
| [ |
| "NN2A1", |
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| ], |
| [ |
| "NN2A2", |
| "BRKH_INT_NN2BEG2" |
| ], |
| [ |
| "NN2A3", |
| "BRKH_INT_NN2BEG3" |
| ], |
| [ |
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| "BRKH_INT_NN2END_S2_0" |
| ], |
| [ |
| "NN2END1", |
| "BRKH_INT_NN2A1" |
| ], |
| [ |
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| "BRKH_INT_NN2A2" |
| ], |
| [ |
| "NN2END3", |
| "BRKH_INT_NN2A3" |
| ], |
| [ |
| "NN6A0", |
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| ], |
| [ |
| "NN6A1", |
| "BRKH_INT_NN6BEG1" |
| ], |
| [ |
| "NN6A2", |
| "BRKH_INT_NN6BEG2" |
| ], |
| [ |
| "NN6A3", |
| "BRKH_INT_NN6BEG3" |
| ], |
| [ |
| "NN6B0", |
| "BRKH_INT_NN6A0" |
| ], |
| [ |
| "NN6B1", |
| "BRKH_INT_NN6A1" |
| ], |
| [ |
| "NN6B2", |
| "BRKH_INT_NN6A2" |
| ], |
| [ |
| "NN6B3", |
| "BRKH_INT_NN6A3" |
| ], |
| [ |
| "NN6C0", |
| "BRKH_INT_NN6B0" |
| ], |
| [ |
| "NN6C1", |
| "BRKH_INT_NN6B1" |
| ], |
| [ |
| "NN6C2", |
| "BRKH_INT_NN6B2" |
| ], |
| [ |
| "NN6C3", |
| "BRKH_INT_NN6B3" |
| ], |
| [ |
| "NN6D0", |
| "BRKH_INT_NN6C0" |
| ], |
| [ |
| "NN6D1", |
| "BRKH_INT_NN6C1" |
| ], |
| [ |
| "NN6D2", |
| "BRKH_INT_NN6C2" |
| ], |
| [ |
| "NN6D3", |
| "BRKH_INT_NN6C3" |
| ], |
| [ |
| "NN6E0", |
| "BRKH_INT_NN6D0" |
| ], |
| [ |
| "NN6E1", |
| "BRKH_INT_NN6D1" |
| ], |
| [ |
| "NN6E2", |
| "BRKH_INT_NN6D2" |
| ], |
| [ |
| "NN6E3", |
| "BRKH_INT_NN6D3" |
| ], |
| [ |
| "NN6END0", |
| "BRKH_INT_NN6END_S1_0" |
| ], |
| [ |
| "NN6END1", |
| "BRKH_INT_NN6E1" |
| ], |
| [ |
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| ], |
| [ |
| "NN6END3", |
| "BRKH_INT_NN6E3" |
| ], |
| [ |
| "NR1END0", |
| "BRKH_INT_NR1BEG0_SLOW" |
| ], |
| [ |
| "NR1END1", |
| "BRKH_INT_NR1BEG1_SLOW" |
| ], |
| [ |
| "NR1END2", |
| "BRKH_INT_NR1BEG2_SLOW" |
| ], |
| [ |
| "NR1END3", |
| "BRKH_INT_NR1BEG3_SLOW" |
| ], |
| [ |
| "NW2A0", |
| "BRKH_INT_NW2BEG0" |
| ], |
| [ |
| "NW2A1", |
| "BRKH_INT_NW2BEG1" |
| ], |
| [ |
| "NW2A2", |
| "BRKH_INT_NW2BEG2" |
| ], |
| [ |
| "NW2A3", |
| "BRKH_INT_NW2BEG3" |
| ], |
| [ |
| "NW2END0", |
| "BRKH_INT_NW2END_S0_0" |
| ], |
| [ |
| "NW6B0", |
| "BRKH_INT_NW6A0" |
| ], |
| [ |
| "NW6B1", |
| "BRKH_INT_NW6A1" |
| ], |
| [ |
| "NW6B2", |
| "BRKH_INT_NW6A2" |
| ], |
| [ |
| "NW6B3", |
| "BRKH_INT_NW6A3" |
| ], |
| [ |
| "NW6C0", |
| "BRKH_INT_NW6B0" |
| ], |
| [ |
| "NW6C1", |
| "BRKH_INT_NW6B1" |
| ], |
| [ |
| "NW6C2", |
| "BRKH_INT_NW6B2" |
| ], |
| [ |
| "NW6C3", |
| "BRKH_INT_NW6B3" |
| ], |
| [ |
| "NW6D0", |
| "BRKH_INT_NW6C0" |
| ], |
| [ |
| "NW6D1", |
| "BRKH_INT_NW6C1" |
| ], |
| [ |
| "NW6D2", |
| "BRKH_INT_NW6C2" |
| ], |
| [ |
| "NW6D3", |
| "BRKH_INT_NW6C3" |
| ], |
| [ |
| "NW6E0", |
| "BRKH_INT_NW6D0" |
| ], |
| [ |
| "NW6E1", |
| "BRKH_INT_NW6D1" |
| ], |
| [ |
| "NW6E2", |
| "BRKH_INT_NW6D2" |
| ], |
| [ |
| "NW6E3", |
| "BRKH_INT_NW6D3" |
| ], |
| [ |
| "NW6END0", |
| "BRKH_INT_NW6END_S0_0" |
| ], |
| [ |
| "SE2BEG0", |
| "BRKH_INT_SE2A0" |
| ], |
| [ |
| "SE2BEG1", |
| "BRKH_INT_SE2A1" |
| ], |
| [ |
| "SE2BEG2", |
| "BRKH_INT_SE2A2" |
| ], |
| [ |
| "SE2BEG3", |
| "BRKH_INT_SE2A3" |
| ], |
| [ |
| "SE6A0", |
| "BRKH_INT_SE6B0" |
| ], |
| [ |
| "SE6A1", |
| "BRKH_INT_SE6B1" |
| ], |
| [ |
| "SE6A2", |
| "BRKH_INT_SE6B2" |
| ], |
| [ |
| "SE6A3", |
| "BRKH_INT_SE6B3" |
| ], |
| [ |
| "SE6B0", |
| "BRKH_INT_SE6C0" |
| ], |
| [ |
| "SE6B1", |
| "BRKH_INT_SE6C1" |
| ], |
| [ |
| "SE6B2", |
| "BRKH_INT_SE6C2" |
| ], |
| [ |
| "SE6B3", |
| "BRKH_INT_SE6C3" |
| ], |
| [ |
| "SE6C0", |
| "BRKH_INT_SE6D0" |
| ], |
| [ |
| "SE6C1", |
| "BRKH_INT_SE6D1" |
| ], |
| [ |
| "SE6C2", |
| "BRKH_INT_SE6D2" |
| ], |
| [ |
| "SE6C3", |
| "BRKH_INT_SE6D3" |
| ], |
| [ |
| "SE6D0", |
| "BRKH_INT_SE6E0" |
| ], |
| [ |
| "SE6D1", |
| "BRKH_INT_SE6E1" |
| ], |
| [ |
| "SE6D2", |
| "BRKH_INT_SE6E2" |
| ], |
| [ |
| "SE6D3", |
| "BRKH_INT_SE6E3" |
| ], |
| [ |
| "SL1BEG0", |
| "BRKH_INT_SL1END0_SLOW" |
| ], |
| [ |
| "SL1BEG1", |
| "BRKH_INT_SL1END1_SLOW" |
| ], |
| [ |
| "SL1BEG2", |
| "BRKH_INT_SL1END2_SLOW" |
| ], |
| [ |
| "SL1BEG3", |
| "BRKH_INT_SL1END3_SLOW" |
| ], |
| [ |
| "SR1BEG1", |
| "BRKH_INT_SR1END1_SLOW" |
| ], |
| [ |
| "SR1BEG2", |
| "BRKH_INT_SR1END2_SLOW" |
| ], |
| [ |
| "SR1BEG3", |
| "BRKH_INT_SR1END3_SLOW" |
| ], |
| [ |
| "SR1END_N3_3", |
| "BRKH_INT_SR1END_N3_3" |
| ], |
| [ |
| "SS2A0", |
| "BRKH_INT_SS2END0" |
| ], |
| [ |
| "SS2A1", |
| "BRKH_INT_SS2END1" |
| ], |
| [ |
| "SS2A2", |
| "BRKH_INT_SS2END2" |
| ], |
| [ |
| "SS2A3", |
| "BRKH_INT_SS2END_N0_3" |
| ], |
| [ |
| "SS2BEG0", |
| "BRKH_INT_SS2A0" |
| ], |
| [ |
| "SS2BEG1", |
| "BRKH_INT_SS2A1" |
| ], |
| [ |
| "SS2BEG2", |
| "BRKH_INT_SS2A2" |
| ], |
| [ |
| "SS2BEG3", |
| "BRKH_INT_SS2A3" |
| ], |
| [ |
| "SS6A0", |
| "BRKH_INT_SS6B0" |
| ], |
| [ |
| "SS6A1", |
| "BRKH_INT_SS6B1" |
| ], |
| [ |
| "SS6A2", |
| "BRKH_INT_SS6B2" |
| ], |
| [ |
| "SS6A3", |
| "BRKH_INT_SS6B3" |
| ], |
| [ |
| "SS6B0", |
| "BRKH_INT_SS6C0" |
| ], |
| [ |
| "SS6B1", |
| "BRKH_INT_SS6C1" |
| ], |
| [ |
| "SS6B2", |
| "BRKH_INT_SS6C2" |
| ], |
| [ |
| "SS6B3", |
| "BRKH_INT_SS6C3" |
| ], |
| [ |
| "SS6BEG0", |
| "BRKH_INT_SS6A0" |
| ], |
| [ |
| "SS6BEG1", |
| "BRKH_INT_SS6A1" |
| ], |
| [ |
| "SS6BEG2", |
| "BRKH_INT_SS6A2" |
| ], |
| [ |
| "SS6BEG3", |
| "BRKH_INT_SS6A3" |
| ], |
| [ |
| "SS6C0", |
| "BRKH_INT_SS6D0" |
| ], |
| [ |
| "SS6C1", |
| "BRKH_INT_SS6D1" |
| ], |
| [ |
| "SS6C2", |
| "BRKH_INT_SS6D2" |
| ], |
| [ |
| "SS6C3", |
| "BRKH_INT_SS6D3" |
| ], |
| [ |
| "SS6D0", |
| "BRKH_INT_SS6E0" |
| ], |
| [ |
| "SS6D1", |
| "BRKH_INT_SS6E1" |
| ], |
| [ |
| "SS6D2", |
| "BRKH_INT_SS6E2" |
| ], |
| [ |
| "SS6D3", |
| "BRKH_INT_SS6E3" |
| ], |
| [ |
| "SS6E0", |
| "BRKH_INT_SS6END0" |
| ], |
| [ |
| "SS6E1", |
| "BRKH_INT_SS6END1" |
| ], |
| [ |
| "SS6E2", |
| "BRKH_INT_SS6END2" |
| ], |
| [ |
| "SS6E3", |
| "BRKH_INT_SS6END_N0_3" |
| ], |
| [ |
| "SW2BEG0", |
| "BRKH_INT_SW2A0" |
| ], |
| [ |
| "SW2BEG1", |
| "BRKH_INT_SW2A1" |
| ], |
| [ |
| "SW2BEG2", |
| "BRKH_INT_SW2A2" |
| ], |
| [ |
| "SW2BEG3", |
| "BRKH_INT_SW2A3" |
| ], |
| [ |
| "SW2END_N0_3", |
| "BRKH_INT_SW2END3" |
| ], |
| [ |
| "SW6A0", |
| "BRKH_INT_SW6B0" |
| ], |
| [ |
| "SW6A1", |
| "BRKH_INT_SW6B1" |
| ], |
| [ |
| "SW6A2", |
| "BRKH_INT_SW6B2" |
| ], |
| [ |
| "SW6A3", |
| "BRKH_INT_SW6B3" |
| ], |
| [ |
| "SW6B0", |
| "BRKH_INT_SW6C0" |
| ], |
| [ |
| "SW6B1", |
| "BRKH_INT_SW6C1" |
| ], |
| [ |
| "SW6B2", |
| "BRKH_INT_SW6C2" |
| ], |
| [ |
| "SW6B3", |
| "BRKH_INT_SW6C3" |
| ], |
| [ |
| "SW6C0", |
| "BRKH_INT_SW6D0" |
| ], |
| [ |
| "SW6C1", |
| "BRKH_INT_SW6D1" |
| ], |
| [ |
| "SW6C2", |
| "BRKH_INT_SW6D2" |
| ], |
| [ |
| "SW6C3", |
| "BRKH_INT_SW6D3" |
| ], |
| [ |
| "SW6D0", |
| "BRKH_INT_SW6E0" |
| ], |
| [ |
| "SW6D1", |
| "BRKH_INT_SW6E1" |
| ], |
| [ |
| "SW6D2", |
| "BRKH_INT_SW6E2" |
| ], |
| [ |
| "SW6D3", |
| "BRKH_INT_SW6E3" |
| ], |
| [ |
| "SW6END_N0_3", |
| "BRKH_INT_SW6END3" |
| ], |
| [ |
| "WL1BEG_N3", |
| "BRKH_INT_WL1BEG3" |
| ], |
| [ |
| "WL1END_N1_3", |
| "BRKH_INT_WL1END3" |
| ], |
| [ |
| "WR1BEG0", |
| "BRKH_INT_WR1BEG_S0" |
| ], |
| [ |
| "WR1END0", |
| "BRKH_INT_WR1END_S1_0" |
| ], |
| [ |
| "WW2END_N0_3", |
| "BRKH_INT_WW2END3" |
| ], |
| [ |
| "WW4END0", |
| "BRKH_INT_WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "INT_L", |
| "HCLK_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "BYP_BOUNCE_N3_2", |
| "HCLK_BYP_BOUNCE2" |
| ], |
| [ |
| "BYP_BOUNCE_N3_3", |
| "HCLK_BYP_BOUNCE3" |
| ], |
| [ |
| "BYP_BOUNCE_N3_6", |
| "HCLK_BYP_BOUNCE6" |
| ], |
| [ |
| "BYP_BOUNCE_N3_7", |
| "HCLK_BYP_BOUNCE7" |
| ], |
| [ |
| "EL1BEG_N3", |
| "HCLK_EL1BEG3" |
| ], |
| [ |
| "EL1END0", |
| "HCLK_EL1END_S3_0" |
| ], |
| [ |
| "ER1BEG0", |
| "HCLK_ER1BEG_S0" |
| ], |
| [ |
| "ER1END_N3_3", |
| "HCLK_ER1END3" |
| ], |
| [ |
| "FAN_BOUNCE0", |
| "HCLK_FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "FAN_BOUNCE2", |
| "HCLK_FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "FAN_BOUNCE4", |
| "HCLK_FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "FAN_BOUNCE6", |
| "HCLK_FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "GCLK_L_B10", |
| "HCLK_LEAF_CLK_B_TOPL4" |
| ], |
| [ |
| "GCLK_L_B11", |
| "HCLK_LEAF_CLK_B_TOPL5" |
| ], |
| [ |
| "GCLK_L_B6", |
| "HCLK_LEAF_CLK_B_TOPL0" |
| ], |
| [ |
| "GCLK_L_B7", |
| "HCLK_LEAF_CLK_B_TOPL1" |
| ], |
| [ |
| "GCLK_L_B8", |
| "HCLK_LEAF_CLK_B_TOPL2" |
| ], |
| [ |
| "GCLK_L_B9", |
| "HCLK_LEAF_CLK_B_TOPL3" |
| ], |
| [ |
| "LVB_L1", |
| "HCLK_LVB1" |
| ], |
| [ |
| "LVB_L10", |
| "HCLK_LVB10" |
| ], |
| [ |
| "LVB_L11", |
| "HCLK_LVB11" |
| ], |
| [ |
| "LVB_L12", |
| "HCLK_LVB12" |
| ], |
| [ |
| "LVB_L2", |
| "HCLK_LVB2" |
| ], |
| [ |
| "LVB_L3", |
| "HCLK_LVB3" |
| ], |
| [ |
| "LVB_L4", |
| "HCLK_LVB4" |
| ], |
| [ |
| "LVB_L5", |
| "HCLK_LVB5" |
| ], |
| [ |
| "LVB_L6", |
| "HCLK_LVB6" |
| ], |
| [ |
| "LVB_L7", |
| "HCLK_LVB7" |
| ], |
| [ |
| "LVB_L8", |
| "HCLK_LVB8" |
| ], |
| [ |
| "LVB_L9", |
| "HCLK_LVB9" |
| ], |
| [ |
| "LV_L1", |
| "HCLK_LV0" |
| ], |
| [ |
| "LV_L10", |
| "HCLK_LV9" |
| ], |
| [ |
| "LV_L11", |
| "HCLK_LV10" |
| ], |
| [ |
| "LV_L12", |
| "HCLK_LV11" |
| ], |
| [ |
| "LV_L13", |
| "HCLK_LV12" |
| ], |
| [ |
| "LV_L14", |
| "HCLK_LV13" |
| ], |
| [ |
| "LV_L15", |
| "HCLK_LV14" |
| ], |
| [ |
| "LV_L16", |
| "HCLK_LV15" |
| ], |
| [ |
| "LV_L17", |
| "HCLK_LV16" |
| ], |
| [ |
| "LV_L18", |
| "HCLK_LV17" |
| ], |
| [ |
| "LV_L2", |
| "HCLK_LV1" |
| ], |
| [ |
| "LV_L3", |
| "HCLK_LV2" |
| ], |
| [ |
| "LV_L4", |
| "HCLK_LV3" |
| ], |
| [ |
| "LV_L5", |
| "HCLK_LV4" |
| ], |
| [ |
| "LV_L6", |
| "HCLK_LV5" |
| ], |
| [ |
| "LV_L7", |
| "HCLK_LV6" |
| ], |
| [ |
| "LV_L8", |
| "HCLK_LV7" |
| ], |
| [ |
| "LV_L9", |
| "HCLK_LV8" |
| ], |
| [ |
| "NE2A0", |
| "HCLK_NE2BEG0" |
| ], |
| [ |
| "NE2A1", |
| "HCLK_NE2BEG1" |
| ], |
| [ |
| "NE2A2", |
| "HCLK_NE2BEG2" |
| ], |
| [ |
| "NE2A3", |
| "HCLK_NE2BEG3" |
| ], |
| [ |
| "NE2END0", |
| "HCLK_NE2END_S3_0" |
| ], |
| [ |
| "NE6B0", |
| "HCLK_NE6A0" |
| ], |
| [ |
| "NE6B1", |
| "HCLK_NE6A1" |
| ], |
| [ |
| "NE6B2", |
| "HCLK_NE6A2" |
| ], |
| [ |
| "NE6B3", |
| "HCLK_NE6A3" |
| ], |
| [ |
| "NE6C0", |
| "HCLK_NE6B0" |
| ], |
| [ |
| "NE6C1", |
| "HCLK_NE6B1" |
| ], |
| [ |
| "NE6C2", |
| "HCLK_NE6B2" |
| ], |
| [ |
| "NE6C3", |
| "HCLK_NE6B3" |
| ], |
| [ |
| "NE6D0", |
| "HCLK_NE6C0" |
| ], |
| [ |
| "NE6D1", |
| "HCLK_NE6C1" |
| ], |
| [ |
| "NE6D2", |
| "HCLK_NE6C2" |
| ], |
| [ |
| "NE6D3", |
| "HCLK_NE6C3" |
| ], |
| [ |
| "NE6E0", |
| "HCLK_NE6D0" |
| ], |
| [ |
| "NE6E1", |
| "HCLK_NE6D1" |
| ], |
| [ |
| "NE6E2", |
| "HCLK_NE6D2" |
| ], |
| [ |
| "NE6E3", |
| "HCLK_NE6D3" |
| ], |
| [ |
| "NL1END0", |
| "HCLK_NL1END_S3_0" |
| ], |
| [ |
| "NL1END1", |
| "HCLK_NL1BEG1" |
| ], |
| [ |
| "NL1END2", |
| "HCLK_NL1BEG2" |
| ], |
| [ |
| "NN2A0", |
| "HCLK_NN2BEG0" |
| ], |
| [ |
| "NN2A1", |
| "HCLK_NN2BEG1" |
| ], |
| [ |
| "NN2A2", |
| "HCLK_NN2BEG2" |
| ], |
| [ |
| "NN2A3", |
| "HCLK_NN2BEG3" |
| ], |
| [ |
| "NN2END0", |
| "HCLK_NN2END_S2_0" |
| ], |
| [ |
| "NN2END1", |
| "HCLK_NN2A1" |
| ], |
| [ |
| "NN2END2", |
| "HCLK_NN2A2" |
| ], |
| [ |
| "NN2END3", |
| "HCLK_NN2A3" |
| ], |
| [ |
| "NN6A0", |
| "HCLK_NN6BEG0" |
| ], |
| [ |
| "NN6A1", |
| "HCLK_NN6BEG1" |
| ], |
| [ |
| "NN6A2", |
| "HCLK_NN6BEG2" |
| ], |
| [ |
| "NN6A3", |
| "HCLK_NN6BEG3" |
| ], |
| [ |
| "NN6B0", |
| "HCLK_NN6A0" |
| ], |
| [ |
| "NN6B1", |
| "HCLK_NN6A1" |
| ], |
| [ |
| "NN6B2", |
| "HCLK_NN6A2" |
| ], |
| [ |
| "NN6B3", |
| "HCLK_NN6A3" |
| ], |
| [ |
| "NN6C0", |
| "HCLK_NN6B0" |
| ], |
| [ |
| "NN6C1", |
| "HCLK_NN6B1" |
| ], |
| [ |
| "NN6C2", |
| "HCLK_NN6B2" |
| ], |
| [ |
| "NN6C3", |
| "HCLK_NN6B3" |
| ], |
| [ |
| "NN6D0", |
| "HCLK_NN6C0" |
| ], |
| [ |
| "NN6D1", |
| "HCLK_NN6C1" |
| ], |
| [ |
| "NN6D2", |
| "HCLK_NN6C2" |
| ], |
| [ |
| "NN6D3", |
| "HCLK_NN6C3" |
| ], |
| [ |
| "NN6E0", |
| "HCLK_NN6D0" |
| ], |
| [ |
| "NN6E1", |
| "HCLK_NN6D1" |
| ], |
| [ |
| "NN6E2", |
| "HCLK_NN6D2" |
| ], |
| [ |
| "NN6E3", |
| "HCLK_NN6D3" |
| ], |
| [ |
| "NN6END0", |
| "HCLK_NN6END_S1_0" |
| ], |
| [ |
| "NN6END1", |
| "HCLK_NN6E1" |
| ], |
| [ |
| "NN6END2", |
| "HCLK_NN6E2" |
| ], |
| [ |
| "NN6END3", |
| "HCLK_NN6E3" |
| ], |
| [ |
| "NR1END0", |
| "HCLK_NR1BEG0" |
| ], |
| [ |
| "NR1END1", |
| "HCLK_NR1BEG1" |
| ], |
| [ |
| "NR1END2", |
| "HCLK_NR1BEG2" |
| ], |
| [ |
| "NR1END3", |
| "HCLK_NR1BEG3" |
| ], |
| [ |
| "NW2A0", |
| "HCLK_NW2A0" |
| ], |
| [ |
| "NW2A1", |
| "HCLK_NW2A1" |
| ], |
| [ |
| "NW2A2", |
| "HCLK_NW2A2" |
| ], |
| [ |
| "NW2A3", |
| "HCLK_NW2A3" |
| ], |
| [ |
| "NW2END0", |
| "HCLK_NW2END_S0_0" |
| ], |
| [ |
| "NW6B0", |
| "HCLK_NW6A0" |
| ], |
| [ |
| "NW6B1", |
| "HCLK_NW6A1" |
| ], |
| [ |
| "NW6B2", |
| "HCLK_NW6A2" |
| ], |
| [ |
| "NW6B3", |
| "HCLK_NW6A3" |
| ], |
| [ |
| "NW6C0", |
| "HCLK_NW6B0" |
| ], |
| [ |
| "NW6C1", |
| "HCLK_NW6B1" |
| ], |
| [ |
| "NW6C2", |
| "HCLK_NW6B2" |
| ], |
| [ |
| "NW6C3", |
| "HCLK_NW6B3" |
| ], |
| [ |
| "NW6D0", |
| "HCLK_NW6C0" |
| ], |
| [ |
| "NW6D1", |
| "HCLK_NW6C1" |
| ], |
| [ |
| "NW6D2", |
| "HCLK_NW6C2" |
| ], |
| [ |
| "NW6D3", |
| "HCLK_NW6C3" |
| ], |
| [ |
| "NW6E0", |
| "HCLK_NW6D0" |
| ], |
| [ |
| "NW6E1", |
| "HCLK_NW6D1" |
| ], |
| [ |
| "NW6E2", |
| "HCLK_NW6D2" |
| ], |
| [ |
| "NW6E3", |
| "HCLK_NW6D3" |
| ], |
| [ |
| "NW6END0", |
| "HCLK_NW6END_S0_0" |
| ], |
| [ |
| "SE2BEG0", |
| "HCLK_SE2A0" |
| ], |
| [ |
| "SE2BEG1", |
| "HCLK_SE2A1" |
| ], |
| [ |
| "SE2BEG2", |
| "HCLK_SE2A2" |
| ], |
| [ |
| "SE2BEG3", |
| "HCLK_SE2A3" |
| ], |
| [ |
| "SE6A0", |
| "HCLK_SE6B0" |
| ], |
| [ |
| "SE6A1", |
| "HCLK_SE6B1" |
| ], |
| [ |
| "SE6A2", |
| "HCLK_SE6B2" |
| ], |
| [ |
| "SE6A3", |
| "HCLK_SE6B3" |
| ], |
| [ |
| "SE6B0", |
| "HCLK_SE6C0" |
| ], |
| [ |
| "SE6B1", |
| "HCLK_SE6C1" |
| ], |
| [ |
| "SE6B2", |
| "HCLK_SE6C2" |
| ], |
| [ |
| "SE6B3", |
| "HCLK_SE6C3" |
| ], |
| [ |
| "SE6C0", |
| "HCLK_SE6D0" |
| ], |
| [ |
| "SE6C1", |
| "HCLK_SE6D1" |
| ], |
| [ |
| "SE6C2", |
| "HCLK_SE6D2" |
| ], |
| [ |
| "SE6C3", |
| "HCLK_SE6D3" |
| ], |
| [ |
| "SE6D0", |
| "HCLK_SE6E0" |
| ], |
| [ |
| "SE6D1", |
| "HCLK_SE6E1" |
| ], |
| [ |
| "SE6D2", |
| "HCLK_SE6E2" |
| ], |
| [ |
| "SE6D3", |
| "HCLK_SE6E3" |
| ], |
| [ |
| "SL1BEG0", |
| "HCLK_SL1END0" |
| ], |
| [ |
| "SL1BEG1", |
| "HCLK_SL1END1" |
| ], |
| [ |
| "SL1BEG2", |
| "HCLK_SL1END2" |
| ], |
| [ |
| "SL1BEG3", |
| "HCLK_SL1END3" |
| ], |
| [ |
| "SR1BEG1", |
| "HCLK_SR1END1" |
| ], |
| [ |
| "SR1BEG2", |
| "HCLK_SR1END2" |
| ], |
| [ |
| "SR1END_N3_3", |
| "HCLK_SR1END_N3_3" |
| ], |
| [ |
| "SS2A0", |
| "HCLK_SS2END0" |
| ], |
| [ |
| "SS2A1", |
| "HCLK_SS2END1" |
| ], |
| [ |
| "SS2A2", |
| "HCLK_SS2END2" |
| ], |
| [ |
| "SS2A3", |
| "HCLK_SS2END_N0_3" |
| ], |
| [ |
| "SS2BEG0", |
| "HCLK_SS2A0" |
| ], |
| [ |
| "SS2BEG1", |
| "HCLK_SS2A1" |
| ], |
| [ |
| "SS2BEG2", |
| "HCLK_SS2A2" |
| ], |
| [ |
| "SS2BEG3", |
| "HCLK_SS2BEG3" |
| ], |
| [ |
| "SS6A0", |
| "HCLK_SS6B0" |
| ], |
| [ |
| "SS6A1", |
| "HCLK_SS6B1" |
| ], |
| [ |
| "SS6A2", |
| "HCLK_SS6B2" |
| ], |
| [ |
| "SS6A3", |
| "HCLK_SS6B3" |
| ], |
| [ |
| "SS6B0", |
| "HCLK_SS6C0" |
| ], |
| [ |
| "SS6B1", |
| "HCLK_SS6C1" |
| ], |
| [ |
| "SS6B2", |
| "HCLK_SS6C2" |
| ], |
| [ |
| "SS6B3", |
| "HCLK_SS6C3" |
| ], |
| [ |
| "SS6BEG0", |
| "HCLK_SS6A0" |
| ], |
| [ |
| "SS6BEG1", |
| "HCLK_SS6A1" |
| ], |
| [ |
| "SS6BEG2", |
| "HCLK_SS6A2" |
| ], |
| [ |
| "SS6BEG3", |
| "HCLK_SS6A3" |
| ], |
| [ |
| "SS6C0", |
| "HCLK_SS6D0" |
| ], |
| [ |
| "SS6C1", |
| "HCLK_SS6D1" |
| ], |
| [ |
| "SS6C2", |
| "HCLK_SS6D2" |
| ], |
| [ |
| "SS6C3", |
| "HCLK_SS6D3" |
| ], |
| [ |
| "SS6D0", |
| "HCLK_SS6E0" |
| ], |
| [ |
| "SS6D1", |
| "HCLK_SS6E1" |
| ], |
| [ |
| "SS6D2", |
| "HCLK_SS6E2" |
| ], |
| [ |
| "SS6D3", |
| "HCLK_SS6E3" |
| ], |
| [ |
| "SS6E0", |
| "HCLK_SS6END0" |
| ], |
| [ |
| "SS6E1", |
| "HCLK_SS6END1" |
| ], |
| [ |
| "SS6E2", |
| "HCLK_SS6END2" |
| ], |
| [ |
| "SS6E3", |
| "HCLK_SS6END_N0_3" |
| ], |
| [ |
| "SW2BEG0", |
| "HCLK_SW2END0" |
| ], |
| [ |
| "SW2BEG1", |
| "HCLK_SW2END1" |
| ], |
| [ |
| "SW2BEG2", |
| "HCLK_SW2END2" |
| ], |
| [ |
| "SW2BEG3", |
| "HCLK_SW2A3" |
| ], |
| [ |
| "SW2END_N0_3", |
| "HCLK_SW2END_N0_3" |
| ], |
| [ |
| "SW6A0", |
| "HCLK_SW6B0" |
| ], |
| [ |
| "SW6A1", |
| "HCLK_SW6B1" |
| ], |
| [ |
| "SW6A2", |
| "HCLK_SW6B2" |
| ], |
| [ |
| "SW6A3", |
| "HCLK_SW6B3" |
| ], |
| [ |
| "SW6B0", |
| "HCLK_SW6C0" |
| ], |
| [ |
| "SW6B1", |
| "HCLK_SW6C1" |
| ], |
| [ |
| "SW6B2", |
| "HCLK_SW6C2" |
| ], |
| [ |
| "SW6B3", |
| "HCLK_SW6C3" |
| ], |
| [ |
| "SW6C0", |
| "HCLK_SW6D0" |
| ], |
| [ |
| "SW6C1", |
| "HCLK_SW6D1" |
| ], |
| [ |
| "SW6C2", |
| "HCLK_SW6D2" |
| ], |
| [ |
| "SW6C3", |
| "HCLK_SW6D3" |
| ], |
| [ |
| "SW6D0", |
| "HCLK_SW6E0" |
| ], |
| [ |
| "SW6D1", |
| "HCLK_SW6E1" |
| ], |
| [ |
| "SW6D2", |
| "HCLK_SW6E2" |
| ], |
| [ |
| "SW6D3", |
| "HCLK_SW6E3" |
| ], |
| [ |
| "SW6END_N0_3", |
| "HCLK_SW6END3" |
| ], |
| [ |
| "WL1BEG_N3", |
| "HCLK_WL1BEG3" |
| ], |
| [ |
| "WL1END_N1_3", |
| "HCLK_WL1END3" |
| ], |
| [ |
| "WR1BEG0", |
| "HCLK_WR1BEG_S0" |
| ], |
| [ |
| "WR1END0", |
| "HCLK_WR1END_S1_0" |
| ], |
| [ |
| "WW2END_N0_3", |
| "HCLK_WW2END3" |
| ], |
| [ |
| "WW4END0", |
| "HCLK_WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "INT_L", |
| "INT_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "BYP_BOUNCE_N3_2", |
| "BYP_BOUNCE2" |
| ], |
| [ |
| "BYP_BOUNCE_N3_3", |
| "BYP_BOUNCE3" |
| ], |
| [ |
| "BYP_BOUNCE_N3_6", |
| "BYP_BOUNCE6" |
| ], |
| [ |
| "BYP_BOUNCE_N3_7", |
| "BYP_BOUNCE7" |
| ], |
| [ |
| "EL1BEG_N3", |
| "EL1BEG3" |
| ], |
| [ |
| "EL1END0", |
| "EL1END_S3_0" |
| ], |
| [ |
| "ER1BEG0", |
| "ER1BEG_S0" |
| ], |
| [ |
| "ER1END_N3_3", |
| "ER1END3" |
| ], |
| [ |
| "FAN_BOUNCE0", |
| "FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "FAN_BOUNCE2", |
| "FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "FAN_BOUNCE4", |
| "FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "FAN_BOUNCE6", |
| "FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "GCLK_L_B10", |
| "GCLK_L_B10" |
| ], |
| [ |
| "GCLK_L_B11", |
| "GCLK_L_B11" |
| ], |
| [ |
| "GCLK_L_B6", |
| "GCLK_L_B6" |
| ], |
| [ |
| "GCLK_L_B7", |
| "GCLK_L_B7" |
| ], |
| [ |
| "GCLK_L_B8", |
| "GCLK_L_B8" |
| ], |
| [ |
| "GCLK_L_B9", |
| "GCLK_L_B9" |
| ], |
| [ |
| "NE2A0", |
| "NE2BEG0" |
| ], |
| [ |
| "NE2A1", |
| "NE2BEG1" |
| ], |
| [ |
| "NE2A2", |
| "NE2BEG2" |
| ], |
| [ |
| "NE2A3", |
| "NE2BEG3" |
| ], |
| [ |
| "NE2END0", |
| "NE2END_S3_0" |
| ], |
| [ |
| "NE6E0", |
| "NE6D0" |
| ], |
| [ |
| "NE6E1", |
| "NE6D1" |
| ], |
| [ |
| "NE6E2", |
| "NE6D2" |
| ], |
| [ |
| "NE6E3", |
| "NE6D3" |
| ], |
| [ |
| "NL1END0", |
| "NL1END_S3_0" |
| ], |
| [ |
| "NL1END1", |
| "NL1BEG1" |
| ], |
| [ |
| "NL1END2", |
| "NL1BEG2" |
| ], |
| [ |
| "NN2A0", |
| "NN2BEG0" |
| ], |
| [ |
| "NN2A1", |
| "NN2BEG1" |
| ], |
| [ |
| "NN2A2", |
| "NN2BEG2" |
| ], |
| [ |
| "NN2A3", |
| "NN2BEG3" |
| ], |
| [ |
| "NN2END0", |
| "NN2A0" |
| ], |
| [ |
| "NN2END1", |
| "NN2A1" |
| ], |
| [ |
| "NN2END2", |
| "NN2A2" |
| ], |
| [ |
| "NN2END3", |
| "NN2A3" |
| ], |
| [ |
| "NN6E0", |
| "NN6D0" |
| ], |
| [ |
| "NN6E1", |
| "NN6D1" |
| ], |
| [ |
| "NN6E2", |
| "NN6D2" |
| ], |
| [ |
| "NN6E3", |
| "NN6D3" |
| ], |
| [ |
| "NR1END0", |
| "NR1BEG0" |
| ], |
| [ |
| "NR1END1", |
| "NR1BEG1" |
| ], |
| [ |
| "NR1END2", |
| "NR1BEG2" |
| ], |
| [ |
| "NR1END3", |
| "NR1BEG3" |
| ], |
| [ |
| "NW2A0", |
| "NW2BEG0" |
| ], |
| [ |
| "NW2A1", |
| "NW2BEG1" |
| ], |
| [ |
| "NW2A2", |
| "NW2BEG2" |
| ], |
| [ |
| "NW2A3", |
| "NW2BEG3" |
| ], |
| [ |
| "NW2END0", |
| "NW2END_S0_0" |
| ], |
| [ |
| "NW6E0", |
| "NW6D0" |
| ], |
| [ |
| "NW6E1", |
| "NW6D1" |
| ], |
| [ |
| "NW6E2", |
| "NW6D2" |
| ], |
| [ |
| "NW6E3", |
| "NW6D3" |
| ], |
| [ |
| "NW6END0", |
| "NW6END_S0_0" |
| ], |
| [ |
| "SE2BEG0", |
| "SE2A0" |
| ], |
| [ |
| "SE2BEG1", |
| "SE2A1" |
| ], |
| [ |
| "SE2BEG2", |
| "SE2A2" |
| ], |
| [ |
| "SE2BEG3", |
| "SE2A3" |
| ], |
| [ |
| "SE6D0", |
| "SE6E0" |
| ], |
| [ |
| "SE6D1", |
| "SE6E1" |
| ], |
| [ |
| "SE6D2", |
| "SE6E2" |
| ], |
| [ |
| "SE6D3", |
| "SE6E3" |
| ], |
| [ |
| "SL1BEG0", |
| "SL1END0" |
| ], |
| [ |
| "SL1BEG1", |
| "SL1END1" |
| ], |
| [ |
| "SL1BEG2", |
| "SL1END2" |
| ], |
| [ |
| "SL1BEG3", |
| "SL1END3" |
| ], |
| [ |
| "SR1BEG1", |
| "SR1END1" |
| ], |
| [ |
| "SR1BEG2", |
| "SR1END2" |
| ], |
| [ |
| "SR1END_N3_3", |
| "SR1END3" |
| ], |
| [ |
| "SS2A0", |
| "SS2END0" |
| ], |
| [ |
| "SS2A1", |
| "SS2END1" |
| ], |
| [ |
| "SS2A2", |
| "SS2END2" |
| ], |
| [ |
| "SS2A3", |
| "SS2END3" |
| ], |
| [ |
| "SS2BEG0", |
| "SS2A0" |
| ], |
| [ |
| "SS2BEG1", |
| "SS2A1" |
| ], |
| [ |
| "SS2BEG2", |
| "SS2A2" |
| ], |
| [ |
| "SS2BEG3", |
| "SS2A3" |
| ], |
| [ |
| "SS6D0", |
| "SS6E0" |
| ], |
| [ |
| "SS6D1", |
| "SS6E1" |
| ], |
| [ |
| "SS6D2", |
| "SS6E2" |
| ], |
| [ |
| "SS6D3", |
| "SS6E3" |
| ], |
| [ |
| "SW2BEG0", |
| "SW2A0" |
| ], |
| [ |
| "SW2BEG1", |
| "SW2A1" |
| ], |
| [ |
| "SW2BEG2", |
| "SW2A2" |
| ], |
| [ |
| "SW2BEG3", |
| "SW2A3" |
| ], |
| [ |
| "SW2END_N0_3", |
| "SW2END3" |
| ], |
| [ |
| "SW6D0", |
| "SW6E0" |
| ], |
| [ |
| "SW6D1", |
| "SW6E1" |
| ], |
| [ |
| "SW6D2", |
| "SW6E2" |
| ], |
| [ |
| "SW6D3", |
| "SW6E3" |
| ], |
| [ |
| "SW6END_N0_3", |
| "SW6END3" |
| ], |
| [ |
| "WL1BEG_N3", |
| "WL1BEG3" |
| ], |
| [ |
| "WL1END_N1_3", |
| "WL1END3" |
| ], |
| [ |
| "WR1BEG0", |
| "WR1BEG_S0" |
| ], |
| [ |
| "WR1END0", |
| "WR1END_S1_0" |
| ], |
| [ |
| "WW2END_N0_3", |
| "WW2END3" |
| ], |
| [ |
| "WW4END0", |
| "WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "INT_L", |
| "INT_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "EE2A0", |
| "EE2END0" |
| ], |
| [ |
| "EE2A1", |
| "EE2END1" |
| ], |
| [ |
| "EE2A2", |
| "EE2END2" |
| ], |
| [ |
| "EE2A3", |
| "EE2END3" |
| ], |
| [ |
| "EE2BEG0", |
| "EE2A0" |
| ], |
| [ |
| "EE2BEG1", |
| "EE2A1" |
| ], |
| [ |
| "EE2BEG2", |
| "EE2A2" |
| ], |
| [ |
| "EE2BEG3", |
| "EE2A3" |
| ], |
| [ |
| "EE4A0", |
| "EE4B0" |
| ], |
| [ |
| "EE4A1", |
| "EE4B1" |
| ], |
| [ |
| "EE4A2", |
| "EE4B2" |
| ], |
| [ |
| "EE4A3", |
| "EE4B3" |
| ], |
| [ |
| "EE4B0", |
| "EE4C0" |
| ], |
| [ |
| "EE4B1", |
| "EE4C1" |
| ], |
| [ |
| "EE4B2", |
| "EE4C2" |
| ], |
| [ |
| "EE4B3", |
| "EE4C3" |
| ], |
| [ |
| "EE4BEG0", |
| "EE4A0" |
| ], |
| [ |
| "EE4BEG1", |
| "EE4A1" |
| ], |
| [ |
| "EE4BEG2", |
| "EE4A2" |
| ], |
| [ |
| "EE4BEG3", |
| "EE4A3" |
| ], |
| [ |
| "EE4C0", |
| "EE4END0" |
| ], |
| [ |
| "EE4C1", |
| "EE4END1" |
| ], |
| [ |
| "EE4C2", |
| "EE4END2" |
| ], |
| [ |
| "EE4C3", |
| "EE4END3" |
| ], |
| [ |
| "EL1BEG1", |
| "EL1END1" |
| ], |
| [ |
| "EL1BEG2", |
| "EL1END2" |
| ], |
| [ |
| "EL1BEG3", |
| "EL1END3" |
| ], |
| [ |
| "ER1BEG0", |
| "ER1END0" |
| ], |
| [ |
| "ER1BEG1", |
| "ER1END1" |
| ], |
| [ |
| "ER1BEG2", |
| "ER1END2" |
| ], |
| [ |
| "GCLK_L_B0", |
| "GCLK_B0_WEST" |
| ], |
| [ |
| "GCLK_L_B1", |
| "GCLK_B1_WEST" |
| ], |
| [ |
| "GCLK_L_B10_EAST", |
| "GCLK_B10" |
| ], |
| [ |
| "GCLK_L_B11_EAST", |
| "GCLK_B11" |
| ], |
| [ |
| "GCLK_L_B2", |
| "GCLK_B2_WEST" |
| ], |
| [ |
| "GCLK_L_B3", |
| "GCLK_B3_WEST" |
| ], |
| [ |
| "GCLK_L_B4", |
| "GCLK_B4_WEST" |
| ], |
| [ |
| "GCLK_L_B5", |
| "GCLK_B5_WEST" |
| ], |
| [ |
| "GCLK_L_B6_EAST", |
| "GCLK_B6" |
| ], |
| [ |
| "GCLK_L_B7_EAST", |
| "GCLK_B7" |
| ], |
| [ |
| "GCLK_L_B8_EAST", |
| "GCLK_B8" |
| ], |
| [ |
| "GCLK_L_B9_EAST", |
| "GCLK_B9" |
| ], |
| [ |
| "LH1", |
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| "NE6B1", |
| "BRKH_INT_NE6A1" |
| ], |
| [ |
| "NE6B2", |
| "BRKH_INT_NE6A2" |
| ], |
| [ |
| "NE6B3", |
| "BRKH_INT_NE6A3" |
| ], |
| [ |
| "NE6C0", |
| "BRKH_INT_NE6B0" |
| ], |
| [ |
| "NE6C1", |
| "BRKH_INT_NE6B1" |
| ], |
| [ |
| "NE6C2", |
| "BRKH_INT_NE6B2" |
| ], |
| [ |
| "NE6C3", |
| "BRKH_INT_NE6B3" |
| ], |
| [ |
| "NE6D0", |
| "BRKH_INT_NE6C0" |
| ], |
| [ |
| "NE6D1", |
| "BRKH_INT_NE6C1" |
| ], |
| [ |
| "NE6D2", |
| "BRKH_INT_NE6C2" |
| ], |
| [ |
| "NE6D3", |
| "BRKH_INT_NE6C3" |
| ], |
| [ |
| "NE6E0", |
| "BRKH_INT_NE6D0" |
| ], |
| [ |
| "NE6E1", |
| "BRKH_INT_NE6D1" |
| ], |
| [ |
| "NE6E2", |
| "BRKH_INT_NE6D2" |
| ], |
| [ |
| "NE6E3", |
| "BRKH_INT_NE6D3" |
| ], |
| [ |
| "NL1END0", |
| "BRKH_INT_NL1END_S3_0" |
| ], |
| [ |
| "NL1END1", |
| "BRKH_INT_NL1BEG1_SLOW" |
| ], |
| [ |
| "NL1END2", |
| "BRKH_INT_NL1BEG2_SLOW" |
| ], |
| [ |
| "NN2A0", |
| "BRKH_INT_NN2BEG0" |
| ], |
| [ |
| "NN2A1", |
| "BRKH_INT_NN2BEG1" |
| ], |
| [ |
| "NN2A2", |
| "BRKH_INT_NN2BEG2" |
| ], |
| [ |
| "NN2A3", |
| "BRKH_INT_NN2BEG3" |
| ], |
| [ |
| "NN2END0", |
| "BRKH_INT_NN2END_S2_0" |
| ], |
| [ |
| "NN2END1", |
| "BRKH_INT_NN2A1" |
| ], |
| [ |
| "NN2END2", |
| "BRKH_INT_NN2A2" |
| ], |
| [ |
| "NN2END3", |
| "BRKH_INT_NN2A3" |
| ], |
| [ |
| "NN6A0", |
| "BRKH_INT_NN6BEG0" |
| ], |
| [ |
| "NN6A1", |
| "BRKH_INT_NN6BEG1" |
| ], |
| [ |
| "NN6A2", |
| "BRKH_INT_NN6BEG2" |
| ], |
| [ |
| "NN6A3", |
| "BRKH_INT_NN6BEG3" |
| ], |
| [ |
| "NN6B0", |
| "BRKH_INT_NN6A0" |
| ], |
| [ |
| "NN6B1", |
| "BRKH_INT_NN6A1" |
| ], |
| [ |
| "NN6B2", |
| "BRKH_INT_NN6A2" |
| ], |
| [ |
| "NN6B3", |
| "BRKH_INT_NN6A3" |
| ], |
| [ |
| "NN6C0", |
| "BRKH_INT_NN6B0" |
| ], |
| [ |
| "NN6C1", |
| "BRKH_INT_NN6B1" |
| ], |
| [ |
| "NN6C2", |
| "BRKH_INT_NN6B2" |
| ], |
| [ |
| "NN6C3", |
| "BRKH_INT_NN6B3" |
| ], |
| [ |
| "NN6D0", |
| "BRKH_INT_NN6C0" |
| ], |
| [ |
| "NN6D1", |
| "BRKH_INT_NN6C1" |
| ], |
| [ |
| "NN6D2", |
| "BRKH_INT_NN6C2" |
| ], |
| [ |
| "NN6D3", |
| "BRKH_INT_NN6C3" |
| ], |
| [ |
| "NN6E0", |
| "BRKH_INT_NN6D0" |
| ], |
| [ |
| "NN6E1", |
| "BRKH_INT_NN6D1" |
| ], |
| [ |
| "NN6E2", |
| "BRKH_INT_NN6D2" |
| ], |
| [ |
| "NN6E3", |
| "BRKH_INT_NN6D3" |
| ], |
| [ |
| "NN6END0", |
| "BRKH_INT_NN6END_S1_0" |
| ], |
| [ |
| "NN6END1", |
| "BRKH_INT_NN6E1" |
| ], |
| [ |
| "NN6END2", |
| "BRKH_INT_NN6E2" |
| ], |
| [ |
| "NN6END3", |
| "BRKH_INT_NN6E3" |
| ], |
| [ |
| "NR1END0", |
| "BRKH_INT_NR1BEG0_SLOW" |
| ], |
| [ |
| "NR1END1", |
| "BRKH_INT_NR1BEG1_SLOW" |
| ], |
| [ |
| "NR1END2", |
| "BRKH_INT_NR1BEG2_SLOW" |
| ], |
| [ |
| "NR1END3", |
| "BRKH_INT_NR1BEG3_SLOW" |
| ], |
| [ |
| "NW2A0", |
| "BRKH_INT_NW2BEG0" |
| ], |
| [ |
| "NW2A1", |
| "BRKH_INT_NW2BEG1" |
| ], |
| [ |
| "NW2A2", |
| "BRKH_INT_NW2BEG2" |
| ], |
| [ |
| "NW2A3", |
| "BRKH_INT_NW2BEG3" |
| ], |
| [ |
| "NW2END0", |
| "BRKH_INT_NW2END_S0_0" |
| ], |
| [ |
| "NW6B0", |
| "BRKH_INT_NW6A0" |
| ], |
| [ |
| "NW6B1", |
| "BRKH_INT_NW6A1" |
| ], |
| [ |
| "NW6B2", |
| "BRKH_INT_NW6A2" |
| ], |
| [ |
| "NW6B3", |
| "BRKH_INT_NW6A3" |
| ], |
| [ |
| "NW6C0", |
| "BRKH_INT_NW6B0" |
| ], |
| [ |
| "NW6C1", |
| "BRKH_INT_NW6B1" |
| ], |
| [ |
| "NW6C2", |
| "BRKH_INT_NW6B2" |
| ], |
| [ |
| "NW6C3", |
| "BRKH_INT_NW6B3" |
| ], |
| [ |
| "NW6D0", |
| "BRKH_INT_NW6C0" |
| ], |
| [ |
| "NW6D1", |
| "BRKH_INT_NW6C1" |
| ], |
| [ |
| "NW6D2", |
| "BRKH_INT_NW6C2" |
| ], |
| [ |
| "NW6D3", |
| "BRKH_INT_NW6C3" |
| ], |
| [ |
| "NW6E0", |
| "BRKH_INT_NW6D0" |
| ], |
| [ |
| "NW6E1", |
| "BRKH_INT_NW6D1" |
| ], |
| [ |
| "NW6E2", |
| "BRKH_INT_NW6D2" |
| ], |
| [ |
| "NW6E3", |
| "BRKH_INT_NW6D3" |
| ], |
| [ |
| "NW6END0", |
| "BRKH_INT_NW6END_S0_0" |
| ], |
| [ |
| "SE2BEG0", |
| "BRKH_INT_SE2A0" |
| ], |
| [ |
| "SE2BEG1", |
| "BRKH_INT_SE2A1" |
| ], |
| [ |
| "SE2BEG2", |
| "BRKH_INT_SE2A2" |
| ], |
| [ |
| "SE2BEG3", |
| "BRKH_INT_SE2A3" |
| ], |
| [ |
| "SE6A0", |
| "BRKH_INT_SE6B0" |
| ], |
| [ |
| "SE6A1", |
| "BRKH_INT_SE6B1" |
| ], |
| [ |
| "SE6A2", |
| "BRKH_INT_SE6B2" |
| ], |
| [ |
| "SE6A3", |
| "BRKH_INT_SE6B3" |
| ], |
| [ |
| "SE6B0", |
| "BRKH_INT_SE6C0" |
| ], |
| [ |
| "SE6B1", |
| "BRKH_INT_SE6C1" |
| ], |
| [ |
| "SE6B2", |
| "BRKH_INT_SE6C2" |
| ], |
| [ |
| "SE6B3", |
| "BRKH_INT_SE6C3" |
| ], |
| [ |
| "SE6C0", |
| "BRKH_INT_SE6D0" |
| ], |
| [ |
| "SE6C1", |
| "BRKH_INT_SE6D1" |
| ], |
| [ |
| "SE6C2", |
| "BRKH_INT_SE6D2" |
| ], |
| [ |
| "SE6C3", |
| "BRKH_INT_SE6D3" |
| ], |
| [ |
| "SE6D0", |
| "BRKH_INT_SE6E0" |
| ], |
| [ |
| "SE6D1", |
| "BRKH_INT_SE6E1" |
| ], |
| [ |
| "SE6D2", |
| "BRKH_INT_SE6E2" |
| ], |
| [ |
| "SE6D3", |
| "BRKH_INT_SE6E3" |
| ], |
| [ |
| "SL1BEG0", |
| "BRKH_INT_SL1END0_SLOW" |
| ], |
| [ |
| "SL1BEG1", |
| "BRKH_INT_SL1END1_SLOW" |
| ], |
| [ |
| "SL1BEG2", |
| "BRKH_INT_SL1END2_SLOW" |
| ], |
| [ |
| "SL1BEG3", |
| "BRKH_INT_SL1END3_SLOW" |
| ], |
| [ |
| "SR1BEG1", |
| "BRKH_INT_SR1END1_SLOW" |
| ], |
| [ |
| "SR1BEG2", |
| "BRKH_INT_SR1END2_SLOW" |
| ], |
| [ |
| "SR1BEG3", |
| "BRKH_INT_SR1END3_SLOW" |
| ], |
| [ |
| "SR1END_N3_3", |
| "BRKH_INT_SR1END_N3_3" |
| ], |
| [ |
| "SS2A0", |
| "BRKH_INT_SS2END0" |
| ], |
| [ |
| "SS2A1", |
| "BRKH_INT_SS2END1" |
| ], |
| [ |
| "SS2A2", |
| "BRKH_INT_SS2END2" |
| ], |
| [ |
| "SS2A3", |
| "BRKH_INT_SS2END_N0_3" |
| ], |
| [ |
| "SS2BEG0", |
| "BRKH_INT_SS2A0" |
| ], |
| [ |
| "SS2BEG1", |
| "BRKH_INT_SS2A1" |
| ], |
| [ |
| "SS2BEG2", |
| "BRKH_INT_SS2A2" |
| ], |
| [ |
| "SS2BEG3", |
| "BRKH_INT_SS2A3" |
| ], |
| [ |
| "SS6A0", |
| "BRKH_INT_SS6B0" |
| ], |
| [ |
| "SS6A1", |
| "BRKH_INT_SS6B1" |
| ], |
| [ |
| "SS6A2", |
| "BRKH_INT_SS6B2" |
| ], |
| [ |
| "SS6A3", |
| "BRKH_INT_SS6B3" |
| ], |
| [ |
| "SS6B0", |
| "BRKH_INT_SS6C0" |
| ], |
| [ |
| "SS6B1", |
| "BRKH_INT_SS6C1" |
| ], |
| [ |
| "SS6B2", |
| "BRKH_INT_SS6C2" |
| ], |
| [ |
| "SS6B3", |
| "BRKH_INT_SS6C3" |
| ], |
| [ |
| "SS6BEG0", |
| "BRKH_INT_SS6A0" |
| ], |
| [ |
| "SS6BEG1", |
| "BRKH_INT_SS6A1" |
| ], |
| [ |
| "SS6BEG2", |
| "BRKH_INT_SS6A2" |
| ], |
| [ |
| "SS6BEG3", |
| "BRKH_INT_SS6A3" |
| ], |
| [ |
| "SS6C0", |
| "BRKH_INT_SS6D0" |
| ], |
| [ |
| "SS6C1", |
| "BRKH_INT_SS6D1" |
| ], |
| [ |
| "SS6C2", |
| "BRKH_INT_SS6D2" |
| ], |
| [ |
| "SS6C3", |
| "BRKH_INT_SS6D3" |
| ], |
| [ |
| "SS6D0", |
| "BRKH_INT_SS6E0" |
| ], |
| [ |
| "SS6D1", |
| "BRKH_INT_SS6E1" |
| ], |
| [ |
| "SS6D2", |
| "BRKH_INT_SS6E2" |
| ], |
| [ |
| "SS6D3", |
| "BRKH_INT_SS6E3" |
| ], |
| [ |
| "SS6E0", |
| "BRKH_INT_SS6END0" |
| ], |
| [ |
| "SS6E1", |
| "BRKH_INT_SS6END1" |
| ], |
| [ |
| "SS6E2", |
| "BRKH_INT_SS6END2" |
| ], |
| [ |
| "SS6E3", |
| "BRKH_INT_SS6END_N0_3" |
| ], |
| [ |
| "SW2BEG0", |
| "BRKH_INT_SW2A0" |
| ], |
| [ |
| "SW2BEG1", |
| "BRKH_INT_SW2A1" |
| ], |
| [ |
| "SW2BEG2", |
| "BRKH_INT_SW2A2" |
| ], |
| [ |
| "SW2BEG3", |
| "BRKH_INT_SW2A3" |
| ], |
| [ |
| "SW2END_N0_3", |
| "BRKH_INT_SW2END3" |
| ], |
| [ |
| "SW6A0", |
| "BRKH_INT_SW6B0" |
| ], |
| [ |
| "SW6A1", |
| "BRKH_INT_SW6B1" |
| ], |
| [ |
| "SW6A2", |
| "BRKH_INT_SW6B2" |
| ], |
| [ |
| "SW6A3", |
| "BRKH_INT_SW6B3" |
| ], |
| [ |
| "SW6B0", |
| "BRKH_INT_SW6C0" |
| ], |
| [ |
| "SW6B1", |
| "BRKH_INT_SW6C1" |
| ], |
| [ |
| "SW6B2", |
| "BRKH_INT_SW6C2" |
| ], |
| [ |
| "SW6B3", |
| "BRKH_INT_SW6C3" |
| ], |
| [ |
| "SW6C0", |
| "BRKH_INT_SW6D0" |
| ], |
| [ |
| "SW6C1", |
| "BRKH_INT_SW6D1" |
| ], |
| [ |
| "SW6C2", |
| "BRKH_INT_SW6D2" |
| ], |
| [ |
| "SW6C3", |
| "BRKH_INT_SW6D3" |
| ], |
| [ |
| "SW6D0", |
| "BRKH_INT_SW6E0" |
| ], |
| [ |
| "SW6D1", |
| "BRKH_INT_SW6E1" |
| ], |
| [ |
| "SW6D2", |
| "BRKH_INT_SW6E2" |
| ], |
| [ |
| "SW6D3", |
| "BRKH_INT_SW6E3" |
| ], |
| [ |
| "SW6END_N0_3", |
| "BRKH_INT_SW6END3" |
| ], |
| [ |
| "WL1BEG_N3", |
| "BRKH_INT_WL1BEG3" |
| ], |
| [ |
| "WL1END_N1_3", |
| "BRKH_INT_WL1END3" |
| ], |
| [ |
| "WR1BEG0", |
| "BRKH_INT_WR1BEG_S0" |
| ], |
| [ |
| "WR1END0", |
| "BRKH_INT_WR1END_S1_0" |
| ], |
| [ |
| "WW2END_N0_3", |
| "BRKH_INT_WW2END3" |
| ], |
| [ |
| "WW4END0", |
| "BRKH_INT_WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "INT_R", |
| "CLBLL_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "BYP0", |
| "CLBLL_BYP0" |
| ], |
| [ |
| "BYP1", |
| "CLBLL_BYP1" |
| ], |
| [ |
| "BYP2", |
| "CLBLL_BYP2" |
| ], |
| [ |
| "BYP3", |
| "CLBLL_BYP3" |
| ], |
| [ |
| "BYP4", |
| "CLBLL_BYP4" |
| ], |
| [ |
| "BYP5", |
| "CLBLL_BYP5" |
| ], |
| [ |
| "BYP6", |
| "CLBLL_BYP6" |
| ], |
| [ |
| "BYP7", |
| "CLBLL_BYP7" |
| ], |
| [ |
| "CLK0", |
| "CLBLL_CLK0" |
| ], |
| [ |
| "CLK1", |
| "CLBLL_CLK1" |
| ], |
| [ |
| "CTRL0", |
| "CLBLL_CTRL0" |
| ], |
| [ |
| "CTRL1", |
| "CLBLL_CTRL1" |
| ], |
| [ |
| "EE2A0", |
| "CLBLL_EE2A0" |
| ], |
| [ |
| "EE2A1", |
| "CLBLL_EE2A1" |
| ], |
| [ |
| "EE2A2", |
| "CLBLL_EE2A2" |
| ], |
| [ |
| "EE2A3", |
| "CLBLL_EE2A3" |
| ], |
| [ |
| "EE2BEG0", |
| "CLBLL_EE2BEG0" |
| ], |
| [ |
| "EE2BEG1", |
| "CLBLL_EE2BEG1" |
| ], |
| [ |
| "EE2BEG2", |
| "CLBLL_EE2BEG2" |
| ], |
| [ |
| "EE2BEG3", |
| "CLBLL_EE2BEG3" |
| ], |
| [ |
| "EE4A0", |
| "CLBLL_EE4A0" |
| ], |
| [ |
| "EE4A1", |
| "CLBLL_EE4A1" |
| ], |
| [ |
| "EE4A2", |
| "CLBLL_EE4A2" |
| ], |
| [ |
| "EE4A3", |
| "CLBLL_EE4A3" |
| ], |
| [ |
| "EE4B0", |
| "CLBLL_EE4B0" |
| ], |
| [ |
| "EE4B1", |
| "CLBLL_EE4B1" |
| ], |
| [ |
| "EE4B2", |
| "CLBLL_EE4B2" |
| ], |
| [ |
| "EE4B3", |
| "CLBLL_EE4B3" |
| ], |
| [ |
| "EE4BEG0", |
| "CLBLL_EE4BEG0" |
| ], |
| [ |
| "EE4BEG1", |
| "CLBLL_EE4BEG1" |
| ], |
| [ |
| "EE4BEG2", |
| "CLBLL_EE4BEG2" |
| ], |
| [ |
| "EE4BEG3", |
| "CLBLL_EE4BEG3" |
| ], |
| [ |
| "EE4C0", |
| "CLBLL_EE4C0" |
| ], |
| [ |
| "EE4C1", |
| "CLBLL_EE4C1" |
| ], |
| [ |
| "EE4C2", |
| "CLBLL_EE4C2" |
| ], |
| [ |
| "EE4C3", |
| "CLBLL_EE4C3" |
| ], |
| [ |
| "EL1BEG0", |
| "CLBLL_EL1BEG0" |
| ], |
| [ |
| "EL1BEG1", |
| "CLBLL_EL1BEG1" |
| ], |
| [ |
| "EL1BEG2", |
| "CLBLL_EL1BEG2" |
| ], |
| [ |
| "EL1BEG3", |
| "CLBLL_EL1BEG3" |
| ], |
| [ |
| "ER1BEG0", |
| "CLBLL_ER1BEG0" |
| ], |
| [ |
| "ER1BEG1", |
| "CLBLL_ER1BEG1" |
| ], |
| [ |
| "ER1BEG2", |
| "CLBLL_ER1BEG2" |
| ], |
| [ |
| "ER1BEG3", |
| "CLBLL_ER1BEG3" |
| ], |
| [ |
| "FAN0", |
| "CLBLL_FAN0" |
| ], |
| [ |
| "FAN1", |
| "CLBLL_FAN1" |
| ], |
| [ |
| "FAN2", |
| "CLBLL_FAN2" |
| ], |
| [ |
| "FAN3", |
| "CLBLL_FAN3" |
| ], |
| [ |
| "FAN4", |
| "CLBLL_FAN4" |
| ], |
| [ |
| "FAN5", |
| "CLBLL_FAN5" |
| ], |
| [ |
| "FAN6", |
| "CLBLL_FAN6" |
| ], |
| [ |
| "FAN7", |
| "CLBLL_FAN7" |
| ], |
| [ |
| "IMUX0", |
| "CLBLL_IMUX0" |
| ], |
| [ |
| "IMUX1", |
| "CLBLL_IMUX1" |
| ], |
| [ |
| "IMUX10", |
| "CLBLL_IMUX10" |
| ], |
| [ |
| "IMUX11", |
| "CLBLL_IMUX11" |
| ], |
| [ |
| "IMUX12", |
| "CLBLL_IMUX12" |
| ], |
| [ |
| "IMUX13", |
| "CLBLL_IMUX13" |
| ], |
| [ |
| "IMUX14", |
| "CLBLL_IMUX14" |
| ], |
| [ |
| "IMUX15", |
| "CLBLL_IMUX15" |
| ], |
| [ |
| "IMUX16", |
| "CLBLL_IMUX16" |
| ], |
| [ |
| "IMUX17", |
| "CLBLL_IMUX17" |
| ], |
| [ |
| "IMUX18", |
| "CLBLL_IMUX18" |
| ], |
| [ |
| "IMUX19", |
| "CLBLL_IMUX19" |
| ], |
| [ |
| "IMUX2", |
| "CLBLL_IMUX2" |
| ], |
| [ |
| "IMUX20", |
| "CLBLL_IMUX20" |
| ], |
| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| { |
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| 0 |
| ], |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
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| [ |
| "LH11", |
| "CLBLM_LH11" |
| ], |
| [ |
| "LH12", |
| "CLBLM_LH12" |
| ], |
| [ |
| "LH2", |
| "CLBLM_LH2" |
| ], |
| [ |
| "LH3", |
| "CLBLM_LH3" |
| ], |
| [ |
| "LH4", |
| "CLBLM_LH4" |
| ], |
| [ |
| "LH5", |
| "CLBLM_LH5" |
| ], |
| [ |
| "LH6", |
| "CLBLM_LH6" |
| ], |
| [ |
| "LH7", |
| "CLBLM_LH7" |
| ], |
| [ |
| "LH8", |
| "CLBLM_LH8" |
| ], |
| [ |
| "LH9", |
| "CLBLM_LH9" |
| ], |
| [ |
| "LOGIC_OUTS0", |
| "CLBLM_LOGIC_OUTS0" |
| ], |
| [ |
| "LOGIC_OUTS1", |
| "CLBLM_LOGIC_OUTS1" |
| ], |
| [ |
| "LOGIC_OUTS10", |
| "CLBLM_LOGIC_OUTS10" |
| ], |
| [ |
| "LOGIC_OUTS11", |
| "CLBLM_LOGIC_OUTS11" |
| ], |
| [ |
| "LOGIC_OUTS12", |
| "CLBLM_LOGIC_OUTS12" |
| ], |
| [ |
| "LOGIC_OUTS13", |
| "CLBLM_LOGIC_OUTS13" |
| ], |
| [ |
| "LOGIC_OUTS14", |
| "CLBLM_LOGIC_OUTS14" |
| ], |
| [ |
| "LOGIC_OUTS15", |
| "CLBLM_LOGIC_OUTS15" |
| ], |
| [ |
| "LOGIC_OUTS16", |
| "CLBLM_LOGIC_OUTS16" |
| ], |
| [ |
| "LOGIC_OUTS17", |
| "CLBLM_LOGIC_OUTS17" |
| ], |
| [ |
| "LOGIC_OUTS18", |
| "CLBLM_LOGIC_OUTS18" |
| ], |
| [ |
| "LOGIC_OUTS19", |
| "CLBLM_LOGIC_OUTS19" |
| ], |
| [ |
| "LOGIC_OUTS2", |
| "CLBLM_LOGIC_OUTS2" |
| ], |
| [ |
| "LOGIC_OUTS20", |
| "CLBLM_LOGIC_OUTS20" |
| ], |
| [ |
| "LOGIC_OUTS21", |
| "CLBLM_LOGIC_OUTS21" |
| ], |
| [ |
| "LOGIC_OUTS22", |
| "CLBLM_LOGIC_OUTS22" |
| ], |
| [ |
| "LOGIC_OUTS23", |
| "CLBLM_LOGIC_OUTS23" |
| ], |
| [ |
| "LOGIC_OUTS3", |
| "CLBLM_LOGIC_OUTS3" |
| ], |
| [ |
| "LOGIC_OUTS4", |
| "CLBLM_LOGIC_OUTS4" |
| ], |
| [ |
| "LOGIC_OUTS5", |
| "CLBLM_LOGIC_OUTS5" |
| ], |
| [ |
| "LOGIC_OUTS6", |
| "CLBLM_LOGIC_OUTS6" |
| ], |
| [ |
| "LOGIC_OUTS7", |
| "CLBLM_LOGIC_OUTS7" |
| ], |
| [ |
| "LOGIC_OUTS8", |
| "CLBLM_LOGIC_OUTS8" |
| ], |
| [ |
| "LOGIC_OUTS9", |
| "CLBLM_LOGIC_OUTS9" |
| ], |
| [ |
| "NE2A0", |
| "CLBLM_NE2A0" |
| ], |
| [ |
| "NE2A1", |
| "CLBLM_NE2A1" |
| ], |
| [ |
| "NE2A2", |
| "CLBLM_NE2A2" |
| ], |
| [ |
| "NE2A3", |
| "CLBLM_NE2A3" |
| ], |
| [ |
| "NE6BEG0", |
| "CLBLM_NE4BEG0" |
| ], |
| [ |
| "NE6BEG1", |
| "CLBLM_NE4BEG1" |
| ], |
| [ |
| "NE6BEG2", |
| "CLBLM_NE4BEG2" |
| ], |
| [ |
| "NE6BEG3", |
| "CLBLM_NE4BEG3" |
| ], |
| [ |
| "NE6E0", |
| "CLBLM_NE4C0" |
| ], |
| [ |
| "NE6E1", |
| "CLBLM_NE4C1" |
| ], |
| [ |
| "NE6E2", |
| "CLBLM_NE4C2" |
| ], |
| [ |
| "NE6E3", |
| "CLBLM_NE4C3" |
| ], |
| [ |
| "NW2END0", |
| "CLBLM_NW2A0" |
| ], |
| [ |
| "NW2END1", |
| "CLBLM_NW2A1" |
| ], |
| [ |
| "NW2END2", |
| "CLBLM_NW2A2" |
| ], |
| [ |
| "NW2END3", |
| "CLBLM_NW2A3" |
| ], |
| [ |
| "NW6END0", |
| "CLBLM_NW4END0" |
| ], |
| [ |
| "NW6END1", |
| "CLBLM_NW4END1" |
| ], |
| [ |
| "NW6END2", |
| "CLBLM_NW4END2" |
| ], |
| [ |
| "NW6END3", |
| "CLBLM_NW4END3" |
| ], |
| [ |
| "SE2A0", |
| "CLBLM_SE2A0" |
| ], |
| [ |
| "SE2A1", |
| "CLBLM_SE2A1" |
| ], |
| [ |
| "SE2A2", |
| "CLBLM_SE2A2" |
| ], |
| [ |
| "SE2A3", |
| "CLBLM_SE2A3" |
| ], |
| [ |
| "SE6BEG0", |
| "CLBLM_SE4BEG0" |
| ], |
| [ |
| "SE6BEG1", |
| "CLBLM_SE4BEG1" |
| ], |
| [ |
| "SE6BEG2", |
| "CLBLM_SE4BEG2" |
| ], |
| [ |
| "SE6BEG3", |
| "CLBLM_SE4BEG3" |
| ], |
| [ |
| "SE6E0", |
| "CLBLM_SE4C0" |
| ], |
| [ |
| "SE6E1", |
| "CLBLM_SE4C1" |
| ], |
| [ |
| "SE6E2", |
| "CLBLM_SE4C2" |
| ], |
| [ |
| "SE6E3", |
| "CLBLM_SE4C3" |
| ], |
| [ |
| "SW2END0", |
| "CLBLM_SW2A0" |
| ], |
| [ |
| "SW2END1", |
| "CLBLM_SW2A1" |
| ], |
| [ |
| "SW2END2", |
| "CLBLM_SW2A2" |
| ], |
| [ |
| "SW2END3", |
| "CLBLM_SW2A3" |
| ], |
| [ |
| "SW6A0", |
| "CLBLM_SW4A0" |
| ], |
| [ |
| "SW6A1", |
| "CLBLM_SW4A1" |
| ], |
| [ |
| "SW6A2", |
| "CLBLM_SW4A2" |
| ], |
| [ |
| "SW6A3", |
| "CLBLM_SW4A3" |
| ], |
| [ |
| "SW6END0", |
| "CLBLM_SW4END0" |
| ], |
| [ |
| "SW6END1", |
| "CLBLM_SW4END1" |
| ], |
| [ |
| "SW6END2", |
| "CLBLM_SW4END2" |
| ], |
| [ |
| "SW6END3", |
| "CLBLM_SW4END3" |
| ], |
| [ |
| "WL1END0", |
| "CLBLM_WL1END0" |
| ], |
| [ |
| "WL1END1", |
| "CLBLM_WL1END1" |
| ], |
| [ |
| "WL1END2", |
| "CLBLM_WL1END2" |
| ], |
| [ |
| "WR1END0", |
| "CLBLM_WR1END0" |
| ], |
| [ |
| "WR1END1", |
| "CLBLM_WR1END1" |
| ], |
| [ |
| "WR1END2", |
| "CLBLM_WR1END2" |
| ], |
| [ |
| "WR1END3", |
| "CLBLM_WR1END3" |
| ], |
| [ |
| "WW2A0", |
| "CLBLM_WW2A0" |
| ], |
| [ |
| "WW2A1", |
| "CLBLM_WW2A1" |
| ], |
| [ |
| "WW2A2", |
| "CLBLM_WW2A2" |
| ], |
| [ |
| "WW2A3", |
| "CLBLM_WW2A3" |
| ], |
| [ |
| "WW2END0", |
| "CLBLM_WW2END0" |
| ], |
| [ |
| "WW2END1", |
| "CLBLM_WW2END1" |
| ], |
| [ |
| "WW2END2", |
| "CLBLM_WW2END2" |
| ], |
| [ |
| "WW2END3", |
| "CLBLM_WW2END3" |
| ], |
| [ |
| "WW4A0", |
| "CLBLM_WW4A0" |
| ], |
| [ |
| "WW4A1", |
| "CLBLM_WW4A1" |
| ], |
| [ |
| "WW4A2", |
| "CLBLM_WW4A2" |
| ], |
| [ |
| "WW4A3", |
| "CLBLM_WW4A3" |
| ], |
| [ |
| "WW4B0", |
| "CLBLM_WW4B0" |
| ], |
| [ |
| "WW4B1", |
| "CLBLM_WW4B1" |
| ], |
| [ |
| "WW4B2", |
| "CLBLM_WW4B2" |
| ], |
| [ |
| "WW4B3", |
| "CLBLM_WW4B3" |
| ], |
| [ |
| "WW4C0", |
| "CLBLM_WW4C0" |
| ], |
| [ |
| "WW4C1", |
| "CLBLM_WW4C1" |
| ], |
| [ |
| "WW4C2", |
| "CLBLM_WW4C2" |
| ], |
| [ |
| "WW4C3", |
| "CLBLM_WW4C3" |
| ], |
| [ |
| "WW4END0", |
| "CLBLM_WW4END0" |
| ], |
| [ |
| "WW4END1", |
| "CLBLM_WW4END1" |
| ], |
| [ |
| "WW4END2", |
| "CLBLM_WW4END2" |
| ], |
| [ |
| "WW4END3", |
| "CLBLM_WW4END3" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "INT_R", |
| "HCLK_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "BYP_BOUNCE_N3_2", |
| "HCLK_BYP_BOUNCE2" |
| ], |
| [ |
| "BYP_BOUNCE_N3_3", |
| "HCLK_BYP_BOUNCE3" |
| ], |
| [ |
| "BYP_BOUNCE_N3_6", |
| "HCLK_BYP_BOUNCE6" |
| ], |
| [ |
| "BYP_BOUNCE_N3_7", |
| "HCLK_BYP_BOUNCE7" |
| ], |
| [ |
| "EL1BEG_N3", |
| "HCLK_EL1BEG3" |
| ], |
| [ |
| "EL1END0", |
| "HCLK_EL1END_S3_0" |
| ], |
| [ |
| "ER1BEG0", |
| "HCLK_ER1BEG_S0" |
| ], |
| [ |
| "ER1END_N3_3", |
| "HCLK_ER1END3" |
| ], |
| [ |
| "FAN_BOUNCE0", |
| "HCLK_FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "FAN_BOUNCE2", |
| "HCLK_FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "FAN_BOUNCE4", |
| "HCLK_FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "FAN_BOUNCE6", |
| "HCLK_FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "GCLK_B0", |
| "HCLK_LEAF_CLK_B_TOP0" |
| ], |
| [ |
| "GCLK_B1", |
| "HCLK_LEAF_CLK_B_TOP1" |
| ], |
| [ |
| "GCLK_B2", |
| "HCLK_LEAF_CLK_B_TOP2" |
| ], |
| [ |
| "GCLK_B3", |
| "HCLK_LEAF_CLK_B_TOP3" |
| ], |
| [ |
| "GCLK_B4", |
| "HCLK_LEAF_CLK_B_TOP4" |
| ], |
| [ |
| "GCLK_B5", |
| "HCLK_LEAF_CLK_B_TOP5" |
| ], |
| [ |
| "LV1", |
| "HCLK_LV0" |
| ], |
| [ |
| "LV10", |
| "HCLK_LV9" |
| ], |
| [ |
| "LV11", |
| "HCLK_LV10" |
| ], |
| [ |
| "LV12", |
| "HCLK_LV11" |
| ], |
| [ |
| "LV13", |
| "HCLK_LV12" |
| ], |
| [ |
| "LV14", |
| "HCLK_LV13" |
| ], |
| [ |
| "LV15", |
| "HCLK_LV14" |
| ], |
| [ |
| "LV16", |
| "HCLK_LV15" |
| ], |
| [ |
| "LV17", |
| "HCLK_LV16" |
| ], |
| [ |
| "LV18", |
| "HCLK_LV17" |
| ], |
| [ |
| "LV2", |
| "HCLK_LV1" |
| ], |
| [ |
| "LV3", |
| "HCLK_LV2" |
| ], |
| [ |
| "LV4", |
| "HCLK_LV3" |
| ], |
| [ |
| "LV5", |
| "HCLK_LV4" |
| ], |
| [ |
| "LV6", |
| "HCLK_LV5" |
| ], |
| [ |
| "LV7", |
| "HCLK_LV6" |
| ], |
| [ |
| "LV8", |
| "HCLK_LV7" |
| ], |
| [ |
| "LV9", |
| "HCLK_LV8" |
| ], |
| [ |
| "LVB1", |
| "HCLK_LVB1" |
| ], |
| [ |
| "LVB10", |
| "HCLK_LVB10" |
| ], |
| [ |
| "LVB11", |
| "HCLK_LVB11" |
| ], |
| [ |
| "LVB12", |
| "HCLK_LVB12" |
| ], |
| [ |
| "LVB2", |
| "HCLK_LVB2" |
| ], |
| [ |
| "LVB3", |
| "HCLK_LVB3" |
| ], |
| [ |
| "LVB4", |
| "HCLK_LVB4" |
| ], |
| [ |
| "LVB5", |
| "HCLK_LVB5" |
| ], |
| [ |
| "LVB6", |
| "HCLK_LVB6" |
| ], |
| [ |
| "LVB7", |
| "HCLK_LVB7" |
| ], |
| [ |
| "LVB8", |
| "HCLK_LVB8" |
| ], |
| [ |
| "LVB9", |
| "HCLK_LVB9" |
| ], |
| [ |
| "NE2A0", |
| "HCLK_NE2BEG0" |
| ], |
| [ |
| "NE2A1", |
| "HCLK_NE2BEG1" |
| ], |
| [ |
| "NE2A2", |
| "HCLK_NE2BEG2" |
| ], |
| [ |
| "NE2A3", |
| "HCLK_NE2BEG3" |
| ], |
| [ |
| "NE2END0", |
| "HCLK_NE2END_S3_0" |
| ], |
| [ |
| "NE6B0", |
| "HCLK_NE6A0" |
| ], |
| [ |
| "NE6B1", |
| "HCLK_NE6A1" |
| ], |
| [ |
| "NE6B2", |
| "HCLK_NE6A2" |
| ], |
| [ |
| "NE6B3", |
| "HCLK_NE6A3" |
| ], |
| [ |
| "NE6C0", |
| "HCLK_NE6B0" |
| ], |
| [ |
| "NE6C1", |
| "HCLK_NE6B1" |
| ], |
| [ |
| "NE6C2", |
| "HCLK_NE6B2" |
| ], |
| [ |
| "NE6C3", |
| "HCLK_NE6B3" |
| ], |
| [ |
| "NE6D0", |
| "HCLK_NE6C0" |
| ], |
| [ |
| "NE6D1", |
| "HCLK_NE6C1" |
| ], |
| [ |
| "NE6D2", |
| "HCLK_NE6C2" |
| ], |
| [ |
| "NE6D3", |
| "HCLK_NE6C3" |
| ], |
| [ |
| "NE6E0", |
| "HCLK_NE6D0" |
| ], |
| [ |
| "NE6E1", |
| "HCLK_NE6D1" |
| ], |
| [ |
| "NE6E2", |
| "HCLK_NE6D2" |
| ], |
| [ |
| "NE6E3", |
| "HCLK_NE6D3" |
| ], |
| [ |
| "NL1END0", |
| "HCLK_NL1END_S3_0" |
| ], |
| [ |
| "NL1END1", |
| "HCLK_NL1BEG1" |
| ], |
| [ |
| "NL1END2", |
| "HCLK_NL1BEG2" |
| ], |
| [ |
| "NN2A0", |
| "HCLK_NN2BEG0" |
| ], |
| [ |
| "NN2A1", |
| "HCLK_NN2BEG1" |
| ], |
| [ |
| "NN2A2", |
| "HCLK_NN2BEG2" |
| ], |
| [ |
| "NN2A3", |
| "HCLK_NN2BEG3" |
| ], |
| [ |
| "NN2END0", |
| "HCLK_NN2END_S2_0" |
| ], |
| [ |
| "NN2END1", |
| "HCLK_NN2A1" |
| ], |
| [ |
| "NN2END2", |
| "HCLK_NN2A2" |
| ], |
| [ |
| "NN2END3", |
| "HCLK_NN2A3" |
| ], |
| [ |
| "NN6A0", |
| "HCLK_NN6BEG0" |
| ], |
| [ |
| "NN6A1", |
| "HCLK_NN6BEG1" |
| ], |
| [ |
| "NN6A2", |
| "HCLK_NN6BEG2" |
| ], |
| [ |
| "NN6A3", |
| "HCLK_NN6BEG3" |
| ], |
| [ |
| "NN6B0", |
| "HCLK_NN6A0" |
| ], |
| [ |
| "NN6B1", |
| "HCLK_NN6A1" |
| ], |
| [ |
| "NN6B2", |
| "HCLK_NN6A2" |
| ], |
| [ |
| "NN6B3", |
| "HCLK_NN6A3" |
| ], |
| [ |
| "NN6C0", |
| "HCLK_NN6B0" |
| ], |
| [ |
| "NN6C1", |
| "HCLK_NN6B1" |
| ], |
| [ |
| "NN6C2", |
| "HCLK_NN6B2" |
| ], |
| [ |
| "NN6C3", |
| "HCLK_NN6B3" |
| ], |
| [ |
| "NN6D0", |
| "HCLK_NN6C0" |
| ], |
| [ |
| "NN6D1", |
| "HCLK_NN6C1" |
| ], |
| [ |
| "NN6D2", |
| "HCLK_NN6C2" |
| ], |
| [ |
| "NN6D3", |
| "HCLK_NN6C3" |
| ], |
| [ |
| "NN6E0", |
| "HCLK_NN6D0" |
| ], |
| [ |
| "NN6E1", |
| "HCLK_NN6D1" |
| ], |
| [ |
| "NN6E2", |
| "HCLK_NN6D2" |
| ], |
| [ |
| "NN6E3", |
| "HCLK_NN6D3" |
| ], |
| [ |
| "NN6END0", |
| "HCLK_NN6END_S1_0" |
| ], |
| [ |
| "NN6END1", |
| "HCLK_NN6E1" |
| ], |
| [ |
| "NN6END2", |
| "HCLK_NN6E2" |
| ], |
| [ |
| "NN6END3", |
| "HCLK_NN6E3" |
| ], |
| [ |
| "NR1END0", |
| "HCLK_NR1BEG0" |
| ], |
| [ |
| "NR1END1", |
| "HCLK_NR1BEG1" |
| ], |
| [ |
| "NR1END2", |
| "HCLK_NR1BEG2" |
| ], |
| [ |
| "NR1END3", |
| "HCLK_NR1BEG3" |
| ], |
| [ |
| "NW2A0", |
| "HCLK_NW2A0" |
| ], |
| [ |
| "NW2A1", |
| "HCLK_NW2A1" |
| ], |
| [ |
| "NW2A2", |
| "HCLK_NW2A2" |
| ], |
| [ |
| "NW2A3", |
| "HCLK_NW2A3" |
| ], |
| [ |
| "NW2END0", |
| "HCLK_NW2END_S0_0" |
| ], |
| [ |
| "NW6B0", |
| "HCLK_NW6A0" |
| ], |
| [ |
| "NW6B1", |
| "HCLK_NW6A1" |
| ], |
| [ |
| "NW6B2", |
| "HCLK_NW6A2" |
| ], |
| [ |
| "NW6B3", |
| "HCLK_NW6A3" |
| ], |
| [ |
| "NW6C0", |
| "HCLK_NW6B0" |
| ], |
| [ |
| "NW6C1", |
| "HCLK_NW6B1" |
| ], |
| [ |
| "NW6C2", |
| "HCLK_NW6B2" |
| ], |
| [ |
| "NW6C3", |
| "HCLK_NW6B3" |
| ], |
| [ |
| "NW6D0", |
| "HCLK_NW6C0" |
| ], |
| [ |
| "NW6D1", |
| "HCLK_NW6C1" |
| ], |
| [ |
| "NW6D2", |
| "HCLK_NW6C2" |
| ], |
| [ |
| "NW6D3", |
| "HCLK_NW6C3" |
| ], |
| [ |
| "NW6E0", |
| "HCLK_NW6D0" |
| ], |
| [ |
| "NW6E1", |
| "HCLK_NW6D1" |
| ], |
| [ |
| "NW6E2", |
| "HCLK_NW6D2" |
| ], |
| [ |
| "NW6E3", |
| "HCLK_NW6D3" |
| ], |
| [ |
| "NW6END0", |
| "HCLK_NW6END_S0_0" |
| ], |
| [ |
| "SE2BEG0", |
| "HCLK_SE2A0" |
| ], |
| [ |
| "SE2BEG1", |
| "HCLK_SE2A1" |
| ], |
| [ |
| "SE2BEG2", |
| "HCLK_SE2A2" |
| ], |
| [ |
| "SE2BEG3", |
| "HCLK_SE2A3" |
| ], |
| [ |
| "SE6A0", |
| "HCLK_SE6B0" |
| ], |
| [ |
| "SE6A1", |
| "HCLK_SE6B1" |
| ], |
| [ |
| "SE6A2", |
| "HCLK_SE6B2" |
| ], |
| [ |
| "SE6A3", |
| "HCLK_SE6B3" |
| ], |
| [ |
| "SE6B0", |
| "HCLK_SE6C0" |
| ], |
| [ |
| "SE6B1", |
| "HCLK_SE6C1" |
| ], |
| [ |
| "SE6B2", |
| "HCLK_SE6C2" |
| ], |
| [ |
| "SE6B3", |
| "HCLK_SE6C3" |
| ], |
| [ |
| "SE6C0", |
| "HCLK_SE6D0" |
| ], |
| [ |
| "SE6C1", |
| "HCLK_SE6D1" |
| ], |
| [ |
| "SE6C2", |
| "HCLK_SE6D2" |
| ], |
| [ |
| "SE6C3", |
| "HCLK_SE6D3" |
| ], |
| [ |
| "SE6D0", |
| "HCLK_SE6E0" |
| ], |
| [ |
| "SE6D1", |
| "HCLK_SE6E1" |
| ], |
| [ |
| "SE6D2", |
| "HCLK_SE6E2" |
| ], |
| [ |
| "SE6D3", |
| "HCLK_SE6E3" |
| ], |
| [ |
| "SL1BEG0", |
| "HCLK_SL1END0" |
| ], |
| [ |
| "SL1BEG1", |
| "HCLK_SL1END1" |
| ], |
| [ |
| "SL1BEG2", |
| "HCLK_SL1END2" |
| ], |
| [ |
| "SL1BEG3", |
| "HCLK_SL1END3" |
| ], |
| [ |
| "SR1BEG1", |
| "HCLK_SR1END1" |
| ], |
| [ |
| "SR1BEG2", |
| "HCLK_SR1END2" |
| ], |
| [ |
| "SR1END_N3_3", |
| "HCLK_SR1END_N3_3" |
| ], |
| [ |
| "SS2A0", |
| "HCLK_SS2END0" |
| ], |
| [ |
| "SS2A1", |
| "HCLK_SS2END1" |
| ], |
| [ |
| "SS2A2", |
| "HCLK_SS2END2" |
| ], |
| [ |
| "SS2A3", |
| "HCLK_SS2END_N0_3" |
| ], |
| [ |
| "SS2BEG0", |
| "HCLK_SS2A0" |
| ], |
| [ |
| "SS2BEG1", |
| "HCLK_SS2A1" |
| ], |
| [ |
| "SS2BEG2", |
| "HCLK_SS2A2" |
| ], |
| [ |
| "SS2BEG3", |
| "HCLK_SS2BEG3" |
| ], |
| [ |
| "SS6A0", |
| "HCLK_SS6B0" |
| ], |
| [ |
| "SS6A1", |
| "HCLK_SS6B1" |
| ], |
| [ |
| "SS6A2", |
| "HCLK_SS6B2" |
| ], |
| [ |
| "SS6A3", |
| "HCLK_SS6B3" |
| ], |
| [ |
| "SS6B0", |
| "HCLK_SS6C0" |
| ], |
| [ |
| "SS6B1", |
| "HCLK_SS6C1" |
| ], |
| [ |
| "SS6B2", |
| "HCLK_SS6C2" |
| ], |
| [ |
| "SS6B3", |
| "HCLK_SS6C3" |
| ], |
| [ |
| "SS6BEG0", |
| "HCLK_SS6A0" |
| ], |
| [ |
| "SS6BEG1", |
| "HCLK_SS6A1" |
| ], |
| [ |
| "SS6BEG2", |
| "HCLK_SS6A2" |
| ], |
| [ |
| "SS6BEG3", |
| "HCLK_SS6A3" |
| ], |
| [ |
| "SS6C0", |
| "HCLK_SS6D0" |
| ], |
| [ |
| "SS6C1", |
| "HCLK_SS6D1" |
| ], |
| [ |
| "SS6C2", |
| "HCLK_SS6D2" |
| ], |
| [ |
| "SS6C3", |
| "HCLK_SS6D3" |
| ], |
| [ |
| "SS6D0", |
| "HCLK_SS6E0" |
| ], |
| [ |
| "SS6D1", |
| "HCLK_SS6E1" |
| ], |
| [ |
| "SS6D2", |
| "HCLK_SS6E2" |
| ], |
| [ |
| "SS6D3", |
| "HCLK_SS6E3" |
| ], |
| [ |
| "SS6E0", |
| "HCLK_SS6END0" |
| ], |
| [ |
| "SS6E1", |
| "HCLK_SS6END1" |
| ], |
| [ |
| "SS6E2", |
| "HCLK_SS6END2" |
| ], |
| [ |
| "SS6E3", |
| "HCLK_SS6END_N0_3" |
| ], |
| [ |
| "SW2BEG0", |
| "HCLK_SW2END0" |
| ], |
| [ |
| "SW2BEG1", |
| "HCLK_SW2END1" |
| ], |
| [ |
| "SW2BEG2", |
| "HCLK_SW2END2" |
| ], |
| [ |
| "SW2BEG3", |
| "HCLK_SW2A3" |
| ], |
| [ |
| "SW2END_N0_3", |
| "HCLK_SW2END_N0_3" |
| ], |
| [ |
| "SW6A0", |
| "HCLK_SW6B0" |
| ], |
| [ |
| "SW6A1", |
| "HCLK_SW6B1" |
| ], |
| [ |
| "SW6A2", |
| "HCLK_SW6B2" |
| ], |
| [ |
| "SW6A3", |
| "HCLK_SW6B3" |
| ], |
| [ |
| "SW6B0", |
| "HCLK_SW6C0" |
| ], |
| [ |
| "SW6B1", |
| "HCLK_SW6C1" |
| ], |
| [ |
| "SW6B2", |
| "HCLK_SW6C2" |
| ], |
| [ |
| "SW6B3", |
| "HCLK_SW6C3" |
| ], |
| [ |
| "SW6C0", |
| "HCLK_SW6D0" |
| ], |
| [ |
| "SW6C1", |
| "HCLK_SW6D1" |
| ], |
| [ |
| "SW6C2", |
| "HCLK_SW6D2" |
| ], |
| [ |
| "SW6C3", |
| "HCLK_SW6D3" |
| ], |
| [ |
| "SW6D0", |
| "HCLK_SW6E0" |
| ], |
| [ |
| "SW6D1", |
| "HCLK_SW6E1" |
| ], |
| [ |
| "SW6D2", |
| "HCLK_SW6E2" |
| ], |
| [ |
| "SW6D3", |
| "HCLK_SW6E3" |
| ], |
| [ |
| "SW6END_N0_3", |
| "HCLK_SW6END3" |
| ], |
| [ |
| "WL1BEG_N3", |
| "HCLK_WL1BEG3" |
| ], |
| [ |
| "WL1END_N1_3", |
| "HCLK_WL1END3" |
| ], |
| [ |
| "WR1BEG0", |
| "HCLK_WR1BEG_S0" |
| ], |
| [ |
| "WR1END0", |
| "HCLK_WR1END_S1_0" |
| ], |
| [ |
| "WW2END_N0_3", |
| "HCLK_WW2END3" |
| ], |
| [ |
| "WW4END0", |
| "HCLK_WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "INT_R", |
| "INT_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "BYP_BOUNCE_N3_2", |
| "BYP_BOUNCE2" |
| ], |
| [ |
| "BYP_BOUNCE_N3_3", |
| "BYP_BOUNCE3" |
| ], |
| [ |
| "BYP_BOUNCE_N3_6", |
| "BYP_BOUNCE6" |
| ], |
| [ |
| "BYP_BOUNCE_N3_7", |
| "BYP_BOUNCE7" |
| ], |
| [ |
| "EL1BEG_N3", |
| "EL1BEG3" |
| ], |
| [ |
| "EL1END0", |
| "EL1END_S3_0" |
| ], |
| [ |
| "ER1BEG0", |
| "ER1BEG_S0" |
| ], |
| [ |
| "ER1END_N3_3", |
| "ER1END3" |
| ], |
| [ |
| "FAN_BOUNCE0", |
| "FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "FAN_BOUNCE2", |
| "FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "FAN_BOUNCE4", |
| "FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "FAN_BOUNCE6", |
| "FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "GCLK_B0", |
| "GCLK_B0" |
| ], |
| [ |
| "GCLK_B1", |
| "GCLK_B1" |
| ], |
| [ |
| "GCLK_B2", |
| "GCLK_B2" |
| ], |
| [ |
| "GCLK_B3", |
| "GCLK_B3" |
| ], |
| [ |
| "GCLK_B4", |
| "GCLK_B4" |
| ], |
| [ |
| "GCLK_B5", |
| "GCLK_B5" |
| ], |
| [ |
| "NE2A0", |
| "NE2BEG0" |
| ], |
| [ |
| "NE2A1", |
| "NE2BEG1" |
| ], |
| [ |
| "NE2A2", |
| "NE2BEG2" |
| ], |
| [ |
| "NE2A3", |
| "NE2BEG3" |
| ], |
| [ |
| "NE2END0", |
| "NE2END_S3_0" |
| ], |
| [ |
| "NE6E0", |
| "NE6D0" |
| ], |
| [ |
| "NE6E1", |
| "NE6D1" |
| ], |
| [ |
| "NE6E2", |
| "NE6D2" |
| ], |
| [ |
| "NE6E3", |
| "NE6D3" |
| ], |
| [ |
| "NL1END0", |
| "NL1END_S3_0" |
| ], |
| [ |
| "NL1END1", |
| "NL1BEG1" |
| ], |
| [ |
| "NL1END2", |
| "NL1BEG2" |
| ], |
| [ |
| "NN2A0", |
| "NN2BEG0" |
| ], |
| [ |
| "NN2A1", |
| "NN2BEG1" |
| ], |
| [ |
| "NN2A2", |
| "NN2BEG2" |
| ], |
| [ |
| "NN2A3", |
| "NN2BEG3" |
| ], |
| [ |
| "NN2END0", |
| "NN2A0" |
| ], |
| [ |
| "NN2END1", |
| "NN2A1" |
| ], |
| [ |
| "NN2END2", |
| "NN2A2" |
| ], |
| [ |
| "NN2END3", |
| "NN2A3" |
| ], |
| [ |
| "NN6E0", |
| "NN6D0" |
| ], |
| [ |
| "NN6E1", |
| "NN6D1" |
| ], |
| [ |
| "NN6E2", |
| "NN6D2" |
| ], |
| [ |
| "NN6E3", |
| "NN6D3" |
| ], |
| [ |
| "NR1END0", |
| "NR1BEG0" |
| ], |
| [ |
| "NR1END1", |
| "NR1BEG1" |
| ], |
| [ |
| "NR1END2", |
| "NR1BEG2" |
| ], |
| [ |
| "NR1END3", |
| "NR1BEG3" |
| ], |
| [ |
| "NW2A0", |
| "NW2BEG0" |
| ], |
| [ |
| "NW2A1", |
| "NW2BEG1" |
| ], |
| [ |
| "NW2A2", |
| "NW2BEG2" |
| ], |
| [ |
| "NW2A3", |
| "NW2BEG3" |
| ], |
| [ |
| "NW2END0", |
| "NW2END_S0_0" |
| ], |
| [ |
| "NW6E0", |
| "NW6D0" |
| ], |
| [ |
| "NW6E1", |
| "NW6D1" |
| ], |
| [ |
| "NW6E2", |
| "NW6D2" |
| ], |
| [ |
| "NW6E3", |
| "NW6D3" |
| ], |
| [ |
| "NW6END0", |
| "NW6END_S0_0" |
| ], |
| [ |
| "SE2BEG0", |
| "SE2A0" |
| ], |
| [ |
| "SE2BEG1", |
| "SE2A1" |
| ], |
| [ |
| "SE2BEG2", |
| "SE2A2" |
| ], |
| [ |
| "SE2BEG3", |
| "SE2A3" |
| ], |
| [ |
| "SE6D0", |
| "SE6E0" |
| ], |
| [ |
| "SE6D1", |
| "SE6E1" |
| ], |
| [ |
| "SE6D2", |
| "SE6E2" |
| ], |
| [ |
| "SE6D3", |
| "SE6E3" |
| ], |
| [ |
| "SL1BEG0", |
| "SL1END0" |
| ], |
| [ |
| "SL1BEG1", |
| "SL1END1" |
| ], |
| [ |
| "SL1BEG2", |
| "SL1END2" |
| ], |
| [ |
| "SL1BEG3", |
| "SL1END3" |
| ], |
| [ |
| "SR1BEG1", |
| "SR1END1" |
| ], |
| [ |
| "SR1BEG2", |
| "SR1END2" |
| ], |
| [ |
| "SR1END_N3_3", |
| "SR1END3" |
| ], |
| [ |
| "SS2A0", |
| "SS2END0" |
| ], |
| [ |
| "SS2A1", |
| "SS2END1" |
| ], |
| [ |
| "SS2A2", |
| "SS2END2" |
| ], |
| [ |
| "SS2A3", |
| "SS2END3" |
| ], |
| [ |
| "SS2BEG0", |
| "SS2A0" |
| ], |
| [ |
| "SS2BEG1", |
| "SS2A1" |
| ], |
| [ |
| "SS2BEG2", |
| "SS2A2" |
| ], |
| [ |
| "SS2BEG3", |
| "SS2A3" |
| ], |
| [ |
| "SS6D0", |
| "SS6E0" |
| ], |
| [ |
| "SS6D1", |
| "SS6E1" |
| ], |
| [ |
| "SS6D2", |
| "SS6E2" |
| ], |
| [ |
| "SS6D3", |
| "SS6E3" |
| ], |
| [ |
| "SW2BEG0", |
| "SW2A0" |
| ], |
| [ |
| "SW2BEG1", |
| "SW2A1" |
| ], |
| [ |
| "SW2BEG2", |
| "SW2A2" |
| ], |
| [ |
| "SW2BEG3", |
| "SW2A3" |
| ], |
| [ |
| "SW2END_N0_3", |
| "SW2END3" |
| ], |
| [ |
| "SW6D0", |
| "SW6E0" |
| ], |
| [ |
| "SW6D1", |
| "SW6E1" |
| ], |
| [ |
| "SW6D2", |
| "SW6E2" |
| ], |
| [ |
| "SW6D3", |
| "SW6E3" |
| ], |
| [ |
| "SW6END_N0_3", |
| "SW6END3" |
| ], |
| [ |
| "WL1BEG_N3", |
| "WL1BEG3" |
| ], |
| [ |
| "WL1END_N1_3", |
| "WL1END3" |
| ], |
| [ |
| "WR1BEG0", |
| "WR1BEG_S0" |
| ], |
| [ |
| "WR1END0", |
| "WR1END_S1_0" |
| ], |
| [ |
| "WW2END_N0_3", |
| "WW2END3" |
| ], |
| [ |
| "WW4END0", |
| "WW4END_S0_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "T_TERM_INT", |
| "INT_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "T_TERM_UTURN_INT_ER1BEG_S0", |
| "EL1BEG3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_ER1END3", |
| "EL1END_S3_0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", |
| "FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", |
| "FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", |
| "FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", |
| "FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB_L0", |
| "LVB_L11" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB_L1", |
| "LVB_L10" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB_L2", |
| "LVB_L9" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB_L3", |
| "LVB_L8" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB_L4", |
| "LVB_L7" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB_L5", |
| "LVB_L6" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L16", |
| "LV_L16" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L17", |
| "LV_L17" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L2", |
| "LV_L15" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L3", |
| "LV_L14" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L4", |
| "LV_L13" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L5", |
| "LV_L12" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L6", |
| "LV_L11" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L7", |
| "LV_L10" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LV_L9", |
| "LV_L8" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A0", |
| "SE2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A1", |
| "SE2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A2", |
| "SE2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A3", |
| "SE2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B0", |
| "SE6B0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B1", |
| "SE6B1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B2", |
| "SE6B2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B3", |
| "SE6B3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C0", |
| "SE6C0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C1", |
| "SE6C1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C2", |
| "SE6C2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C3", |
| "SE6C3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D0", |
| "SE6D0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D1", |
| "SE6D1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D2", |
| "SE6D2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D3", |
| "SE6D3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E0", |
| "SE6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E1", |
| "SE6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E2", |
| "SE6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E3", |
| "SE6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END0", |
| "SL1END0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END1", |
| "SL1END1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END2", |
| "SL1END2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END3", |
| "SL1END3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SR1END1", |
| "SR1END1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SR1END2", |
| "SR1END2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SR1END3", |
| "SR1END3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A0", |
| "SS2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A1", |
| "SS2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A2", |
| "SS2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A3", |
| "SS2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END0", |
| "NN2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END1", |
| "NN2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END2", |
| "NN2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END3", |
| "NN2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A0", |
| "SS6A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A1", |
| "SS6A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A2", |
| "SS6A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A3", |
| "SS6A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B0", |
| "SS6B0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B1", |
| "SS6B1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B2", |
| "SS6B2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B3", |
| "SS6B3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C0", |
| "SS6C0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C1", |
| "SS6C1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C2", |
| "SS6C2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C3", |
| "SS6C3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D0", |
| "SS6D0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D1", |
| "SS6D1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D2", |
| "SS6D2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D3", |
| "SS6D3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E0", |
| "SS6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E1", |
| "SS6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E2", |
| "SS6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E3", |
| "SS6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END0", |
| "NN6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END1", |
| "NN6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END2", |
| "NN6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END3", |
| "NN6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A0", |
| "SW2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A1", |
| "SW2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A2", |
| "SW2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A3", |
| "SW2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B0", |
| "SW6B0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B1", |
| "SW6B1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B2", |
| "SW6B2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B3", |
| "SW6B3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C0", |
| "SW6C0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C1", |
| "SW6C1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C2", |
| "SW6C2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C3", |
| "SW6C3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D0", |
| "SW6D0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D1", |
| "SW6D1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D2", |
| "SW6D2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D3", |
| "SW6D3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E0", |
| "SW6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E1", |
| "SW6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E2", |
| "SW6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E3", |
| "SW6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_WR1BEG_S0", |
| "WL1BEG3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_WR1END_S1_0", |
| "WR1END_S1_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 0, |
| 1 |
| ], |
| "tile_types": [ |
| "T_TERM_INT", |
| "INT_R" |
| ], |
| "wire_pairs": [ |
| [ |
| "T_TERM_INT_UTURN_LV_R16", |
| "LV16" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R17", |
| "LV17" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R2", |
| "LV15" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R3", |
| "LV14" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R4", |
| "LV13" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R5", |
| "LV12" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R6", |
| "LV11" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R7", |
| "LV10" |
| ], |
| [ |
| "T_TERM_INT_UTURN_LV_R9", |
| "LV8" |
| ], |
| [ |
| "T_TERM_UTURN_INT_ER1BEG_S0", |
| "EL1BEG3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_ER1END3", |
| "EL1END_S3_0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_0", |
| "FAN_BOUNCE_S3_0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_2", |
| "FAN_BOUNCE_S3_2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_4", |
| "FAN_BOUNCE_S3_4" |
| ], |
| [ |
| "T_TERM_UTURN_INT_FAN_BOUNCE_S3_6", |
| "FAN_BOUNCE_S3_6" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB0", |
| "LVB11" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB1", |
| "LVB10" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB2", |
| "LVB9" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB3", |
| "LVB8" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB4", |
| "LVB7" |
| ], |
| [ |
| "T_TERM_UTURN_INT_LVB5", |
| "LVB6" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A0", |
| "SE2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A1", |
| "SE2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A2", |
| "SE2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE2A3", |
| "SE2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B0", |
| "SE6B0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B1", |
| "SE6B1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B2", |
| "SE6B2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6B3", |
| "SE6B3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C0", |
| "SE6C0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C1", |
| "SE6C1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C2", |
| "SE6C2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6C3", |
| "SE6C3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D0", |
| "SE6D0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D1", |
| "SE6D1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D2", |
| "SE6D2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6D3", |
| "SE6D3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E0", |
| "SE6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E1", |
| "SE6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E2", |
| "SE6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SE6E3", |
| "SE6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END0", |
| "SL1END0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END1", |
| "SL1END1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END2", |
| "SL1END2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SL1END3", |
| "SL1END3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SR1END1", |
| "SR1END1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SR1END2", |
| "SR1END2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SR1END3", |
| "SR1END3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A0", |
| "SS2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A1", |
| "SS2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A2", |
| "SS2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2A3", |
| "SS2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END0", |
| "NN2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END1", |
| "NN2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END2", |
| "NN2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS2END3", |
| "NN2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A0", |
| "SS6A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A1", |
| "SS6A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A2", |
| "SS6A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6A3", |
| "SS6A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B0", |
| "SS6B0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B1", |
| "SS6B1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B2", |
| "SS6B2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6B3", |
| "SS6B3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C0", |
| "SS6C0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C1", |
| "SS6C1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C2", |
| "SS6C2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6C3", |
| "SS6C3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D0", |
| "SS6D0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D1", |
| "SS6D1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D2", |
| "SS6D2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6D3", |
| "SS6D3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E0", |
| "SS6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E1", |
| "SS6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E2", |
| "SS6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6E3", |
| "SS6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END0", |
| "NN6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END1", |
| "NN6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END2", |
| "NN6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SS6END3", |
| "NN6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A0", |
| "SW2A0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A1", |
| "SW2A1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A2", |
| "SW2A2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW2A3", |
| "SW2A3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B0", |
| "SW6B0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B1", |
| "SW6B1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B2", |
| "SW6B2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6B3", |
| "SW6B3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C0", |
| "SW6C0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C1", |
| "SW6C1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C2", |
| "SW6C2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6C3", |
| "SW6C3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D0", |
| "SW6D0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D1", |
| "SW6D1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D2", |
| "SW6D2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6D3", |
| "SW6D3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E0", |
| "SW6E0" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E1", |
| "SW6E1" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E2", |
| "SW6E2" |
| ], |
| [ |
| "T_TERM_UTURN_INT_SW6E3", |
| "SW6E3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_WR1BEG_S0", |
| "WL1BEG3" |
| ], |
| [ |
| "T_TERM_UTURN_INT_WR1END_S1_0", |
| "WR1END_S1_0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "T_TERM_INT", |
| "T_TERM_INT" |
| ], |
| "wire_pairs": [ |
| [ |
| "T_TERM_UTURN_INT_WR1END_S1_0", |
| "T_TERM_UTURN_INT_WR1BEG_S0" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "VBRK", |
| "CLBLL_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "VBRK_EE2A0", |
| "CLBLL_EE2A0" |
| ], |
| [ |
| "VBRK_EE2A1", |
| "CLBLL_EE2A1" |
| ], |
| [ |
| "VBRK_EE2A2", |
| "CLBLL_EE2A2" |
| ], |
| [ |
| "VBRK_EE2A3", |
| "CLBLL_EE2A3" |
| ], |
| [ |
| "VBRK_EE2BEG0", |
| "CLBLL_EE2BEG0" |
| ], |
| [ |
| "VBRK_EE2BEG1", |
| "CLBLL_EE2BEG1" |
| ], |
| [ |
| "VBRK_EE2BEG2", |
| "CLBLL_EE2BEG2" |
| ], |
| [ |
| "VBRK_EE2BEG3", |
| "CLBLL_EE2BEG3" |
| ], |
| [ |
| "VBRK_EE4A0", |
| "CLBLL_EE4A0" |
| ], |
| [ |
| "VBRK_EE4A1", |
| "CLBLL_EE4A1" |
| ], |
| [ |
| "VBRK_EE4A2", |
| "CLBLL_EE4A2" |
| ], |
| [ |
| "VBRK_EE4A3", |
| "CLBLL_EE4A3" |
| ], |
| [ |
| "VBRK_EE4B0", |
| "CLBLL_EE4B0" |
| ], |
| [ |
| "VBRK_EE4B1", |
| "CLBLL_EE4B1" |
| ], |
| [ |
| "VBRK_EE4B2", |
| "CLBLL_EE4B2" |
| ], |
| [ |
| "VBRK_EE4B3", |
| "CLBLL_EE4B3" |
| ], |
| [ |
| "VBRK_EE4BEG0", |
| "CLBLL_EE4BEG0" |
| ], |
| [ |
| "VBRK_EE4BEG1", |
| "CLBLL_EE4BEG1" |
| ], |
| [ |
| "VBRK_EE4BEG2", |
| "CLBLL_EE4BEG2" |
| ], |
| [ |
| "VBRK_EE4BEG3", |
| "CLBLL_EE4BEG3" |
| ], |
| [ |
| "VBRK_EE4C0", |
| "CLBLL_EE4C0" |
| ], |
| [ |
| "VBRK_EE4C1", |
| "CLBLL_EE4C1" |
| ], |
| [ |
| "VBRK_EE4C2", |
| "CLBLL_EE4C2" |
| ], |
| [ |
| "VBRK_EE4C3", |
| "CLBLL_EE4C3" |
| ], |
| [ |
| "VBRK_EL1BEG0", |
| "CLBLL_EL1BEG0" |
| ], |
| [ |
| "VBRK_EL1BEG1", |
| "CLBLL_EL1BEG1" |
| ], |
| [ |
| "VBRK_EL1BEG2", |
| "CLBLL_EL1BEG2" |
| ], |
| [ |
| "VBRK_EL1BEG3", |
| "CLBLL_EL1BEG3" |
| ], |
| [ |
| "VBRK_ER1BEG0", |
| "CLBLL_ER1BEG0" |
| ], |
| [ |
| "VBRK_ER1BEG1", |
| "CLBLL_ER1BEG1" |
| ], |
| [ |
| "VBRK_ER1BEG2", |
| "CLBLL_ER1BEG2" |
| ], |
| [ |
| "VBRK_ER1BEG3", |
| "CLBLL_ER1BEG3" |
| ], |
| [ |
| "VBRK_LH1", |
| "CLBLL_LH1" |
| ], |
| [ |
| "VBRK_LH10", |
| "CLBLL_LH10" |
| ], |
| [ |
| "VBRK_LH11", |
| "CLBLL_LH11" |
| ], |
| [ |
| "VBRK_LH12", |
| "CLBLL_LH12" |
| ], |
| [ |
| "VBRK_LH2", |
| "CLBLL_LH2" |
| ], |
| [ |
| "VBRK_LH3", |
| "CLBLL_LH3" |
| ], |
| [ |
| "VBRK_LH4", |
| "CLBLL_LH4" |
| ], |
| [ |
| "VBRK_LH5", |
| "CLBLL_LH5" |
| ], |
| [ |
| "VBRK_LH6", |
| "CLBLL_LH6" |
| ], |
| [ |
| "VBRK_LH7", |
| "CLBLL_LH7" |
| ], |
| [ |
| "VBRK_LH8", |
| "CLBLL_LH8" |
| ], |
| [ |
| "VBRK_LH9", |
| "CLBLL_LH9" |
| ], |
| [ |
| "VBRK_NE2A0", |
| "CLBLL_NE2A0" |
| ], |
| [ |
| "VBRK_NE2A1", |
| "CLBLL_NE2A1" |
| ], |
| [ |
| "VBRK_NE2A2", |
| "CLBLL_NE2A2" |
| ], |
| [ |
| "VBRK_NE2A3", |
| "CLBLL_NE2A3" |
| ], |
| [ |
| "VBRK_NE4BEG0", |
| "CLBLL_NE4BEG0" |
| ], |
| [ |
| "VBRK_NE4BEG1", |
| "CLBLL_NE4BEG1" |
| ], |
| [ |
| "VBRK_NE4BEG2", |
| "CLBLL_NE4BEG2" |
| ], |
| [ |
| "VBRK_NE4BEG3", |
| "CLBLL_NE4BEG3" |
| ], |
| [ |
| "VBRK_NE4C0", |
| "CLBLL_NE4C0" |
| ], |
| [ |
| "VBRK_NE4C1", |
| "CLBLL_NE4C1" |
| ], |
| [ |
| "VBRK_NE4C2", |
| "CLBLL_NE4C2" |
| ], |
| [ |
| "VBRK_NE4C3", |
| "CLBLL_NE4C3" |
| ], |
| [ |
| "VBRK_NW2A0", |
| "CLBLL_NW2A0" |
| ], |
| [ |
| "VBRK_NW2A1", |
| "CLBLL_NW2A1" |
| ], |
| [ |
| "VBRK_NW2A2", |
| "CLBLL_NW2A2" |
| ], |
| [ |
| "VBRK_NW2A3", |
| "CLBLL_NW2A3" |
| ], |
| [ |
| "VBRK_NW4A0", |
| "CLBLL_NW4A0" |
| ], |
| [ |
| "VBRK_NW4A1", |
| "CLBLL_NW4A1" |
| ], |
| [ |
| "VBRK_NW4A2", |
| "CLBLL_NW4A2" |
| ], |
| [ |
| "VBRK_NW4A3", |
| "CLBLL_NW4A3" |
| ], |
| [ |
| "VBRK_NW4END0", |
| "CLBLL_NW4END0" |
| ], |
| [ |
| "VBRK_NW4END1", |
| "CLBLL_NW4END1" |
| ], |
| [ |
| "VBRK_NW4END2", |
| "CLBLL_NW4END2" |
| ], |
| [ |
| "VBRK_NW4END3", |
| "CLBLL_NW4END3" |
| ], |
| [ |
| "VBRK_SE2A0", |
| "CLBLL_SE2A0" |
| ], |
| [ |
| "VBRK_SE2A1", |
| "CLBLL_SE2A1" |
| ], |
| [ |
| "VBRK_SE2A2", |
| "CLBLL_SE2A2" |
| ], |
| [ |
| "VBRK_SE2A3", |
| "CLBLL_SE2A3" |
| ], |
| [ |
| "VBRK_SE4BEG0", |
| "CLBLL_SE4BEG0" |
| ], |
| [ |
| "VBRK_SE4BEG1", |
| "CLBLL_SE4BEG1" |
| ], |
| [ |
| "VBRK_SE4BEG2", |
| "CLBLL_SE4BEG2" |
| ], |
| [ |
| "VBRK_SE4BEG3", |
| "CLBLL_SE4BEG3" |
| ], |
| [ |
| "VBRK_SE4C0", |
| "CLBLL_SE4C0" |
| ], |
| [ |
| "VBRK_SE4C1", |
| "CLBLL_SE4C1" |
| ], |
| [ |
| "VBRK_SE4C2", |
| "CLBLL_SE4C2" |
| ], |
| [ |
| "VBRK_SE4C3", |
| "CLBLL_SE4C3" |
| ], |
| [ |
| "VBRK_SW2A0", |
| "CLBLL_SW2A0" |
| ], |
| [ |
| "VBRK_SW2A1", |
| "CLBLL_SW2A1" |
| ], |
| [ |
| "VBRK_SW2A2", |
| "CLBLL_SW2A2" |
| ], |
| [ |
| "VBRK_SW2A3", |
| "CLBLL_SW2A3" |
| ], |
| [ |
| "VBRK_SW4A0", |
| "CLBLL_SW4A0" |
| ], |
| [ |
| "VBRK_SW4A1", |
| "CLBLL_SW4A1" |
| ], |
| [ |
| "VBRK_SW4A2", |
| "CLBLL_SW4A2" |
| ], |
| [ |
| "VBRK_SW4A3", |
| "CLBLL_SW4A3" |
| ], |
| [ |
| "VBRK_SW4END0", |
| "CLBLL_SW4END0" |
| ], |
| [ |
| "VBRK_SW4END1", |
| "CLBLL_SW4END1" |
| ], |
| [ |
| "VBRK_SW4END2", |
| "CLBLL_SW4END2" |
| ], |
| [ |
| "VBRK_SW4END3", |
| "CLBLL_SW4END3" |
| ], |
| [ |
| "VBRK_WL1END0", |
| "CLBLL_WL1END0" |
| ], |
| [ |
| "VBRK_WL1END1", |
| "CLBLL_WL1END1" |
| ], |
| [ |
| "VBRK_WL1END2", |
| "CLBLL_WL1END2" |
| ], |
| [ |
| "VBRK_WL1END3", |
| "CLBLL_WL1END3" |
| ], |
| [ |
| "VBRK_WR1END0", |
| "CLBLL_WR1END0" |
| ], |
| [ |
| "VBRK_WR1END1", |
| "CLBLL_WR1END1" |
| ], |
| [ |
| "VBRK_WR1END2", |
| "CLBLL_WR1END2" |
| ], |
| [ |
| "VBRK_WR1END3", |
| "CLBLL_WR1END3" |
| ], |
| [ |
| "VBRK_WW2A0", |
| "CLBLL_WW2A0" |
| ], |
| [ |
| "VBRK_WW2A1", |
| "CLBLL_WW2A1" |
| ], |
| [ |
| "VBRK_WW2A2", |
| "CLBLL_WW2A2" |
| ], |
| [ |
| "VBRK_WW2A3", |
| "CLBLL_WW2A3" |
| ], |
| [ |
| "VBRK_WW2END0", |
| "CLBLL_WW2END0" |
| ], |
| [ |
| "VBRK_WW2END1", |
| "CLBLL_WW2END1" |
| ], |
| [ |
| "VBRK_WW2END2", |
| "CLBLL_WW2END2" |
| ], |
| [ |
| "VBRK_WW2END3", |
| "CLBLL_WW2END3" |
| ], |
| [ |
| "VBRK_WW4A0", |
| "CLBLL_WW4A0" |
| ], |
| [ |
| "VBRK_WW4A1", |
| "CLBLL_WW4A1" |
| ], |
| [ |
| "VBRK_WW4A2", |
| "CLBLL_WW4A2" |
| ], |
| [ |
| "VBRK_WW4A3", |
| "CLBLL_WW4A3" |
| ], |
| [ |
| "VBRK_WW4B0", |
| "CLBLL_WW4B0" |
| ], |
| [ |
| "VBRK_WW4B1", |
| "CLBLL_WW4B1" |
| ], |
| [ |
| "VBRK_WW4B2", |
| "CLBLL_WW4B2" |
| ], |
| [ |
| "VBRK_WW4B3", |
| "CLBLL_WW4B3" |
| ], |
| [ |
| "VBRK_WW4C0", |
| "CLBLL_WW4C0" |
| ], |
| [ |
| "VBRK_WW4C1", |
| "CLBLL_WW4C1" |
| ], |
| [ |
| "VBRK_WW4C2", |
| "CLBLL_WW4C2" |
| ], |
| [ |
| "VBRK_WW4C3", |
| "CLBLL_WW4C3" |
| ], |
| [ |
| "VBRK_WW4END0", |
| "CLBLL_WW4END0" |
| ], |
| [ |
| "VBRK_WW4END1", |
| "CLBLL_WW4END1" |
| ], |
| [ |
| "VBRK_WW4END2", |
| "CLBLL_WW4END2" |
| ], |
| [ |
| "VBRK_WW4END3", |
| "CLBLL_WW4END3" |
| ] |
| ] |
| }, |
| { |
| "grid_deltas": [ |
| 1, |
| 0 |
| ], |
| "tile_types": [ |
| "VBRK", |
| "CLBLM_L" |
| ], |
| "wire_pairs": [ |
| [ |
| "VBRK_EE2A0", |
| "CLBLM_EE2A0" |
| ], |
| [ |
| "VBRK_EE2A1", |
| "CLBLM_EE2A1" |
| ], |
| [ |
| "VBRK_EE2A2", |
| "CLBLM_EE2A2" |
| ], |
| [ |
| "VBRK_EE2A3", |
| "CLBLM_EE2A3" |
| ], |
| [ |
| "VBRK_EE2BEG0", |
| "CLBLM_EE2BEG0" |
| ], |
| [ |
| "VBRK_EE2BEG1", |
| "CLBLM_EE2BEG1" |
| ], |
| [ |
| "VBRK_EE2BEG2", |
| "CLBLM_EE2BEG2" |
| ], |
| [ |
| "VBRK_EE2BEG3", |
| "CLBLM_EE2BEG3" |
| ], |
| [ |
| "VBRK_EE4A0", |
| "CLBLM_EE4A0" |
| ], |
| [ |
| "VBRK_EE4A1", |
| "CLBLM_EE4A1" |
| ], |
| [ |
| "VBRK_EE4A2", |
| "CLBLM_EE4A2" |
| ], |
| [ |
| "VBRK_EE4A3", |
| "CLBLM_EE4A3" |
| ], |
| [ |
| "VBRK_EE4B0", |
| "CLBLM_EE4B0" |
| ], |
| [ |
| "VBRK_EE4B1", |
| "CLBLM_EE4B1" |
| ], |
| [ |
| "VBRK_EE4B2", |
| "CLBLM_EE4B2" |
| ], |
| [ |
| "VBRK_EE4B3", |
| "CLBLM_EE4B3" |
| ], |
| [ |
| "VBRK_EE4BEG0", |
| "CLBLM_EE4BEG0" |
| ], |
| [ |
| "VBRK_EE4BEG1", |
| "CLBLM_EE4BEG1" |
| ], |
| [ |
| "VBRK_EE4BEG2", |
| "CLBLM_EE4BEG2" |
| ], |
| [ |
| "VBRK_EE4BEG3", |
| "CLBLM_EE4BEG3" |
| ], |
| [ |
| "VBRK_EE4C0", |
| "CLBLM_EE4C0" |
| ], |
| [ |
| "VBRK_EE4C1", |
| "CLBLM_EE4C1" |
| ], |
| [ |
| "VBRK_EE4C2", |
| "CLBLM_EE4C2" |
| ], |
| [ |
| "VBRK_EE4C3", |
| "CLBLM_EE4C3" |
| ], |
| [ |
| "VBRK_EL1BEG0", |
| "CLBLM_EL1BEG0" |
| ], |
| [ |
| "VBRK_EL1BEG1", |
| "CLBLM_EL1BEG1" |
| ], |
| [ |
| "VBRK_EL1BEG2", |
| "CLBLM_EL1BEG2" |
| ], |
| [ |
| "VBRK_EL1BEG3", |
| "CLBLM_EL1BEG3" |
| ], |
| [ |
| "VBRK_ER1BEG0", |
| "CLBLM_ER1BEG0" |
| ], |
| [ |
| "VBRK_ER1BEG1", |
| "CLBLM_ER1BEG1" |
| ], |
| [ |
| "VBRK_ER1BEG2", |
| "CLBLM_ER1BEG2" |
| ], |
| [ |
| "VBRK_ER1BEG3", |
| "CLBLM_ER1BEG3" |
| ], |
| [ |
| "VBRK_LH1", |
| "CLBLM_LH1" |
| ], |
| [ |
| "VBRK_LH10", |
| "CLBLM_LH10" |
| ], |
| [ |
| "VBRK_LH11", |
| "CLBLM_LH11" |
| ], |
| [ |
| "VBRK_LH12", |
| "CLBLM_LH12" |
| ], |
| [ |
| "VBRK_LH2", |
| "CLBLM_LH2" |
| ], |
| [ |
| "VBRK_LH3", |
| "CLBLM_LH3" |
| ], |
| [ |
| "VBRK_LH4", |
| "CLBLM_LH4" |
| ], |
| [ |
| "VBRK_LH5", |
| "CLBLM_LH5" |
| ], |
| [ |
| "VBRK_LH6", |
| "CLBLM_LH6" |
| ], |
| [ |
| "VBRK_LH7", |
| "CLBLM_LH7" |
| ], |
| [ |
| "VBRK_LH8", |
| "CLBLM_LH8" |
| ], |
| [ |
| "VBRK_LH9", |
| "CLBLM_LH9" |
| ], |
| [ |
| "VBRK_NE2A0", |
| "CLBLM_NE2A0" |
| ], |
| [ |
| "VBRK_NE2A1", |
| "CLBLM_NE2A1" |
| ], |
| [ |
| "VBRK_NE2A2", |
| "CLBLM_NE2A2" |
| ], |
| [ |
| "VBRK_NE2A3", |
| "CLBLM_NE2A3" |
| ], |
| [ |
| "VBRK_NE4BEG0", |
| "CLBLM_NE4BEG0" |
| ], |
| [ |
| "VBRK_NE4BEG1", |
| "CLBLM_NE4BEG1" |
| ], |
| [ |
| "VBRK_NE4BEG2", |
| "CLBLM_NE4BEG2" |
| ], |
| [ |
| "VBRK_NE4BEG3", |
| "CLBLM_NE4BEG3" |
| ], |
| [ |
| "VBRK_NE4C0", |
| "CLBLM_NE4C0" |
| ], |
| [ |
| "VBRK_NE4C1", |
| "CLBLM_NE4C1" |
| ], |
| [ |
| "VBRK_NE4C2", |
| "CLBLM_NE4C2" |
| ], |
| [ |
| "VBRK_NE4C3", |
| "CLBLM_NE4C3" |
| ], |
| [ |
| "VBRK_NW2A0", |
| "CLBLM_NW2A0" |
| ], |
| [ |
| "VBRK_NW2A1", |
| "CLBLM_NW2A1" |
| ], |
| [ |
| "VBRK_NW2A2", |
| "CLBLM_NW2A2" |
| ], |
| [ |
| "VBRK_NW2A3", |
| "CLBLM_NW2A3" |
| ], |
| [ |
| "VBRK_NW4A0", |
| "CLBLM_NW4A0" |
| ], |
| [ |
| "VBRK_NW4A1", |
| "CLBLM_NW4A1" |
| ], |
| [ |
| "VBRK_NW4A2", |
| "CLBLM_NW4A2" |
| ], |
| [ |
| "VBRK_NW4A3", |
| "CLBLM_NW4A3" |
| ], |
| [ |
| "VBRK_NW4END0", |
| "CLBLM_NW4END0" |
| ], |
| [ |
| "VBRK_NW4END1", |
| "CLBLM_NW4END1" |
| ], |
| [ |
| "VBRK_NW4END2", |
| "CLBLM_NW4END2" |
| ], |
| [ |
| "VBRK_NW4END3", |
| "CLBLM_NW4END3" |
| ], |
| [ |
| "VBRK_SE2A0", |
| "CLBLM_SE2A0" |
| ], |
| [ |
| "VBRK_SE2A1", |
| "CLBLM_SE2A1" |
| ], |
| [ |
| "VBRK_SE2A2", |
| "CLBLM_SE2A2" |
| ], |
| [ |
| "VBRK_SE2A3", |
| "CLBLM_SE2A3" |
| ], |
| [ |
| "VBRK_SE4BEG0", |
| "CLBLM_SE4BEG0" |
| ], |
| [ |
| "VBRK_SE4BEG1", |
| "CLBLM_SE4BEG1" |
| ], |
| [ |
| "VBRK_SE4BEG2", |
| "CLBLM_SE4BEG2" |
| ], |
| [ |
| "VBRK_SE4BEG3", |
| "CLBLM_SE4BEG3" |
| ], |
| [ |
| "VBRK_SE4C0", |
| "CLBLM_SE4C0" |
| ], |
| [ |
| "VBRK_SE4C1", |
| "CLBLM_SE4C1" |
| ], |
| [ |
| "VBRK_SE4C2", |
| "CLBLM_SE4C2" |
| ], |
| [ |
| "VBRK_SE4C3", |
| "CLBLM_SE4C3" |
| ], |
| [ |
| "VBRK_SW2A0", |
| "CLBLM_SW2A0" |
| ], |
| [ |
| "VBRK_SW2A1", |
| "CLBLM_SW2A1" |
| ], |
| [ |
| "VBRK_SW2A2", |
| "CLBLM_SW2A2" |
| ], |
| [ |
| "VBRK_SW2A3", |
| "CLBLM_SW2A3" |
| ], |
| [ |
| "VBRK_SW4A0", |
| "CLBLM_SW4A0" |
| ], |
| [ |
| "VBRK_SW4A1", |
| "CLBLM_SW4A1" |
| ], |
| [ |
| "VBRK_SW4A2", |
| "CLBLM_SW4A2" |
| ], |
| [ |
| "VBRK_SW4A3", |
| "CLBLM_SW4A3" |
| ], |
| [ |
| "VBRK_SW4END0", |
| "CLBLM_SW4END0" |
| ], |
| [ |
| "VBRK_SW4END1", |
| "CLBLM_SW4END1" |
| ], |
| [ |
| "VBRK_SW4END2", |
| "CLBLM_SW4END2" |
| ], |
| [ |
| "VBRK_SW4END3", |
| "CLBLM_SW4END3" |
| ], |
| [ |
| "VBRK_WL1END0", |
| "CLBLM_WL1END0" |
| ], |
| [ |
| "VBRK_WL1END1", |
| "CLBLM_WL1END1" |
| ], |
| [ |
| "VBRK_WL1END2", |
| "CLBLM_WL1END2" |
| ], |
| [ |
| "VBRK_WL1END3", |
| "CLBLM_WL1END3" |
| ], |
| [ |
| "VBRK_WR1END0", |
| "CLBLM_WR1END0" |
| ], |
| [ |
| "VBRK_WR1END1", |
| "CLBLM_WR1END1" |
| ], |
| [ |
| "VBRK_WR1END2", |
| "CLBLM_WR1END2" |
| ], |
| [ |
| "VBRK_WR1END3", |
| "CLBLM_WR1END3" |
| ], |
| [ |
| "VBRK_WW2A0", |
| "CLBLM_WW2A0" |
| ], |
| [ |
| "VBRK_WW2A1", |
| "CLBLM_WW2A1" |
| ], |
| [ |
| "VBRK_WW2A2", |
| "CLBLM_WW2A2" |
| ], |
| [ |
| "VBRK_WW2A3", |
| "CLBLM_WW2A3" |
| ], |
| [ |
| "VBRK_WW2END0", |
| "CLBLM_WW2END0" |
| ], |
| [ |
| "VBRK_WW2END1", |
| "CLBLM_WW2END1" |
| ], |
| [ |
| "VBRK_WW2END2", |
| "CLBLM_WW2END2" |
| ], |
| [ |
| "VBRK_WW2END3", |
| "CLBLM_WW2END3" |
| ], |
| [ |
| "VBRK_WW4A0", |
| "CLBLM_WW4A0" |
| ], |
| [ |
| "VBRK_WW4A1", |
| "CLBLM_WW4A1" |
| ], |
| [ |
| "VBRK_WW4A2", |
| "CLBLM_WW4A2" |
| ], |
| [ |
| "VBRK_WW4A3", |
| "CLBLM_WW4A3" |
| ], |
| [ |
| "VBRK_WW4B0", |
| "CLBLM_WW4B0" |
| ], |
| [ |
| "VBRK_WW4B1", |
| "CLBLM_WW4B1" |
| ], |
| [ |
| "VBRK_WW4B2", |
| "CLBLM_WW4B2" |
| ], |
| [ |
| "VBRK_WW4B3", |
| "CLBLM_WW4B3" |
| ], |
| [ |
| "VBRK_WW4C0", |
| "CLBLM_WW4C0" |
| ], |
| [ |
| "VBRK_WW4C1", |
| "CLBLM_WW4C1" |
| ], |
| [ |
| "VBRK_WW4C2", |
| "CLBLM_WW4C2" |
| ], |
| [ |
| "VBRK_WW4C3", |
| "CLBLM_WW4C3" |
| ], |
| [ |
| "VBRK_WW4END0", |
| "CLBLM_WW4END0" |
| ], |
| [ |
| "VBRK_WW4END1", |
| "CLBLM_WW4END1" |
| ], |
| [ |
| "VBRK_WW4END2", |
| "CLBLM_WW4END2" |
| ], |
| [ |
| "VBRK_WW4END3", |
| "CLBLM_WW4END3" |
| ] |
| ] |
| } |
| ] |
