|  |  | 
|  | (DELAYFILE | 
|  | (SDFVERSION "3.0") | 
|  | (TIMESCALE 1ns) | 
|  |  | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_MEM_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_FREQ_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_MEM_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_OUTPUT_CLK_SRC_PHASE_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK DQSFOUND (0.204::0.217)(0.379::0.402)) | 
|  | (IOPATH RST DQSOUTOFRANGE (0.094::0.100)(0.186::0.198)) | 
|  | (IOPATH RST PHASELOCKED (0.094::0.100)(0.186::0.198)) | 
|  | (IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198)) | 
|  | (IOPATH SYSCLK COUNTERREADVAL (0.132::0.140)(0.255::0.271)) | 
|  | (IOPATH SYSCLK FINEOVERFLOW (0.344::0.365)(0.667::0.708)) | 
|  | (IOPATH SYSCLK STG1OVERFLOW (0.230::0.244)(0.431::0.458)) | 
|  | (IOPATH SYSCLK STG1REGR (0.222::0.236)(0.459::0.487)) | 
|  | ) | 
|  | ) | 
|  | (TIMINGCHECK | 
|  | (HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP BURSTPENDING (posedge SYSCLK) (0.040::0.042)) | 
|  | (HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053)) | 
|  | (SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105)) | 
|  | (HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP COUNTERLOADVAL (posedge SYSCLK) (0.067::0.071)) | 
|  | (HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053)) | 
|  | (SETUP COUNTERREADEN (posedge SYSCLK) (0.095::0.101)) | 
|  | (HOLD DIVIDERST (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP DIVIDERST (posedge SYSCLK) (0.091::0.097)) | 
|  | (HOLD EDGEADV (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP EDGEADV (posedge SYSCLK) (0.028::0.030)) | 
|  | (HOLD ENCALIB (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP ENCALIB (posedge SYSCLK) (0.217::0.230)) | 
|  | (HOLD ENSTG1 (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP ENSTG1 (posedge SYSCLK) (0.170::0.180)) | 
|  | (HOLD ENSTG1ADJUSTB (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP ENSTG1ADJUSTB (posedge SYSCLK) (0.227::0.241)) | 
|  | (HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053)) | 
|  | (SETUP FINEENABLE (posedge SYSCLK) (0.072::0.076)) | 
|  | (HOLD FINEINC (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP FINEINC (posedge SYSCLK) (0.057::0.061)) | 
|  | (HOLD RANKSEL (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP RANKSEL (posedge SYSCLK) (0.228::0.242)) | 
|  | (HOLD RSTDQSFIND (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP RSTDQSFIND (posedge SYSCLK) (0.156::0.166)) | 
|  | (HOLD SCANENB (posedge SCANCLK) (0.000::0.000)) | 
|  | (SETUP SCANENB (posedge SCANCLK) (0.212::0.225)) | 
|  | (HOLD SCANIN (posedge SCANCLK) (0.000::0.000)) | 
|  | (SETUP SCANIN (posedge SCANCLK) (0.030::0.032)) | 
|  | (HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000)) | 
|  | (SETUP SCANMODEB (posedge SCANCLK) (0.526::0.559)) | 
|  | (HOLD SELCALORSTG1 (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP SELCALORSTG1 (posedge SYSCLK) (0.046::0.049)) | 
|  | (HOLD STG1INCDEC (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP STG1INCDEC (posedge SYSCLK) (0.227::0.241)) | 
|  | (HOLD STG1LOAD (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP STG1LOAD (posedge SYSCLK) (0.218::0.232)) | 
|  | (HOLD STG1READ (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP STG1READ (posedge SYSCLK) (0.154::0.164)) | 
|  | (HOLD STG1REGL (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP STG1REGL (posedge SYSCLK) (0.218::0.231)) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_MEM_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK ISERDESRST (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK WRENABLE (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK ISERDESRST (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK WRENABLE (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH FREQREFCLK ISERDESRST (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH FREQREFCLK WRENABLE (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_FREQ_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH FREQREFCLK ICLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH FREQREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH FREQREFCLK RCLK (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_MEM_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK ICLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK RCLK (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_IN_PHY_PHASER_IN_PHYPHASER_IN_PHY_OUTPUT_CLK_SRC_PHASE_REF") | 
|  | (INSTANCE PHASER_IN_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK ICLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK ICLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK RCLK (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_FREQ_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_OUTPUT_CLK_SRC_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH SCANCLK SCANOUT (0.094::0.100)(0.186::0.198)) | 
|  | (IOPATH SYSCLK COARSEOVERFLOW (0.143::0.152)(0.274::0.291)) | 
|  | (IOPATH SYSCLK COUNTERREADVAL (0.123::0.131)(0.251::0.267)) | 
|  | (IOPATH SYSCLK FINEOVERFLOW (0.182::0.193)(0.337::0.358)) | 
|  | ) | 
|  | ) | 
|  | (TIMINGCHECK | 
|  | (HOLD BURSTPENDING (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP BURSTPENDING (posedge SYSCLK) (0.126::0.134)) | 
|  | (HOLD COARSEENABLE (posedge SYSCLK) (0.050::0.053)) | 
|  | (SETUP COARSEENABLE (posedge SYSCLK) (0.114::0.121)) | 
|  | (HOLD COARSEINC (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP COARSEINC (posedge SYSCLK) (0.133::0.141)) | 
|  | (HOLD COUNTERLOADEN (posedge SYSCLK) (0.050::0.053)) | 
|  | (SETUP COUNTERLOADEN (posedge SYSCLK) (0.099::0.105)) | 
|  | (HOLD COUNTERLOADVAL (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP COUNTERLOADVAL (posedge SYSCLK) (0.168::0.178)) | 
|  | (HOLD COUNTERREADEN (posedge SYSCLK) (0.050::0.053)) | 
|  | (SETUP COUNTERREADEN (posedge SYSCLK) (0.073::0.077)) | 
|  | (HOLD EDGEADV (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP EDGEADV (posedge SYSCLK) (0.027::0.029)) | 
|  | (HOLD ENCALIB (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP ENCALIB (posedge SYSCLK) (0.176::0.187)) | 
|  | (HOLD FINEENABLE (posedge SYSCLK) (0.050::0.053)) | 
|  | (SETUP FINEENABLE (posedge SYSCLK) (0.169::0.179)) | 
|  | (HOLD FINEINC (posedge SYSCLK) (0.000::0.000)) | 
|  | (SETUP FINEINC (posedge SYSCLK) (0.050::0.053)) | 
|  | (HOLD SCANENB (posedge SCANCLK) (0.000::0.000)) | 
|  | (SETUP SCANENB (posedge SCANCLK) (0.488::0.518)) | 
|  | (HOLD SCANIN (posedge SCANCLK) (0.000::0.000)) | 
|  | (SETUP SCANIN (posedge SCANCLK) (0.194::0.206)) | 
|  | (HOLD SCANMODEB (posedge SCANCLK) (0.000::0.000)) | 
|  | (SETUP SCANMODEB (posedge SCANCLK) (0.966::1.026)) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_FALSE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_FALSE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OCLKDELAY_INV_TRUE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLKDELAYED (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK CTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK DQSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK DTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK OSERDESRST (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK RDENABLE (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_COARSE_BYPASS_TRUE_OUTPUT_CLK_SRC_DELAYED_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK CTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK DQSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK DTSBUS (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK OSERDESRST (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK RDENABLE (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_FREQ_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK OCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH MEMREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHASER_OUT_PHY_PHASER_OUT_PHYPHASER_OUT_PHY_OUTPUT_CLK_SRC_PHASE_REF") | 
|  | (INSTANCE PHASER_OUT_PHY) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH PHASEREFCLK OCLK (0.000::0.000)(0.000::0.000)) | 
|  | (IOPATH PHASEREFCLK OCLKDIV (0.000::0.000)(0.000::0.000)) | 
|  | ) | 
|  | ) | 
|  | ) | 
|  | (CELL | 
|  | (CELLTYPE "PHY_CONTROL_PHY_CONTROLPHY_CONTROL") | 
|  | (INSTANCE PHY_CONTROL) | 
|  | (DELAY | 
|  | (ABSOLUTE | 
|  | (IOPATH MEMREFCLK AUXOUTPUT (0.265::0.305)(0.542::0.624)) | 
|  | (IOPATH MEMREFCLK INBURSTPENDING (0.316::0.363)(0.689::0.792)) | 
|  | (IOPATH MEMREFCLK INRANKA (0.306::0.353)(0.660::0.759)) | 
|  | (IOPATH MEMREFCLK INRANKB (0.316::0.363)(0.688::0.791)) | 
|  | (IOPATH MEMREFCLK INRANKC (0.319::0.367)(0.697::0.802)) | 
|  | (IOPATH MEMREFCLK INRANKD (0.310::0.357)(0.667::0.768)) | 
|  | (IOPATH MEMREFCLK OUTBURSTPENDING (0.311::0.358)(0.676::0.778)) | 
|  | (IOPATH MEMREFCLK PCENABLECALIB (0.265::0.305)(0.590::0.679)) | 
|  | (IOPATH MEMREFCLK PHYCTLEMPTY (0.313::0.360)(0.541::0.622)) | 
|  | (IOPATH MEMREFCLK TESTOUTPUT (0.504::0.579)(1.131::1.301)) | 
|  | (IOPATH PHYCLK PHYCTLALMOSTFULL (0.158::0.182)(0.338::0.389)) | 
|  | (IOPATH PHYCLK PHYCTLFULL (0.151::0.174)(0.321::0.369)) | 
|  | (IOPATH PHYCLK PHYCTLREADY (0.174::0.200)(0.368::0.423)) | 
|  | ) | 
|  | ) | 
|  | (TIMINGCHECK | 
|  | (HOLD PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.203::0.233)) | 
|  | (SETUP PHYCTLMSTREMPTY (posedge MEMREFCLK) (0.010::0.011)) | 
|  | (HOLD PHYCTLWD (posedge PHYCLK) (0.172::0.198)) | 
|  | (SETUP PHYCTLWD (posedge PHYCLK) (0.215::0.248)) | 
|  | (HOLD PHYCTLWRENABLE (posedge PHYCLK) (0.049::0.056)) | 
|  | (SETUP PHYCTLWRENABLE (posedge PHYCLK) (0.327::0.376)) | 
|  | (HOLD SYNCIN (posedge MEMREFCLK) (0.151::0.174)) | 
|  | (SETUP SYNCIN (posedge MEMREFCLK) (0.158::0.182)) | 
|  | (HOLD TESTINPUT (posedge MEMREFCLK) (0.049::0.056)) | 
|  | (SETUP TESTINPUT (posedge MEMREFCLK) (0.244::0.281)) | 
|  | (HOLD TESTSELECT (posedge MEMREFCLK) (0.049::0.056)) | 
|  | (SETUP TESTSELECT (posedge MEMREFCLK) (0.244::0.281)) | 
|  | ) | 
|  | ) | 
|  | ) |