Updating all based on "Merge pull request #941 from litghost/fixup_arty_harnes". See [Info File](Info.md) for details. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
diff --git a/Info.md b/Info.md index ee3aabb..5c99869 100644 --- a/Info.md +++ b/Info.md
@@ -37,20 +37,20 @@ # Details -Last updated on Tue 09 Jul 2019 09:31:53 PM UTC (2019-07-09T21:31:53+00:00). +Last updated on Thu 11 Jul 2019 05:54:48 PM UTC (2019-07-11T17:54:48+00:00). -Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [948a3b2](https://github.com/SymbiFlow/prjxray/commit/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c). +Created using [Project X-Ray](https://github.com/SymbiFlow/prjxray) version [24d852c](https://github.com/SymbiFlow/prjxray/commit/24d852c016e938ca655222ef44219de465b94d6e). Latest commit was; ``` -commit 948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c -Merge: 219f0f0 e096d9c -Author: Tomasz Michalak <tmichalak@antmicro.com> -Date: Thu Jul 4 23:32:20 2019 +0200 +commit 24d852c016e938ca655222ef44219de465b94d6e +Merge: 36af12c 3345f30 +Author: litghost <537074+litghost@users.noreply.github.com> +Date: Wed Jul 10 22:52:45 2019 -0700 - Merge pull request #915 from antmicro/913_hclk_ioi_baseaddress + Merge pull request #941 from litghost/fixup_arty_harnes - Calculate base addresses for HCLK_IOI3 tiles. + Fix D9/B8 in arty-swbut harness. ``` @@ -59,7 +59,7 @@ ### Settings -Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c/settings/artix7.sh) +Created using following [settings/artix7.sh (sha256: 26e1ff93657132928a3b583c95347267d7afeb18a7b7036f0d7a6ea3367ae803)](https://github.com/SymbiFlow/prjxray/blob/24d852c016e938ca655222ef44219de465b94d6e/settings/artix7.sh) ```shell export XRAY_DATABASE="artix7" export XRAY_PART="xc7a50tfgg484-1" @@ -142,8 +142,8 @@ * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_hclk_l.origin_info.db`](./artix7/mask_hclk_l.origin_info.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./artix7/mask_hclk_r.db`](./artix7/mask_hclk_r.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/mask_hclk_r.origin_info.db`](./artix7/mask_hclk_r.origin_info.db) - * [`653d03789df2c691773f96543abe1ed87e932c2791f5073dd20cd8961257da51 ./artix7/mask_liob33.db`](./artix7/mask_liob33.db) - * [`653d03789df2c691773f96543abe1ed87e932c2791f5073dd20cd8961257da51 ./artix7/mask_riob33.db`](./artix7/mask_riob33.db) + * [`6ce58e9c76af4fe684ab556cacf92d118b75ef0c06f04d286c122fd48c19b49a ./artix7/mask_liob33.db`](./artix7/mask_liob33.db) + * [`6ce58e9c76af4fe684ab556cacf92d118b75ef0c06f04d286c122fd48c19b49a ./artix7/mask_riob33.db`](./artix7/mask_riob33.db) * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./artix7/ppips_bram_int_interface_l.db`](./artix7/ppips_bram_int_interface_l.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./artix7/ppips_bram_int_interface_l.origin_info.db`](./artix7/ppips_bram_int_interface_l.origin_info.db) * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./artix7/ppips_bram_int_interface_r.db`](./artix7/ppips_bram_int_interface_r.db) @@ -199,10 +199,10 @@ * [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./artix7/segbits_clbll_l.origin_info.db`](./artix7/segbits_clbll_l.origin_info.db) * [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./artix7/segbits_clbll_r.db`](./artix7/segbits_clbll_r.db) * [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./artix7/segbits_clbll_r.origin_info.db`](./artix7/segbits_clbll_r.origin_info.db) - * [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db) - * [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./artix7/segbits_clblm_l.origin_info.db`](./artix7/segbits_clblm_l.origin_info.db) - * [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db) - * [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./artix7/segbits_clblm_r.origin_info.db`](./artix7/segbits_clblm_r.origin_info.db) + * [`07dca7c6b00f07a2a255f5178153c42bf16aff202623f2e3bc4bb0f2b974ba41 ./artix7/segbits_clblm_l.db`](./artix7/segbits_clblm_l.db) + * [`9d7b3d414b03af80cba56318576751041ab06ea82be9489028d6b0b419caa60b ./artix7/segbits_clblm_l.origin_info.db`](./artix7/segbits_clblm_l.origin_info.db) + * [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64 ./artix7/segbits_clblm_r.db`](./artix7/segbits_clblm_r.db) + * [`1555a95b4e655a99d5f535e3900c91e30dd96513723ef67a8222a0d3fd58861d ./artix7/segbits_clblm_r.origin_info.db`](./artix7/segbits_clblm_r.origin_info.db) * [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./artix7/segbits_clk_bufg_bot_r.db`](./artix7/segbits_clk_bufg_bot_r.db) * [`9358f07a22575c1874e4a56e892c1c513e11d2727081844f10791a4601258f08 ./artix7/segbits_clk_bufg_bot_r.origin_info.db`](./artix7/segbits_clk_bufg_bot_r.origin_info.db) * [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./artix7/segbits_clk_bufg_rebuf.db`](./artix7/segbits_clk_bufg_rebuf.db) @@ -213,6 +213,10 @@ * [`cde71c02d36c0a41d0706b944568ce03c0992ca2853276bc193470ec83d86186 ./artix7/segbits_clk_hrow_bot_r.origin_info.db`](./artix7/segbits_clk_hrow_bot_r.origin_info.db) * [`972ea949e0bc360892d15ec0313d04e416a10a10fa594f3c361d37c357d59992 ./artix7/segbits_clk_hrow_top_r.db`](./artix7/segbits_clk_hrow_top_r.db) * [`b66f2fcf9007247c5146cca61ddb82b815130d9dc8c54bca75e7f239b5bb64ae ./artix7/segbits_clk_hrow_top_r.origin_info.db`](./artix7/segbits_clk_hrow_top_r.origin_info.db) + * [`e99df1b0ef107704b36091d4e28cd920c55258c609faffb8236eb3d387b1f3e7 ./artix7/segbits_cmt_top_l_upper_t.db`](./artix7/segbits_cmt_top_l_upper_t.db) + * [`308e4b11c5522f29b1ce0fabe136f60ef41268f483286b64a7e1422c9e9c09c6 ./artix7/segbits_cmt_top_l_upper_t.origin_info.db`](./artix7/segbits_cmt_top_l_upper_t.origin_info.db) + * [`850a4874662716370ed864e5a851eda2c362d5c51901d3d02cc6735b5b946865 ./artix7/segbits_cmt_top_r_upper_t.db`](./artix7/segbits_cmt_top_r_upper_t.db) + * [`b94347c375638c5f423fcb282b33a692cd4a0500febed8756ea6d438923f051d ./artix7/segbits_cmt_top_r_upper_t.origin_info.db`](./artix7/segbits_cmt_top_r_upper_t.origin_info.db) * [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./artix7/segbits_dsp_l.db`](./artix7/segbits_dsp_l.db) * [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./artix7/segbits_dsp_l.origin_info.db`](./artix7/segbits_dsp_l.origin_info.db) * [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./artix7/segbits_dsp_r.db`](./artix7/segbits_dsp_r.db) @@ -226,13 +230,13 @@ * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./artix7/segbits_hclk_r.db`](./artix7/segbits_hclk_r.db) * [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./artix7/segbits_hclk_r.origin_info.db`](./artix7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./artix7/segbits_int_l.db`](./artix7/segbits_int_l.db) - * [`cd7974e166e00e172584a468ae4f27e3d7d38af14e47a4313afff1ae94bbebc7 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db) + * [`0a0b68b503b23f1fc0fef91d7c92d0c98da7dbcb0635b495babbf6123a074956 ./artix7/segbits_int_l.origin_info.db`](./artix7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./artix7/segbits_int_r.db`](./artix7/segbits_int_r.db) - * [`aec7ff22207dd629b706cf308707cb27ba8aa80271f40138b99675e06284cd23 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db) - * [`6ece030404b8fd09095382730639d261e0402e2c513bf07d9ec301a7311ceb7e ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db) - * [`f100a6e9abd51bbddb7aacb810c00b7240b2f50a25b3f331121d923198d43d8f ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db) - * [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db) - * [`27a74d9eddb6f960a94f107b28343d88dc8c2274de61be865e21e3a8d1f4e9f1 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db) + * [`5d31fdae73bec297b9ebee977359713181c86077cae89368efd6d74adcfd46c7 ./artix7/segbits_int_r.origin_info.db`](./artix7/segbits_int_r.origin_info.db) + * [`216bf1f206b5e98e453f2d4b4d64de01788d050238f427c975d9b8559eae55b0 ./artix7/segbits_liob33.db`](./artix7/segbits_liob33.db) + * [`90f81fd31255224e6dd4725832c690159a59fb168c83e59fdae10fd6d291ddcb ./artix7/segbits_liob33.origin_info.db`](./artix7/segbits_liob33.origin_info.db) + * [`6382b44bc537fca6c822cab52f93a7486b402db753743168a462abbb067662e1 ./artix7/segbits_riob33.db`](./artix7/segbits_riob33.db) + * [`f651df59cf27fa9883dd8487653b0f571cb199311106a78e23f7588cc94bf917 ./artix7/segbits_riob33.origin_info.db`](./artix7/segbits_riob33.origin_info.db) * [`2bc07bf06b86af1985fe1c76da7bd6d858768dd6d9e99344a3c52d490b797cdb ./artix7/settings.sh`](./artix7/settings.sh) * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./artix7/site_type_BSCAN.json`](./artix7/site_type_BSCAN.json) * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./artix7/site_type_BUFGCTRL.json`](./artix7/site_type_BUFGCTRL.json) @@ -391,7 +395,7 @@ * [`5fb8795e142a7bc6955e6c50089540c890aeb3b3a6c326e6e24a6e4983d91f62 ./artix7/tile_type_VBRK_EXT.json`](./artix7/tile_type_VBRK_EXT.json) * [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./artix7/tile_type_VFRAME.json`](./artix7/tile_type_VFRAME.json) * [`1604d48580815e26069c2b4909fcc50e8e8f974ad0beb349ced2329c302bb06b ./artix7/tileconn.json`](./artix7/tileconn.json) - * [`864eb276f06fa2407d1d48695c9b63704690ec691fd000736174e4ae99ab3f46 ./artix7/tilegrid.json`](./artix7/tilegrid.json) + * [`dce02654691e0f64613054db1fabfcf4d44f02d6090c6117014a07933d5106e0 ./artix7/tilegrid.json`](./artix7/tilegrid.json) * [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./artix7/timings/BRAM_L.sdf`](./artix7/timings/BRAM_L.sdf) * [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./artix7/timings/BRAM_R.sdf`](./artix7/timings/BRAM_R.sdf) * [`120e57d254f8394507718098dd4fe299ede60d3228c3b4e90669577c9de64042 ./artix7/timings/CFG_CENTER_MID.sdf`](./artix7/timings/CFG_CENTER_MID.sdf) @@ -453,7 +457,7 @@ ### Settings -Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c/settings/kintex7.sh) +Created using following [settings/kintex7.sh (sha256: 794538b550d399255cbafeeb1b5ff183dc66ebc6cd8dc0f725e3f6a3977f757d)](https://github.com/SymbiFlow/prjxray/blob/24d852c016e938ca655222ef44219de465b94d6e/settings/kintex7.sh) ```shell export XRAY_DATABASE="kintex7" export XRAY_PART="xc7k70tfbg676-2" @@ -518,8 +522,8 @@ * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_hclk_l.origin_info.db`](./kintex7/mask_hclk_l.origin_info.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./kintex7/mask_hclk_r.db`](./kintex7/mask_hclk_r.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/mask_hclk_r.origin_info.db`](./kintex7/mask_hclk_r.origin_info.db) - * [`2739be1268a3e0fcf6d9c95960d3982eea4ca3ee019412166ab30533d9965190 ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db) - * [`2739be1268a3e0fcf6d9c95960d3982eea4ca3ee019412166ab30533d9965190 ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db) + * [`3338e1efe9b0d2533d0a8dc8fdd8f5659d94a6919b55847b065484d0f4d90efa ./kintex7/mask_liob33.db`](./kintex7/mask_liob33.db) + * [`3338e1efe9b0d2533d0a8dc8fdd8f5659d94a6919b55847b065484d0f4d90efa ./kintex7/mask_riob33.db`](./kintex7/mask_riob33.db) * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./kintex7/ppips_bram_int_interface_l.db`](./kintex7/ppips_bram_int_interface_l.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./kintex7/ppips_bram_int_interface_l.origin_info.db`](./kintex7/ppips_bram_int_interface_l.origin_info.db) * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./kintex7/ppips_bram_int_interface_r.db`](./kintex7/ppips_bram_int_interface_r.db) @@ -571,10 +575,10 @@ * [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./kintex7/segbits_clbll_l.origin_info.db`](./kintex7/segbits_clbll_l.origin_info.db) * [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./kintex7/segbits_clbll_r.db`](./kintex7/segbits_clbll_r.db) * [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./kintex7/segbits_clbll_r.origin_info.db`](./kintex7/segbits_clbll_r.origin_info.db) - * [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db) - * [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./kintex7/segbits_clblm_l.origin_info.db`](./kintex7/segbits_clblm_l.origin_info.db) - * [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db) - * [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./kintex7/segbits_clblm_r.origin_info.db`](./kintex7/segbits_clblm_r.origin_info.db) + * [`07dca7c6b00f07a2a255f5178153c42bf16aff202623f2e3bc4bb0f2b974ba41 ./kintex7/segbits_clblm_l.db`](./kintex7/segbits_clblm_l.db) + * [`9d7b3d414b03af80cba56318576751041ab06ea82be9489028d6b0b419caa60b ./kintex7/segbits_clblm_l.origin_info.db`](./kintex7/segbits_clblm_l.origin_info.db) + * [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64 ./kintex7/segbits_clblm_r.db`](./kintex7/segbits_clblm_r.db) + * [`1555a95b4e655a99d5f535e3900c91e30dd96513723ef67a8222a0d3fd58861d ./kintex7/segbits_clblm_r.origin_info.db`](./kintex7/segbits_clblm_r.origin_info.db) * [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./kintex7/segbits_clk_bufg_bot_r.db`](./kintex7/segbits_clk_bufg_bot_r.db) * [`9358f07a22575c1874e4a56e892c1c513e11d2727081844f10791a4601258f08 ./kintex7/segbits_clk_bufg_bot_r.origin_info.db`](./kintex7/segbits_clk_bufg_bot_r.origin_info.db) * [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./kintex7/segbits_clk_bufg_rebuf.db`](./kintex7/segbits_clk_bufg_rebuf.db) @@ -585,6 +589,10 @@ * [`396e42f2564290eb1a382c535631ea6f8f73b78121da9664c83688dac46b4765 ./kintex7/segbits_clk_hrow_bot_r.origin_info.db`](./kintex7/segbits_clk_hrow_bot_r.origin_info.db) * [`375d8ee4051ac320d23f03f93acc7958b5bd6fdce3f05584179ecddf4fb4388a ./kintex7/segbits_clk_hrow_top_r.db`](./kintex7/segbits_clk_hrow_top_r.db) * [`b4d096345faf6b99198cd8409e38fb49d1572f9ddae4c4539f61014d1c897c8f ./kintex7/segbits_clk_hrow_top_r.origin_info.db`](./kintex7/segbits_clk_hrow_top_r.origin_info.db) + * [`4efe7d3c284d19113eee98ca8e796f1805f1da9f48ddb967ea2ae4dbda87fbcf ./kintex7/segbits_cmt_top_l_upper_t.db`](./kintex7/segbits_cmt_top_l_upper_t.db) + * [`79bbfd32b228c0c0a42cccec63c7a4e725df3292ecc58bee6cf76a6255e4f3e2 ./kintex7/segbits_cmt_top_l_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_l_upper_t.origin_info.db) + * [`a6b47c2013cde02576f18e56b37a0c0915ded789424afd5640a969890f0102d8 ./kintex7/segbits_cmt_top_r_upper_t.db`](./kintex7/segbits_cmt_top_r_upper_t.db) + * [`bc109f11724511025e1bff37c1af0561b0d6e339df47c068bde36424d8110002 ./kintex7/segbits_cmt_top_r_upper_t.origin_info.db`](./kintex7/segbits_cmt_top_r_upper_t.origin_info.db) * [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./kintex7/segbits_dsp_l.db`](./kintex7/segbits_dsp_l.db) * [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./kintex7/segbits_dsp_l.origin_info.db`](./kintex7/segbits_dsp_l.origin_info.db) * [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./kintex7/segbits_dsp_r.db`](./kintex7/segbits_dsp_r.db) @@ -598,13 +606,13 @@ * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./kintex7/segbits_hclk_r.db`](./kintex7/segbits_hclk_r.db) * [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./kintex7/segbits_hclk_r.origin_info.db`](./kintex7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./kintex7/segbits_int_l.db`](./kintex7/segbits_int_l.db) - * [`ee3b5f2adbd4f3b7d6135dcb4f7183f379fe95e19bbbf59583c1aa801f208677 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db) + * [`b89e756998ef8ad4e931e0e3ea37606789e496e4b7681b8e8d1967c8be0f4ad6 ./kintex7/segbits_int_l.origin_info.db`](./kintex7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./kintex7/segbits_int_r.db`](./kintex7/segbits_int_r.db) - * [`64574afb2e9615d414a0515948f395a8d871403c70ab3ed0d7367f0798cbad95 ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db) - * [`bed06fc405947c72a47a7fbac7adbc220efd2dc8d73f321ed70b8d2490ab745b ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db) - * [`61fef185b5fd5aa46425d9e28b61f0d6b1b4c4a0577f1452801a6531c45bee7b ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db) - * [`8ec421f8f4ce1bab7e81bcbf0cbdc37fb3f6ed4715bc2fdf75db336805efc53e ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db) - * [`25338a0bd1e45606e0a868db6989ce6c3bcef6dab0daea700debd5ca597f9f8d ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db) + * [`1c259198ed7f9d03a4d3e832bd50ef53c404e2a9b4bafd61dfdbff681789f56e ./kintex7/segbits_int_r.origin_info.db`](./kintex7/segbits_int_r.origin_info.db) + * [`7f7678239ee07a0a6e14f485125edcf3113283c32fdf30ef476380a6a03855ec ./kintex7/segbits_liob33.db`](./kintex7/segbits_liob33.db) + * [`f3d41676543f572882ae48a2fad5f63dfaa3b39be46c051ae167e571f787734f ./kintex7/segbits_liob33.origin_info.db`](./kintex7/segbits_liob33.origin_info.db) + * [`f9ee96e8ec2bc5ec3385894c5f27be07946f4f7e954eac1614cbadc0652948ed ./kintex7/segbits_riob33.db`](./kintex7/segbits_riob33.db) + * [`1945f23947816d901036e054895b21b7e911554976974601e3e75d112b100e41 ./kintex7/segbits_riob33.origin_info.db`](./kintex7/segbits_riob33.origin_info.db) * [`c4fe49753a5ba6b4abc688337d5df26f2101ccfca3dd4270ca77e39e5221bfe9 ./kintex7/settings.sh`](./kintex7/settings.sh) * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./kintex7/site_type_BSCAN.json`](./kintex7/site_type_BSCAN.json) * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./kintex7/site_type_BUFGCTRL.json`](./kintex7/site_type_BUFGCTRL.json) @@ -771,7 +779,7 @@ * [`5fb8795e142a7bc6955e6c50089540c890aeb3b3a6c326e6e24a6e4983d91f62 ./kintex7/tile_type_VBRK_EXT.json`](./kintex7/tile_type_VBRK_EXT.json) * [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./kintex7/tile_type_VFRAME.json`](./kintex7/tile_type_VFRAME.json) * [`77985c4643b2984db517096deb4fc80ae992794089aea91c21b456d81fcbadd2 ./kintex7/tileconn.json`](./kintex7/tileconn.json) - * [`f16812056bc9ba5f599e2874acc4ab958f07fd21d763637aba9108d8e75795de ./kintex7/tilegrid.json`](./kintex7/tilegrid.json) + * [`f38ea56bdbcda19fa2979a5a3c13e0af26d665a3880ac7ec14607229e8c54252 ./kintex7/tilegrid.json`](./kintex7/tilegrid.json) * [`916a9b924454c10b835d561d80434461c5a9a2824bf85c3cdeeee5f0dedfcb24 ./kintex7/xc7k70tfbg676-2.json`](./kintex7/xc7k70tfbg676-2.json) * [`44c1530cc9a184551c98face08bd4ab0a7ec3883623175a52da5c59fba9bfa38 ./kintex7/xc7k70tfbg676-2.yaml`](./kintex7/xc7k70tfbg676-2.yaml) * [`f7b5e70b102e1e3d624f61c470f77374f14136579f69a92c061485fddea92239 ./kintex7/xc7k70tfbg676-2_package_pins.csv`](./kintex7/xc7k70tfbg676-2_package_pins.csv) @@ -781,7 +789,7 @@ ### Settings -Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/948a3b21cc7bf9c3a1f0c638c95f3c1ddb0f7f0c/settings/zynq7.sh) +Created using following [settings/zynq7.sh (sha256: 61298e89dcc873eadba47f5c2f9f72a38fa022583b2c7ff89246b2e051585ad8)](https://github.com/SymbiFlow/prjxray/blob/24d852c016e938ca655222ef44219de465b94d6e/settings/zynq7.sh) ```shell export XRAY_DATABASE="zynq7" export XRAY_PART="xc7z010clg400-1" @@ -850,8 +858,8 @@ * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_l.origin_info.db`](./zynq7/mask_hclk_l.origin_info.db) * [`76d1e0bd4b7ad492cf3fe8698b2b5f46f7dcc5fe446984e5dccae373c63edafd ./zynq7/mask_hclk_r.db`](./zynq7/mask_hclk_r.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/mask_hclk_r.origin_info.db`](./zynq7/mask_hclk_r.origin_info.db) - * [`43d42ac58a77f62efe8e538fb452fffa81427276864b05894feba7f7338cde2d ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db) - * [`02973a3ddaed35cebdc965205244d155a3b2f031baf25b2bc56380ab932717eb ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db) + * [`7b316407a6f773f00ce4fc85092843641287fc759b8f25bd9a79d63a5b878650 ./zynq7/mask_liob33.db`](./zynq7/mask_liob33.db) + * [`cfcccd307c4d7153897c49744f30674a31342b221be7354388f8d665d3539da3 ./zynq7/mask_riob33.db`](./zynq7/mask_riob33.db) * [`d94e4d13df16da498224f0e94deaa310fbf471b6f9ec0ec8b2308fe62fa2eeaf ./zynq7/ppips_bram_int_interface_l.db`](./zynq7/ppips_bram_int_interface_l.db) * [`e3b0c44298fc1c149afbf4c8996fb92427ae41e4649b934ca495991b7852b855 ./zynq7/ppips_bram_int_interface_l.origin_info.db`](./zynq7/ppips_bram_int_interface_l.origin_info.db) * [`b48d766ac6f9dd0e21280d3a04dd448ea39016143309c0c7867fc00d730a59ae ./zynq7/ppips_bram_int_interface_r.db`](./zynq7/ppips_bram_int_interface_r.db) @@ -902,10 +910,10 @@ * [`7ceeda50b084788b94f2d2088b791565edb7d4cff97b39c9c4adb81d4252ca94 ./zynq7/segbits_clbll_l.origin_info.db`](./zynq7/segbits_clbll_l.origin_info.db) * [`c2ac0aeafc4d1e528e743c49fc00eba3b8b49068f034a4c0ab82df5dd9fb683b ./zynq7/segbits_clbll_r.db`](./zynq7/segbits_clbll_r.db) * [`6a35dceeb20430aa3e83baa2ce468fa404edac6b0ec27866e0ab084161578532 ./zynq7/segbits_clbll_r.origin_info.db`](./zynq7/segbits_clbll_r.origin_info.db) - * [`5fb4543665c056eaaef652e0fbb35173f66cdc49bdc1679e2ebbd118bfb3009a ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db) - * [`337f9161fff289679274c0bdef0058097d3bdfea5942ac4d90b64b31ba6e3ad2 ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db) - * [`cf646f6b44e3f7b36f5e670b2af3ecf6337abd17b196064adc24b0aa8db8d14c ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db) - * [`4a6d5462ad028d58a5d40feacfd2cd6461c8d166992ff951979a4a32f45a4653 ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db) + * [`07dca7c6b00f07a2a255f5178153c42bf16aff202623f2e3bc4bb0f2b974ba41 ./zynq7/segbits_clblm_l.db`](./zynq7/segbits_clblm_l.db) + * [`9d7b3d414b03af80cba56318576751041ab06ea82be9489028d6b0b419caa60b ./zynq7/segbits_clblm_l.origin_info.db`](./zynq7/segbits_clblm_l.origin_info.db) + * [`3ddfeca1b01bdc04b4f1b3d0dc73cf39f4230708fbbcb5b6170d5b50dc49ad64 ./zynq7/segbits_clblm_r.db`](./zynq7/segbits_clblm_r.db) + * [`1555a95b4e655a99d5f535e3900c91e30dd96513723ef67a8222a0d3fd58861d ./zynq7/segbits_clblm_r.origin_info.db`](./zynq7/segbits_clblm_r.origin_info.db) * [`8d43bd09b2f7127ff9ed4803b92303d72c827d10b8b8d943c295343257b3e818 ./zynq7/segbits_clk_bufg_bot_r.db`](./zynq7/segbits_clk_bufg_bot_r.db) * [`9358f07a22575c1874e4a56e892c1c513e11d2727081844f10791a4601258f08 ./zynq7/segbits_clk_bufg_bot_r.origin_info.db`](./zynq7/segbits_clk_bufg_bot_r.origin_info.db) * [`d094c55a62408bd79c2606a8fc10839b23d979e4e924ced0d4276d285db7810f ./zynq7/segbits_clk_bufg_rebuf.db`](./zynq7/segbits_clk_bufg_rebuf.db) @@ -916,6 +924,10 @@ * [`eb566cda47e23291d9a3bfdef765233a030d6ff0d8d5debf68e9ade16d2fc6f9 ./zynq7/segbits_clk_hrow_bot_r.origin_info.db`](./zynq7/segbits_clk_hrow_bot_r.origin_info.db) * [`724bcea2bc588cf5089840f66c6a813ad6cc9958fec6b5db2d44ef75b8843c14 ./zynq7/segbits_clk_hrow_top_r.db`](./zynq7/segbits_clk_hrow_top_r.db) * [`5e5bc3b26dd2cc2632e95f390f87e9a7cc7cfd1f163e20447c02b0e2e111889d ./zynq7/segbits_clk_hrow_top_r.origin_info.db`](./zynq7/segbits_clk_hrow_top_r.origin_info.db) + * [`69eda3b03d20087c121c15e79559152eeae2619c5a86477ad763be9b63b58f4a ./zynq7/segbits_cmt_top_l_upper_t.db`](./zynq7/segbits_cmt_top_l_upper_t.db) + * [`302b0d51e98f856a498132119f42c10248345ab5181ab60cabd1f2fcb3c6344f ./zynq7/segbits_cmt_top_l_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_l_upper_t.origin_info.db) + * [`6b205562d2e870f43d7959a05b1b8fbd75bfbb08878bb7ec5239d6b419ce3117 ./zynq7/segbits_cmt_top_r_upper_t.db`](./zynq7/segbits_cmt_top_r_upper_t.db) + * [`29023fed85b544c2d849067d1c945cb9cdc64fa2f4070acf6496ea132f9f3997 ./zynq7/segbits_cmt_top_r_upper_t.origin_info.db`](./zynq7/segbits_cmt_top_r_upper_t.origin_info.db) * [`0c4a6e4bc385a8b3a43d05a06d8e87c8822cf2cc1742593167244ff194af4a5e ./zynq7/segbits_dsp_l.db`](./zynq7/segbits_dsp_l.db) * [`85105e324b53c9b8a3d60a3631e125c2e6dc1329e017636232313c4aa8e1576d ./zynq7/segbits_dsp_l.origin_info.db`](./zynq7/segbits_dsp_l.origin_info.db) * [`b014d7e2b101b0b0540a539cb74a76ccbe3a494e225e8e510bf258a457b18685 ./zynq7/segbits_dsp_r.db`](./zynq7/segbits_dsp_r.db) @@ -927,13 +939,13 @@ * [`51288ec0be63172fcb2a12a92853150c62a21e894c2d42a2586046c462bf57a9 ./zynq7/segbits_hclk_r.db`](./zynq7/segbits_hclk_r.db) * [`0e9b5da6def4776e2ca8dd59af8f4334bf5cfb88d99b323be25dd6ba2e3386f7 ./zynq7/segbits_hclk_r.origin_info.db`](./zynq7/segbits_hclk_r.origin_info.db) * [`0ea44e8dfaf97ed200f30b2afe117e94e1a68bdb26af2e09e69e855414779520 ./zynq7/segbits_int_l.db`](./zynq7/segbits_int_l.db) - * [`8bcecca9f265dc6d40bc00caecfc14a2ea43217ec8ceb36ece26f1572119fae7 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db) + * [`541c37385792706a1b37a16f09d8ba3a66cfe46a1dba00084e5fce3c74a7ad59 ./zynq7/segbits_int_l.origin_info.db`](./zynq7/segbits_int_l.origin_info.db) * [`1541c7832dd161c5b3b5745d08fe0ee6f92bfbd372b76c12f54afc032c888556 ./zynq7/segbits_int_r.db`](./zynq7/segbits_int_r.db) - * [`ebcae3b19d45466fc0b1c17e9ed4d94166998b9dba75940862c07a8f5788e66a ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db) - * [`d1ad493bd149ba47ac50a68fef57809d21a1ef36db63725317a12df9266ca8d8 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db) - * [`caaa32eadfca7d6417a09d5357f8c1eea23bdb325164857de03b8798bdf252bb ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db) - * [`32cae09e1ab0ba143570d702cfee2a3e04948c131f6511e6040c684638c67ed4 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) - * [`27a74d9eddb6f960a94f107b28343d88dc8c2274de61be865e21e3a8d1f4e9f1 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db) + * [`a8982b6f0a9d538d10c61c1a90624d3dfb54652ccf1fc5ccc64d27b573b04821 ./zynq7/segbits_int_r.origin_info.db`](./zynq7/segbits_int_r.origin_info.db) + * [`f85762b3e63eabe167710bb6d6273810f3a4e3e11d78513677b403db459b9e44 ./zynq7/segbits_liob33.db`](./zynq7/segbits_liob33.db) + * [`b37fd628a5530efb3e2de4bab01b2c9db5917e8083ca9a361700714a45d2cf63 ./zynq7/segbits_liob33.origin_info.db`](./zynq7/segbits_liob33.origin_info.db) + * [`6382b44bc537fca6c822cab52f93a7486b402db753743168a462abbb067662e1 ./zynq7/segbits_riob33.db`](./zynq7/segbits_riob33.db) + * [`f651df59cf27fa9883dd8487653b0f571cb199311106a78e23f7588cc94bf917 ./zynq7/segbits_riob33.origin_info.db`](./zynq7/segbits_riob33.origin_info.db) * [`ee26e7dbf78c2a37118c49ce7edb5fa44afd51850a24824ba8b68e34366f0787 ./zynq7/settings.sh`](./zynq7/settings.sh) * [`ac6ba9ad814503f0fdc1dabb4292aaccd1a2195f5b348276cfee12aed3d96a70 ./zynq7/site_type_BSCAN.json`](./zynq7/site_type_BSCAN.json) * [`64724ba2f8af98df5e1d92e5c2da2e6d5a41eec6580f796405e271dadb4e63be ./zynq7/site_type_BUFGCTRL.json`](./zynq7/site_type_BUFGCTRL.json) @@ -1067,7 +1079,7 @@ * [`9d6388021982de6d4a676c2c2fe6543029a2f44db45d290f4e827d35b91a2a6b ./zynq7/tile_type_VBRK.json`](./zynq7/tile_type_VBRK.json) * [`63851d7ed48855486ee7e04a6332935799e8d2f3524ec6d627ea6e5d2e7cbfa4 ./zynq7/tile_type_VFRAME.json`](./zynq7/tile_type_VFRAME.json) * [`e6d0ebf9b27f60f4afdab85a357bff4d7cf2cd77c3a6c0f2d887022cda874066 ./zynq7/tileconn.json`](./zynq7/tileconn.json) - * [`ea21496ec29a0041f148c5fa5ce5bc4d81ea7ed0333cf6791b8c46bccca58717 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json) + * [`4d9d291298a5d9f2077b9d3b6356cf1f61dec188040afd3261f1194a1b7a5a30 ./zynq7/tilegrid.json`](./zynq7/tilegrid.json) * [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./zynq7/timings/BRAM_L.sdf`](./zynq7/timings/BRAM_L.sdf) * [`71fdc4268e7b5c7fa3884f2d71c7de077e7e46079b46d8fd1ac168735555302f ./zynq7/timings/BRAM_R.sdf`](./zynq7/timings/BRAM_R.sdf) * [`120e57d254f8394507718098dd4fe299ede60d3228c3b4e90669577c9de64042 ./zynq7/timings/CFG_CENTER_MID.sdf`](./zynq7/timings/CFG_CENTER_MID.sdf)
diff --git a/artix7/mask_liob33.db b/artix7/mask_liob33.db index dd88e69..2e9d88a 100644 --- a/artix7/mask_liob33.db +++ b/artix7/mask_liob33.db
@@ -1,6 +1,3 @@ -bit 00_02 -bit 00_07 -bit 00_09 bit 00_10 bit 00_11 bit 00_14 @@ -10,16 +7,6 @@ bit 00_35 bit 00_38 bit 00_39 -bit 00_42 -bit 00_43 -bit 00_45 -bit 00_50 -bit 00_51 -bit 00_54 -bit 00_58 -bit 00_66 -bit 00_71 -bit 00_73 bit 00_74 bit 00_75 bit 00_78 @@ -29,399 +16,103 @@ bit 00_99 bit 00_102 bit 00_103 -bit 00_106 -bit 00_107 -bit 00_114 -bit 01_00 -bit 01_01 -bit 01_02 -bit 01_04 -bit 01_05 -bit 01_06 bit 01_09 bit 01_10 bit 01_13 bit 01_14 -bit 01_32 bit 01_33 -bit 01_36 bit 01_37 bit 01_38 bit 01_40 -bit 01_41 -bit 01_44 -bit 01_50 -bit 01_58 -bit 01_64 -bit 01_65 -bit 01_66 -bit 01_68 -bit 01_69 -bit 01_70 bit 01_73 bit 01_74 bit 01_77 bit 01_78 -bit 01_96 bit 01_97 -bit 01_100 bit 01_101 bit 01_102 bit 01_104 -bit 01_105 -bit 01_114 -bit 02_05 -bit 02_06 bit 02_07 -bit 02_09 -bit 02_10 -bit 02_11 -bit 02_13 -bit 02_14 -bit 02_15 -bit 02_18 -bit 02_22 -bit 02_23 -bit 02_30 -bit 02_31 -bit 02_34 -bit 02_35 -bit 02_38 -bit 02_39 -bit 02_46 -bit 02_47 -bit 02_50 -bit 02_51 -bit 02_54 -bit 02_55 -bit 02_62 -bit 02_66 -bit 02_67 -bit 02_69 -bit 02_70 -bit 02_71 -bit 02_73 -bit 02_75 -bit 02_77 -bit 02_78 -bit 02_79 -bit 02_82 -bit 02_86 -bit 02_87 -bit 02_94 -bit 02_95 -bit 02_102 -bit 02_103 -bit 02_114 -bit 02_117 -bit 02_118 -bit 02_119 -bit 02_126 -bit 02_127 -bit 03_02 -bit 03_05 -bit 03_06 -bit 03_10 -bit 03_13 -bit 03_14 -bit 03_21 -bit 03_29 -bit 03_36 -bit 03_37 -bit 03_38 -bit 03_45 -bit 03_52 -bit 03_53 -bit 03_54 -bit 03_60 -bit 03_61 -bit 03_62 -bit 03_66 -bit 03_68 -bit 03_69 -bit 03_70 -bit 03_74 -bit 03_77 -bit 03_78 -bit 03_85 -bit 03_86 -bit 03_93 -bit 03_101 -bit 03_102 bit 03_116 -bit 03_117 -bit 03_118 -bit 03_126 bit 04_04 -bit 04_05 -bit 04_06 -bit 04_07 -bit 04_10 -bit 04_11 -bit 04_12 -bit 04_14 -bit 04_15 -bit 04_19 -bit 04_20 -bit 04_21 -bit 04_22 -bit 04_23 -bit 04_27 -bit 04_28 -bit 04_30 -bit 04_31 -bit 04_35 -bit 04_36 -bit 04_37 -bit 04_39 -bit 04_44 -bit 04_47 -bit 04_51 -bit 04_52 -bit 04_53 -bit 04_55 -bit 04_63 -bit 04_66 -bit 04_68 -bit 04_69 -bit 04_70 -bit 04_74 -bit 04_75 -bit 04_76 -bit 04_78 -bit 04_79 -bit 04_83 -bit 04_84 -bit 04_85 -bit 04_86 -bit 04_87 -bit 04_94 -bit 04_95 -bit 04_100 -bit 04_101 -bit 04_103 -bit 04_115 -bit 04_116 -bit 04_117 -bit 04_119 -bit 04_124 -bit 05_01 -bit 05_02 -bit 05_05 -bit 05_06 -bit 05_09 -bit 05_10 -bit 05_12 -bit 05_13 -bit 05_14 -bit 05_17 -bit 05_18 -bit 05_22 -bit 05_25 -bit 05_26 -bit 05_28 -bit 05_33 -bit 05_34 -bit 05_36 -bit 05_37 -bit 05_38 -bit 05_44 -bit 05_46 -bit 05_49 -bit 05_50 -bit 05_52 -bit 05_53 -bit 05_58 -bit 05_60 -bit 05_63 -bit 05_65 -bit 05_66 -bit 05_69 bit 05_70 -bit 05_73 -bit 05_74 -bit 05_76 -bit 05_77 -bit 05_81 -bit 05_82 -bit 05_86 -bit 05_89 -bit 05_94 -bit 05_98 -bit 05_101 -bit 05_102 -bit 05_113 -bit 05_114 -bit 05_116 -bit 05_117 bit 05_119 bit 06_01 -bit 06_02 bit 06_03 -bit 06_04 -bit 06_05 -bit 06_06 -bit 06_10 bit 06_11 -bit 06_12 -bit 06_13 -bit 06_14 -bit 06_15 bit 06_17 -bit 06_20 -bit 06_22 -bit 06_24 -bit 06_27 -bit 06_28 bit 06_29 -bit 06_30 -bit 06_31 bit 06_33 bit 06_35 -bit 06_36 -bit 06_37 -bit 06_39 bit 06_43 -bit 06_46 bit 06_49 bit 06_51 -bit 06_52 -bit 06_53 -bit 06_55 bit 06_59 bit 06_61 -bit 06_64 bit 06_65 -bit 06_66 bit 06_67 -bit 06_68 -bit 06_69 -bit 06_70 -bit 06_71 -bit 06_72 -bit 06_74 -bit 06_75 -bit 06_76 -bit 06_77 -bit 06_78 -bit 06_79 -bit 06_80 bit 06_81 bit 06_83 -bit 06_84 -bit 06_85 -bit 06_86 bit 06_91 -bit 06_92 -bit 06_93 -bit 06_94 bit 06_97 bit 06_99 -bit 06_100 -bit 06_101 bit 06_103 bit 06_107 bit 06_113 bit 06_115 -bit 06_116 -bit 06_117 -bit 06_119 bit 06_121 bit 06_123 bit 07_00 bit 07_02 -bit 07_03 bit 07_04 -bit 07_05 bit 07_06 -bit 07_07 bit 07_08 -bit 07_10 -bit 07_11 bit 07_12 -bit 07_13 bit 07_14 -bit 07_15 bit 07_16 -bit 07_19 bit 07_20 bit 07_22 -bit 07_23 bit 07_24 -bit 07_25 -bit 07_26 -bit 07_27 bit 07_28 bit 07_30 -bit 07_31 bit 07_32 -bit 07_34 -bit 07_35 bit 07_36 -bit 07_37 bit 07_38 -bit 07_39 bit 07_40 bit 07_44 bit 07_46 -bit 07_47 bit 07_48 -bit 07_50 -bit 07_51 -bit 07_53 +bit 07_52 bit 07_54 -bit 07_55 bit 07_56 bit 07_58 -bit 07_59 bit 07_60 bit 07_62 -bit 07_63 bit 07_64 -bit 07_65 -bit 07_67 +bit 07_66 bit 07_68 -bit 07_69 bit 07_70 bit 07_71 bit 07_72 -bit 07_74 -bit 07_75 bit 07_76 -bit 07_77 bit 07_78 -bit 07_79 bit 07_80 -bit 07_81 -bit 07_82 -bit 07_83 bit 07_84 bit 07_86 -bit 07_87 bit 07_88 -bit 07_91 bit 07_92 bit 07_94 -bit 07_95 -bit 07_96 bit 07_98 -bit 07_99 bit 07_100 bit 07_102 -bit 07_103 bit 07_104 bit 07_108 bit 07_110 bit 07_112 -bit 07_114 -bit 07_115 -bit 07_117 bit 07_118 -bit 07_119 bit 07_120 bit 07_124 bit 07_126 -bit 07_127 bit 08_00 bit 08_01 bit 08_02 @@ -433,23 +124,18 @@ bit 08_08 bit 08_09 bit 08_10 -bit 08_11 -bit 08_12 -bit 08_13 bit 08_14 bit 08_15 bit 08_16 bit 08_17 bit 08_18 -bit 08_20 -bit 08_21 +bit 08_19 bit 08_22 bit 08_23 bit 08_24 bit 08_25 bit 08_26 bit 08_27 -bit 08_28 bit 08_30 bit 08_31 bit 08_32 @@ -468,46 +154,34 @@ bit 08_48 bit 08_49 bit 08_50 -bit 08_51 -bit 08_52 bit 08_54 bit 08_55 bit 08_56 bit 08_57 bit 08_58 bit 08_59 -bit 08_61 bit 08_62 bit 08_63 bit 08_64 bit 08_65 bit 08_66 bit 08_67 -bit 08_68 -bit 08_69 -bit 08_70 bit 08_71 bit 08_72 bit 08_73 bit 08_74 bit 08_75 -bit 08_76 -bit 08_77 bit 08_78 bit 08_79 bit 08_80 bit 08_81 bit 08_82 bit 08_83 -bit 08_84 -bit 08_86 bit 08_87 bit 08_88 bit 08_89 bit 08_90 bit 08_91 -bit 08_92 -bit 08_93 bit 08_94 bit 08_95 bit 08_96 @@ -533,46 +207,30 @@ bit 08_120 bit 08_121 bit 08_122 -bit 08_124 +bit 08_125 bit 08_126 bit 08_127 -bit 09_00 -bit 09_01 bit 09_02 bit 09_03 bit 09_04 bit 09_05 -bit 09_07 -bit 09_08 -bit 09_09 -bit 09_10 bit 09_11 bit 09_12 bit 09_13 bit 09_14 -bit 09_15 bit 09_16 -bit 09_18 bit 09_19 bit 09_20 -bit 09_23 -bit 09_24 -bit 09_26 +bit 09_21 bit 09_27 bit 09_28 bit 09_29 -bit 09_30 -bit 09_31 -bit 09_32 -bit 09_33 bit 09_34 bit 09_35 bit 09_36 bit 09_43 bit 09_44 bit 09_45 -bit 09_46 -bit 09_47 bit 09_48 bit 09_49 bit 09_50 @@ -580,27 +238,17 @@ bit 09_52 bit 09_58 bit 09_59 +bit 09_60 bit 09_61 -bit 09_63 -bit 09_64 -bit 09_65 bit 09_66 bit 09_67 bit 09_68 -bit 09_69 -bit 09_71 -bit 09_72 -bit 09_73 bit 09_75 bit 09_76 bit 09_77 -bit 09_79 bit 09_82 bit 09_83 bit 09_84 -bit 09_85 -bit 09_87 -bit 09_90 bit 09_91 bit 09_92 bit 09_93 @@ -614,9 +262,6 @@ bit 09_108 bit 09_109 bit 09_110 -bit 09_111 -bit 09_112 -bit 09_113 bit 09_114 bit 09_115 bit 09_116 @@ -624,111 +269,66 @@ bit 09_123 bit 09_124 bit 09_125 -bit 09_127 bit 10_00 bit 10_01 bit 10_02 -bit 10_03 bit 10_04 bit 10_05 -bit 10_06 bit 10_07 -bit 10_08 bit 10_09 bit 10_10 -bit 10_11 -bit 10_12 bit 10_13 -bit 10_14 bit 10_15 bit 10_16 bit 10_17 bit 10_18 -bit 10_19 -bit 10_20 -bit 10_21 -bit 10_22 bit 10_23 -bit 10_24 -bit 10_25 bit 10_26 -bit 10_27 -bit 10_28 -bit 10_30 +bit 10_29 bit 10_31 bit 10_32 bit 10_33 bit 10_34 -bit 10_35 -bit 10_36 bit 10_37 bit 10_39 bit 10_41 bit 10_42 -bit 10_45 -bit 10_46 bit 10_47 bit 10_48 bit 10_49 bit 10_50 -bit 10_51 -bit 10_52 -bit 10_54 bit 10_55 -bit 10_56 bit 10_57 bit 10_58 -bit 10_59 -bit 10_61 -bit 10_62 bit 10_63 -bit 10_64 bit 10_65 bit 10_66 -bit 10_67 -bit 10_68 bit 10_69 -bit 10_70 bit 10_71 bit 10_72 bit 10_73 bit 10_74 -bit 10_75 -bit 10_76 bit 10_77 -bit 10_78 bit 10_79 bit 10_80 bit 10_81 bit 10_82 -bit 10_83 -bit 10_84 -bit 10_86 bit 10_87 bit 10_88 bit 10_90 -bit 10_91 -bit 10_92 bit 10_93 -bit 10_94 bit 10_95 bit 10_96 -bit 10_97 bit 10_98 bit 10_99 -bit 10_101 bit 10_103 bit 10_104 -bit 10_105 bit 10_106 -bit 10_110 +bit 10_109 bit 10_111 -bit 10_112 bit 10_113 bit 10_114 -bit 10_115 bit 10_117 -bit 10_118 bit 10_119 bit 10_120 bit 10_121 @@ -742,65 +342,49 @@ bit 11_05 bit 11_07 bit 11_09 -bit 11_10 -bit 11_11 bit 11_12 bit 11_13 bit 11_15 -bit 11_16 bit 11_17 -bit 11_18 bit 11_19 bit 11_22 bit 11_23 bit 11_25 -bit 11_26 bit 11_27 -bit 11_28 bit 11_29 bit 11_30 bit 11_31 -bit 11_32 bit 11_33 -bit 11_34 bit 11_35 -bit 11_36 bit 11_39 bit 11_41 bit 11_43 -bit 11_44 bit 11_45 bit 11_46 bit 11_47 bit 11_48 bit 11_49 -bit 11_50 bit 11_51 bit 11_52 bit 11_55 bit 11_57 -bit 11_58 bit 11_59 -bit 11_60 bit 11_61 bit 11_63 bit 11_64 bit 11_65 -bit 11_66 bit 11_67 +bit 11_68 bit 11_69 bit 11_71 bit 11_73 -bit 11_74 bit 11_75 bit 11_77 bit 11_79 bit 11_81 -bit 11_82 bit 11_83 bit 11_87 bit 11_89 -bit 11_90 bit 11_91 bit 11_93 bit 11_95 @@ -808,22 +392,19 @@ bit 11_97 bit 11_98 bit 11_99 +bit 11_100 bit 11_101 bit 11_103 bit 11_105 bit 11_107 -bit 11_108 bit 11_109 bit 11_111 bit 11_112 bit 11_113 -bit 11_114 bit 11_115 bit 11_116 -bit 11_117 bit 11_119 bit 11_121 -bit 11_122 bit 11_123 bit 11_125 bit 11_127 @@ -833,82 +414,62 @@ bit 12_03 bit 12_04 bit 12_05 -bit 12_06 bit 12_07 -bit 12_08 bit 12_09 bit 12_10 -bit 12_11 bit 12_13 -bit 12_14 bit 12_15 bit 12_16 bit 12_17 -bit 12_18 bit 12_19 bit 12_21 -bit 12_22 bit 12_23 bit 12_25 bit 12_26 bit 12_27 bit 12_28 bit 12_29 -bit 12_30 bit 12_31 -bit 12_32 bit 12_33 bit 12_34 bit 12_35 bit 12_37 -bit 12_38 bit 12_39 bit 12_41 bit 12_42 bit 12_43 -bit 12_44 bit 12_45 -bit 12_46 bit 12_47 bit 12_48 bit 12_49 bit 12_50 bit 12_51 -bit 12_54 +bit 12_53 bit 12_55 -bit 12_56 bit 12_57 bit 12_58 bit 12_59 bit 12_60 bit 12_61 -bit 12_62 bit 12_63 -bit 12_64 bit 12_65 bit 12_66 bit 12_67 bit 12_69 -bit 12_70 bit 12_71 bit 12_73 -bit 12_74 bit 12_75 +bit 12_76 bit 12_77 -bit 12_78 bit 12_79 -bit 12_80 bit 12_81 bit 12_82 bit 12_83 -bit 12_84 -bit 12_86 bit 12_87 bit 12_89 bit 12_90 bit 12_91 bit 12_93 -bit 12_94 bit 12_95 bit 12_96 bit 12_97 @@ -920,16 +481,12 @@ bit 12_106 bit 12_107 bit 12_109 -bit 12_110 bit 12_111 -bit 12_112 bit 12_113 bit 12_114 bit 12_115 bit 12_117 -bit 12_118 bit 12_119 -bit 12_120 bit 12_121 bit 12_122 bit 12_123 @@ -938,14 +495,10 @@ bit 13_00 bit 13_01 bit 13_02 -bit 13_03 bit 13_04 bit 13_05 -bit 13_06 bit 13_07 -bit 13_08 bit 13_09 -bit 13_10 bit 13_11 bit 13_12 bit 13_13 @@ -958,9 +511,7 @@ bit 13_20 bit 13_22 bit 13_23 -bit 13_24 bit 13_25 -bit 13_26 bit 13_27 bit 13_28 bit 13_30 @@ -971,7 +522,6 @@ bit 13_35 bit 13_36 bit 13_37 -bit 13_38 bit 13_39 bit 13_41 bit 13_42 @@ -982,8 +532,6 @@ bit 13_49 bit 13_50 bit 13_52 -bit 13_53 -bit 13_54 bit 13_55 bit 13_57 bit 13_58 @@ -995,8 +543,6 @@ bit 13_66 bit 13_67 bit 13_68 -bit 13_69 -bit 13_70 bit 13_71 bit 13_72 bit 13_73 @@ -1004,19 +550,15 @@ bit 13_75 bit 13_76 bit 13_77 -bit 13_78 bit 13_79 bit 13_80 bit 13_81 bit 13_82 bit 13_83 -bit 13_84 -bit 13_86 bit 13_87 bit 13_88 bit 13_89 bit 13_90 -bit 13_91 bit 13_92 bit 13_93 bit 13_94 @@ -1042,79 +584,40 @@ bit 13_114 bit 13_116 bit 13_117 -bit 13_118 bit 13_119 bit 13_120 bit 13_121 -bit 13_122 bit 13_124 bit 13_125 bit 13_127 bit 14_00 -bit 14_01 bit 14_02 -bit 14_03 bit 14_04 -bit 14_05 -bit 14_06 -bit 14_07 -bit 14_09 bit 14_10 -bit 14_11 bit 14_12 -bit 14_13 -bit 14_14 -bit 14_15 bit 14_16 bit 14_18 -bit 14_19 bit 14_20 -bit 14_21 -bit 14_22 -bit 14_23 bit 14_26 -bit 14_27 -bit 14_28 -bit 14_29 -bit 14_31 bit 14_32 bit 14_34 bit 14_36 bit 14_42 -bit 14_46 bit 14_48 bit 14_50 bit 14_52 -bit 14_54 bit 14_58 -bit 14_62 +bit 14_60 bit 14_64 -bit 14_65 bit 14_66 -bit 14_67 bit 14_68 -bit 14_69 -bit 14_70 -bit 14_71 -bit 14_73 bit 14_74 -bit 14_75 bit 14_76 -bit 14_77 -bit 14_78 -bit 14_79 bit 14_80 bit 14_82 -bit 14_83 bit 14_84 -bit 14_85 -bit 14_87 -bit 14_89 bit 14_90 -bit 14_91 bit 14_92 -bit 14_93 -bit 14_95 bit 14_96 bit 14_98 bit 14_100 @@ -1123,40 +626,22 @@ bit 14_112 bit 14_114 bit 14_116 +bit 14_120 bit 14_122 bit 14_124 -bit 14_126 -bit 15_00 bit 15_01 -bit 15_02 bit 15_03 -bit 15_04 bit 15_05 -bit 15_06 bit 15_07 -bit 15_08 bit 15_09 -bit 15_10 -bit 15_11 -bit 15_12 bit 15_13 -bit 15_14 bit 15_15 -bit 15_16 bit 15_17 -bit 15_18 bit 15_19 -bit 15_20 -bit 15_21 -bit 15_22 bit 15_23 -bit 15_24 bit 15_25 -bit 15_26 bit 15_27 -bit 15_28 bit 15_29 -bit 15_30 bit 15_31 bit 15_33 bit 15_35 @@ -1173,36 +658,21 @@ bit 15_59 bit 15_61 bit 15_63 -bit 15_64 bit 15_65 -bit 15_66 bit 15_67 -bit 15_68 bit 15_69 -bit 15_70 bit 15_71 -bit 15_72 bit 15_73 -bit 15_74 bit 15_75 -bit 15_76 bit 15_77 -bit 15_78 bit 15_79 -bit 15_80 bit 15_81 bit 15_83 -bit 15_84 bit 15_85 -bit 15_86 bit 15_87 -bit 15_88 bit 15_89 -bit 15_90 bit 15_91 -bit 15_92 bit 15_93 -bit 15_94 bit 15_95 bit 15_97 bit 15_99 @@ -1232,7 +702,6 @@ bit 16_30 bit 16_31 bit 16_32 -bit 16_35 bit 16_38 bit 16_39 bit 16_40 @@ -1242,7 +711,6 @@ bit 16_46 bit 16_47 bit 16_48 -bit 16_51 bit 16_54 bit 16_56 bit 16_57 @@ -1262,7 +730,6 @@ bit 16_94 bit 16_95 bit 16_96 -bit 16_99 bit 16_102 bit 16_103 bit 16_104 @@ -1272,7 +739,6 @@ bit 16_110 bit 16_111 bit 16_112 -bit 16_115 bit 16_118 bit 16_120 bit 16_121 @@ -1292,7 +758,6 @@ bit 17_30 bit 17_31 bit 17_32 -bit 17_35 bit 17_38 bit 17_39 bit 17_40 @@ -1302,7 +767,6 @@ bit 17_46 bit 17_47 bit 17_48 -bit 17_51 bit 17_54 bit 17_55 bit 17_56 @@ -1315,14 +779,12 @@ bit 17_71 bit 17_73 bit 17_79 -bit 17_80 bit 17_85 bit 17_86 bit 17_87 bit 17_88 bit 17_94 bit 17_95 -bit 17_99 bit 17_102 bit 17_103 bit 17_104 @@ -1332,9 +794,7 @@ bit 17_110 bit 17_111 bit 17_112 -bit 17_115 bit 17_118 -bit 17_119 bit 17_120 bit 17_121 bit 17_122 @@ -1352,8 +812,6 @@ bit 18_25 bit 18_30 bit 18_31 -bit 18_33 -bit 18_34 bit 18_38 bit 18_39 bit 18_41 @@ -1363,7 +821,6 @@ bit 18_46 bit 18_47 bit 18_49 -bit 18_50 bit 18_54 bit 18_55 bit 18_56 @@ -1380,10 +837,10 @@ bit 18_84 bit 18_86 bit 18_87 +bit 18_89 bit 18_94 bit 18_95 bit 18_97 -bit 18_98 bit 18_102 bit 18_103 bit 18_105 @@ -1393,7 +850,6 @@ bit 18_110 bit 18_111 bit 18_113 -bit 18_114 bit 18_119 bit 18_120 bit 18_121 @@ -1401,9 +857,9 @@ bit 18_125 bit 18_127 bit 19_03 +bit 19_06 bit 19_07 bit 19_08 -bit 19_09 bit 19_14 bit 19_17 bit 19_20 @@ -1413,7 +869,6 @@ bit 19_30 bit 19_31 bit 19_33 -bit 19_34 bit 19_38 bit 19_39 bit 19_41 @@ -1423,7 +878,6 @@ bit 19_46 bit 19_47 bit 19_49 -bit 19_50 bit 19_54 bit 19_55 bit 19_56 @@ -1445,7 +899,6 @@ bit 19_94 bit 19_95 bit 19_97 -bit 19_98 bit 19_102 bit 19_103 bit 19_105 @@ -1455,19 +908,15 @@ bit 19_110 bit 19_111 bit 19_113 -bit 19_114 bit 19_119 bit 19_120 bit 19_121 bit 19_123 bit 19_125 bit 19_127 -bit 20_01 bit 20_02 -bit 20_05 bit 20_06 bit 20_09 -bit 20_13 bit 20_21 bit 20_22 bit 20_30 @@ -1476,20 +925,14 @@ bit 20_43 bit 20_44 bit 20_46 -bit 20_48 bit 20_54 -bit 20_55 bit 20_57 bit 20_58 bit 20_60 bit 20_62 -bit 20_65 bit 20_66 -bit 20_69 bit 20_70 bit 20_73 -bit 20_77 -bit 20_84 bit 20_85 bit 20_86 bit 20_94 @@ -1498,8 +941,8 @@ bit 20_107 bit 20_108 bit 20_110 +bit 20_112 bit 20_118 -bit 20_119 bit 20_121 bit 20_122 bit 20_124 @@ -1507,39 +950,30 @@ bit 21_02 bit 21_06 bit 21_09 -bit 21_20 bit 21_21 bit 21_22 bit 21_30 -bit 21_34 -bit 21_35 bit 21_38 bit 21_42 bit 21_43 bit 21_44 bit 21_46 -bit 21_51 -bit 21_52 bit 21_54 bit 21_57 bit 21_58 bit 21_60 bit 21_62 bit 21_66 -bit 21_69 bit 21_70 bit 21_73 -bit 21_84 bit 21_85 bit 21_86 bit 21_94 -bit 21_98 bit 21_102 bit 21_106 bit 21_107 bit 21_108 bit 21_110 -bit 21_116 bit 21_118 bit 21_121 bit 21_122 @@ -1558,17 +992,14 @@ bit 22_30 bit 22_31 bit 22_32 -bit 22_35 bit 22_38 bit 22_39 -bit 22_40 bit 22_42 bit 22_43 bit 22_44 bit 22_46 bit 22_47 bit 22_48 -bit 22_51 bit 22_54 bit 22_55 bit 22_56 @@ -1588,10 +1019,7 @@ bit 22_88 bit 22_94 bit 22_95 -bit 22_96 -bit 22_99 bit 22_102 -bit 22_103 bit 22_104 bit 22_106 bit 22_107 @@ -1599,7 +1027,6 @@ bit 22_110 bit 22_111 bit 22_112 -bit 22_115 bit 22_118 bit 22_120 bit 22_121 @@ -1619,7 +1046,6 @@ bit 23_30 bit 23_31 bit 23_32 -bit 23_35 bit 23_38 bit 23_39 bit 23_40 @@ -1629,7 +1055,6 @@ bit 23_46 bit 23_47 bit 23_48 -bit 23_51 bit 23_54 bit 23_56 bit 23_57 @@ -1648,7 +1073,6 @@ bit 23_94 bit 23_95 bit 23_96 -bit 23_99 bit 23_102 bit 23_103 bit 23_104 @@ -1658,20 +1082,16 @@ bit 23_110 bit 23_111 bit 23_112 -bit 23_115 bit 23_118 bit 23_120 bit 23_121 bit 23_122 bit 23_124 bit 23_126 -bit 24_01 bit 24_02 -bit 24_05 bit 24_06 bit 24_07 bit 24_09 -bit 24_13 bit 24_15 bit 24_16 bit 24_21 @@ -1681,7 +1101,6 @@ bit 24_30 bit 24_31 bit 24_32 -bit 24_35 bit 24_38 bit 24_39 bit 24_40 @@ -1691,7 +1110,6 @@ bit 24_46 bit 24_47 bit 24_48 -bit 24_51 bit 24_54 bit 24_55 bit 24_56 @@ -1699,16 +1117,12 @@ bit 24_58 bit 24_60 bit 24_62 -bit 24_65 bit 24_66 -bit 24_69 bit 24_70 bit 24_71 bit 24_73 -bit 24_77 bit 24_79 bit 24_80 -bit 24_84 bit 24_85 bit 24_86 bit 24_87 @@ -1716,7 +1130,6 @@ bit 24_94 bit 24_95 bit 24_96 -bit 24_99 bit 24_102 bit 24_103 bit 24_104 @@ -1726,9 +1139,7 @@ bit 24_110 bit 24_111 bit 24_112 -bit 24_115 bit 24_118 -bit 24_119 bit 24_120 bit 24_121 bit 24_122 @@ -1851,12 +1262,18 @@ bit 28_64 bit 28_67 bit 28_72 +bit 28_75 bit 28_76 bit 28_77 +bit 28_79 +bit 28_81 bit 28_83 bit 28_86 +bit 28_89 bit 28_93 bit 28_94 +bit 28_95 +bit 28_97 bit 28_110 bit 28_111 bit 28_116 @@ -1871,12 +1288,18 @@ bit 29_11 bit 29_16 bit 29_17 +bit 29_30 +bit 29_32 bit 29_33 bit 29_34 +bit 29_38 bit 29_41 bit 29_44 +bit 29_46 +bit 29_48 bit 29_50 bit 29_51 +bit 29_52 bit 29_55 bit 29_60 bit 29_63 @@ -1909,13 +1332,19 @@ bit 30_25 bit 30_27 bit 30_29 +bit 30_30 +bit 30_32 bit 30_34 bit 30_35 bit 30_37 +bit 30_38 bit 30_41 bit 30_44 +bit 30_46 +bit 30_48 bit 30_50 bit 30_51 +bit 30_52 bit 30_60 bit 30_67 bit 30_71 @@ -1950,13 +1379,19 @@ bit 31_56 bit 31_60 bit 31_67 +bit 31_75 bit 31_76 bit 31_77 +bit 31_79 +bit 31_81 bit 31_83 bit 31_86 +bit 31_89 bit 31_90 bit 31_92 bit 31_93 +bit 31_95 +bit 31_97 bit 31_98 bit 31_100 bit 31_102
diff --git a/artix7/mask_riob33.db b/artix7/mask_riob33.db index dd88e69..2e9d88a 100644 --- a/artix7/mask_riob33.db +++ b/artix7/mask_riob33.db
@@ -1,6 +1,3 @@ -bit 00_02 -bit 00_07 -bit 00_09 bit 00_10 bit 00_11 bit 00_14 @@ -10,16 +7,6 @@ bit 00_35 bit 00_38 bit 00_39 -bit 00_42 -bit 00_43 -bit 00_45 -bit 00_50 -bit 00_51 -bit 00_54 -bit 00_58 -bit 00_66 -bit 00_71 -bit 00_73 bit 00_74 bit 00_75 bit 00_78 @@ -29,399 +16,103 @@ bit 00_99 bit 00_102 bit 00_103 -bit 00_106 -bit 00_107 -bit 00_114 -bit 01_00 -bit 01_01 -bit 01_02 -bit 01_04 -bit 01_05 -bit 01_06 bit 01_09 bit 01_10 bit 01_13 bit 01_14 -bit 01_32 bit 01_33 -bit 01_36 bit 01_37 bit 01_38 bit 01_40 -bit 01_41 -bit 01_44 -bit 01_50 -bit 01_58 -bit 01_64 -bit 01_65 -bit 01_66 -bit 01_68 -bit 01_69 -bit 01_70 bit 01_73 bit 01_74 bit 01_77 bit 01_78 -bit 01_96 bit 01_97 -bit 01_100 bit 01_101 bit 01_102 bit 01_104 -bit 01_105 -bit 01_114 -bit 02_05 -bit 02_06 bit 02_07 -bit 02_09 -bit 02_10 -bit 02_11 -bit 02_13 -bit 02_14 -bit 02_15 -bit 02_18 -bit 02_22 -bit 02_23 -bit 02_30 -bit 02_31 -bit 02_34 -bit 02_35 -bit 02_38 -bit 02_39 -bit 02_46 -bit 02_47 -bit 02_50 -bit 02_51 -bit 02_54 -bit 02_55 -bit 02_62 -bit 02_66 -bit 02_67 -bit 02_69 -bit 02_70 -bit 02_71 -bit 02_73 -bit 02_75 -bit 02_77 -bit 02_78 -bit 02_79 -bit 02_82 -bit 02_86 -bit 02_87 -bit 02_94 -bit 02_95 -bit 02_102 -bit 02_103 -bit 02_114 -bit 02_117 -bit 02_118 -bit 02_119 -bit 02_126 -bit 02_127 -bit 03_02 -bit 03_05 -bit 03_06 -bit 03_10 -bit 03_13 -bit 03_14 -bit 03_21 -bit 03_29 -bit 03_36 -bit 03_37 -bit 03_38 -bit 03_45 -bit 03_52 -bit 03_53 -bit 03_54 -bit 03_60 -bit 03_61 -bit 03_62 -bit 03_66 -bit 03_68 -bit 03_69 -bit 03_70 -bit 03_74 -bit 03_77 -bit 03_78 -bit 03_85 -bit 03_86 -bit 03_93 -bit 03_101 -bit 03_102 bit 03_116 -bit 03_117 -bit 03_118 -bit 03_126 bit 04_04 -bit 04_05 -bit 04_06 -bit 04_07 -bit 04_10 -bit 04_11 -bit 04_12 -bit 04_14 -bit 04_15 -bit 04_19 -bit 04_20 -bit 04_21 -bit 04_22 -bit 04_23 -bit 04_27 -bit 04_28 -bit 04_30 -bit 04_31 -bit 04_35 -bit 04_36 -bit 04_37 -bit 04_39 -bit 04_44 -bit 04_47 -bit 04_51 -bit 04_52 -bit 04_53 -bit 04_55 -bit 04_63 -bit 04_66 -bit 04_68 -bit 04_69 -bit 04_70 -bit 04_74 -bit 04_75 -bit 04_76 -bit 04_78 -bit 04_79 -bit 04_83 -bit 04_84 -bit 04_85 -bit 04_86 -bit 04_87 -bit 04_94 -bit 04_95 -bit 04_100 -bit 04_101 -bit 04_103 -bit 04_115 -bit 04_116 -bit 04_117 -bit 04_119 -bit 04_124 -bit 05_01 -bit 05_02 -bit 05_05 -bit 05_06 -bit 05_09 -bit 05_10 -bit 05_12 -bit 05_13 -bit 05_14 -bit 05_17 -bit 05_18 -bit 05_22 -bit 05_25 -bit 05_26 -bit 05_28 -bit 05_33 -bit 05_34 -bit 05_36 -bit 05_37 -bit 05_38 -bit 05_44 -bit 05_46 -bit 05_49 -bit 05_50 -bit 05_52 -bit 05_53 -bit 05_58 -bit 05_60 -bit 05_63 -bit 05_65 -bit 05_66 -bit 05_69 bit 05_70 -bit 05_73 -bit 05_74 -bit 05_76 -bit 05_77 -bit 05_81 -bit 05_82 -bit 05_86 -bit 05_89 -bit 05_94 -bit 05_98 -bit 05_101 -bit 05_102 -bit 05_113 -bit 05_114 -bit 05_116 -bit 05_117 bit 05_119 bit 06_01 -bit 06_02 bit 06_03 -bit 06_04 -bit 06_05 -bit 06_06 -bit 06_10 bit 06_11 -bit 06_12 -bit 06_13 -bit 06_14 -bit 06_15 bit 06_17 -bit 06_20 -bit 06_22 -bit 06_24 -bit 06_27 -bit 06_28 bit 06_29 -bit 06_30 -bit 06_31 bit 06_33 bit 06_35 -bit 06_36 -bit 06_37 -bit 06_39 bit 06_43 -bit 06_46 bit 06_49 bit 06_51 -bit 06_52 -bit 06_53 -bit 06_55 bit 06_59 bit 06_61 -bit 06_64 bit 06_65 -bit 06_66 bit 06_67 -bit 06_68 -bit 06_69 -bit 06_70 -bit 06_71 -bit 06_72 -bit 06_74 -bit 06_75 -bit 06_76 -bit 06_77 -bit 06_78 -bit 06_79 -bit 06_80 bit 06_81 bit 06_83 -bit 06_84 -bit 06_85 -bit 06_86 bit 06_91 -bit 06_92 -bit 06_93 -bit 06_94 bit 06_97 bit 06_99 -bit 06_100 -bit 06_101 bit 06_103 bit 06_107 bit 06_113 bit 06_115 -bit 06_116 -bit 06_117 -bit 06_119 bit 06_121 bit 06_123 bit 07_00 bit 07_02 -bit 07_03 bit 07_04 -bit 07_05 bit 07_06 -bit 07_07 bit 07_08 -bit 07_10 -bit 07_11 bit 07_12 -bit 07_13 bit 07_14 -bit 07_15 bit 07_16 -bit 07_19 bit 07_20 bit 07_22 -bit 07_23 bit 07_24 -bit 07_25 -bit 07_26 -bit 07_27 bit 07_28 bit 07_30 -bit 07_31 bit 07_32 -bit 07_34 -bit 07_35 bit 07_36 -bit 07_37 bit 07_38 -bit 07_39 bit 07_40 bit 07_44 bit 07_46 -bit 07_47 bit 07_48 -bit 07_50 -bit 07_51 -bit 07_53 +bit 07_52 bit 07_54 -bit 07_55 bit 07_56 bit 07_58 -bit 07_59 bit 07_60 bit 07_62 -bit 07_63 bit 07_64 -bit 07_65 -bit 07_67 +bit 07_66 bit 07_68 -bit 07_69 bit 07_70 bit 07_71 bit 07_72 -bit 07_74 -bit 07_75 bit 07_76 -bit 07_77 bit 07_78 -bit 07_79 bit 07_80 -bit 07_81 -bit 07_82 -bit 07_83 bit 07_84 bit 07_86 -bit 07_87 bit 07_88 -bit 07_91 bit 07_92 bit 07_94 -bit 07_95 -bit 07_96 bit 07_98 -bit 07_99 bit 07_100 bit 07_102 -bit 07_103 bit 07_104 bit 07_108 bit 07_110 bit 07_112 -bit 07_114 -bit 07_115 -bit 07_117 bit 07_118 -bit 07_119 bit 07_120 bit 07_124 bit 07_126 -bit 07_127 bit 08_00 bit 08_01 bit 08_02 @@ -433,23 +124,18 @@ bit 08_08 bit 08_09 bit 08_10 -bit 08_11 -bit 08_12 -bit 08_13 bit 08_14 bit 08_15 bit 08_16 bit 08_17 bit 08_18 -bit 08_20 -bit 08_21 +bit 08_19 bit 08_22 bit 08_23 bit 08_24 bit 08_25 bit 08_26 bit 08_27 -bit 08_28 bit 08_30 bit 08_31 bit 08_32 @@ -468,46 +154,34 @@ bit 08_48 bit 08_49 bit 08_50 -bit 08_51 -bit 08_52 bit 08_54 bit 08_55 bit 08_56 bit 08_57 bit 08_58 bit 08_59 -bit 08_61 bit 08_62 bit 08_63 bit 08_64 bit 08_65 bit 08_66 bit 08_67 -bit 08_68 -bit 08_69 -bit 08_70 bit 08_71 bit 08_72 bit 08_73 bit 08_74 bit 08_75 -bit 08_76 -bit 08_77 bit 08_78 bit 08_79 bit 08_80 bit 08_81 bit 08_82 bit 08_83 -bit 08_84 -bit 08_86 bit 08_87 bit 08_88 bit 08_89 bit 08_90 bit 08_91 -bit 08_92 -bit 08_93 bit 08_94 bit 08_95 bit 08_96 @@ -533,46 +207,30 @@ bit 08_120 bit 08_121 bit 08_122 -bit 08_124 +bit 08_125 bit 08_126 bit 08_127 -bit 09_00 -bit 09_01 bit 09_02 bit 09_03 bit 09_04 bit 09_05 -bit 09_07 -bit 09_08 -bit 09_09 -bit 09_10 bit 09_11 bit 09_12 bit 09_13 bit 09_14 -bit 09_15 bit 09_16 -bit 09_18 bit 09_19 bit 09_20 -bit 09_23 -bit 09_24 -bit 09_26 +bit 09_21 bit 09_27 bit 09_28 bit 09_29 -bit 09_30 -bit 09_31 -bit 09_32 -bit 09_33 bit 09_34 bit 09_35 bit 09_36 bit 09_43 bit 09_44 bit 09_45 -bit 09_46 -bit 09_47 bit 09_48 bit 09_49 bit 09_50 @@ -580,27 +238,17 @@ bit 09_52 bit 09_58 bit 09_59 +bit 09_60 bit 09_61 -bit 09_63 -bit 09_64 -bit 09_65 bit 09_66 bit 09_67 bit 09_68 -bit 09_69 -bit 09_71 -bit 09_72 -bit 09_73 bit 09_75 bit 09_76 bit 09_77 -bit 09_79 bit 09_82 bit 09_83 bit 09_84 -bit 09_85 -bit 09_87 -bit 09_90 bit 09_91 bit 09_92 bit 09_93 @@ -614,9 +262,6 @@ bit 09_108 bit 09_109 bit 09_110 -bit 09_111 -bit 09_112 -bit 09_113 bit 09_114 bit 09_115 bit 09_116 @@ -624,111 +269,66 @@ bit 09_123 bit 09_124 bit 09_125 -bit 09_127 bit 10_00 bit 10_01 bit 10_02 -bit 10_03 bit 10_04 bit 10_05 -bit 10_06 bit 10_07 -bit 10_08 bit 10_09 bit 10_10 -bit 10_11 -bit 10_12 bit 10_13 -bit 10_14 bit 10_15 bit 10_16 bit 10_17 bit 10_18 -bit 10_19 -bit 10_20 -bit 10_21 -bit 10_22 bit 10_23 -bit 10_24 -bit 10_25 bit 10_26 -bit 10_27 -bit 10_28 -bit 10_30 +bit 10_29 bit 10_31 bit 10_32 bit 10_33 bit 10_34 -bit 10_35 -bit 10_36 bit 10_37 bit 10_39 bit 10_41 bit 10_42 -bit 10_45 -bit 10_46 bit 10_47 bit 10_48 bit 10_49 bit 10_50 -bit 10_51 -bit 10_52 -bit 10_54 bit 10_55 -bit 10_56 bit 10_57 bit 10_58 -bit 10_59 -bit 10_61 -bit 10_62 bit 10_63 -bit 10_64 bit 10_65 bit 10_66 -bit 10_67 -bit 10_68 bit 10_69 -bit 10_70 bit 10_71 bit 10_72 bit 10_73 bit 10_74 -bit 10_75 -bit 10_76 bit 10_77 -bit 10_78 bit 10_79 bit 10_80 bit 10_81 bit 10_82 -bit 10_83 -bit 10_84 -bit 10_86 bit 10_87 bit 10_88 bit 10_90 -bit 10_91 -bit 10_92 bit 10_93 -bit 10_94 bit 10_95 bit 10_96 -bit 10_97 bit 10_98 bit 10_99 -bit 10_101 bit 10_103 bit 10_104 -bit 10_105 bit 10_106 -bit 10_110 +bit 10_109 bit 10_111 -bit 10_112 bit 10_113 bit 10_114 -bit 10_115 bit 10_117 -bit 10_118 bit 10_119 bit 10_120 bit 10_121 @@ -742,65 +342,49 @@ bit 11_05 bit 11_07 bit 11_09 -bit 11_10 -bit 11_11 bit 11_12 bit 11_13 bit 11_15 -bit 11_16 bit 11_17 -bit 11_18 bit 11_19 bit 11_22 bit 11_23 bit 11_25 -bit 11_26 bit 11_27 -bit 11_28 bit 11_29 bit 11_30 bit 11_31 -bit 11_32 bit 11_33 -bit 11_34 bit 11_35 -bit 11_36 bit 11_39 bit 11_41 bit 11_43 -bit 11_44 bit 11_45 bit 11_46 bit 11_47 bit 11_48 bit 11_49 -bit 11_50 bit 11_51 bit 11_52 bit 11_55 bit 11_57 -bit 11_58 bit 11_59 -bit 11_60 bit 11_61 bit 11_63 bit 11_64 bit 11_65 -bit 11_66 bit 11_67 +bit 11_68 bit 11_69 bit 11_71 bit 11_73 -bit 11_74 bit 11_75 bit 11_77 bit 11_79 bit 11_81 -bit 11_82 bit 11_83 bit 11_87 bit 11_89 -bit 11_90 bit 11_91 bit 11_93 bit 11_95 @@ -808,22 +392,19 @@ bit 11_97 bit 11_98 bit 11_99 +bit 11_100 bit 11_101 bit 11_103 bit 11_105 bit 11_107 -bit 11_108 bit 11_109 bit 11_111 bit 11_112 bit 11_113 -bit 11_114 bit 11_115 bit 11_116 -bit 11_117 bit 11_119 bit 11_121 -bit 11_122 bit 11_123 bit 11_125 bit 11_127 @@ -833,82 +414,62 @@ bit 12_03 bit 12_04 bit 12_05 -bit 12_06 bit 12_07 -bit 12_08 bit 12_09 bit 12_10 -bit 12_11 bit 12_13 -bit 12_14 bit 12_15 bit 12_16 bit 12_17 -bit 12_18 bit 12_19 bit 12_21 -bit 12_22 bit 12_23 bit 12_25 bit 12_26 bit 12_27 bit 12_28 bit 12_29 -bit 12_30 bit 12_31 -bit 12_32 bit 12_33 bit 12_34 bit 12_35 bit 12_37 -bit 12_38 bit 12_39 bit 12_41 bit 12_42 bit 12_43 -bit 12_44 bit 12_45 -bit 12_46 bit 12_47 bit 12_48 bit 12_49 bit 12_50 bit 12_51 -bit 12_54 +bit 12_53 bit 12_55 -bit 12_56 bit 12_57 bit 12_58 bit 12_59 bit 12_60 bit 12_61 -bit 12_62 bit 12_63 -bit 12_64 bit 12_65 bit 12_66 bit 12_67 bit 12_69 -bit 12_70 bit 12_71 bit 12_73 -bit 12_74 bit 12_75 +bit 12_76 bit 12_77 -bit 12_78 bit 12_79 -bit 12_80 bit 12_81 bit 12_82 bit 12_83 -bit 12_84 -bit 12_86 bit 12_87 bit 12_89 bit 12_90 bit 12_91 bit 12_93 -bit 12_94 bit 12_95 bit 12_96 bit 12_97 @@ -920,16 +481,12 @@ bit 12_106 bit 12_107 bit 12_109 -bit 12_110 bit 12_111 -bit 12_112 bit 12_113 bit 12_114 bit 12_115 bit 12_117 -bit 12_118 bit 12_119 -bit 12_120 bit 12_121 bit 12_122 bit 12_123 @@ -938,14 +495,10 @@ bit 13_00 bit 13_01 bit 13_02 -bit 13_03 bit 13_04 bit 13_05 -bit 13_06 bit 13_07 -bit 13_08 bit 13_09 -bit 13_10 bit 13_11 bit 13_12 bit 13_13 @@ -958,9 +511,7 @@ bit 13_20 bit 13_22 bit 13_23 -bit 13_24 bit 13_25 -bit 13_26 bit 13_27 bit 13_28 bit 13_30 @@ -971,7 +522,6 @@ bit 13_35 bit 13_36 bit 13_37 -bit 13_38 bit 13_39 bit 13_41 bit 13_42 @@ -982,8 +532,6 @@ bit 13_49 bit 13_50 bit 13_52 -bit 13_53 -bit 13_54 bit 13_55 bit 13_57 bit 13_58 @@ -995,8 +543,6 @@ bit 13_66 bit 13_67 bit 13_68 -bit 13_69 -bit 13_70 bit 13_71 bit 13_72 bit 13_73 @@ -1004,19 +550,15 @@ bit 13_75 bit 13_76 bit 13_77 -bit 13_78 bit 13_79 bit 13_80 bit 13_81 bit 13_82 bit 13_83 -bit 13_84 -bit 13_86 bit 13_87 bit 13_88 bit 13_89 bit 13_90 -bit 13_91 bit 13_92 bit 13_93 bit 13_94 @@ -1042,79 +584,40 @@ bit 13_114 bit 13_116 bit 13_117 -bit 13_118 bit 13_119 bit 13_120 bit 13_121 -bit 13_122 bit 13_124 bit 13_125 bit 13_127 bit 14_00 -bit 14_01 bit 14_02 -bit 14_03 bit 14_04 -bit 14_05 -bit 14_06 -bit 14_07 -bit 14_09 bit 14_10 -bit 14_11 bit 14_12 -bit 14_13 -bit 14_14 -bit 14_15 bit 14_16 bit 14_18 -bit 14_19 bit 14_20 -bit 14_21 -bit 14_22 -bit 14_23 bit 14_26 -bit 14_27 -bit 14_28 -bit 14_29 -bit 14_31 bit 14_32 bit 14_34 bit 14_36 bit 14_42 -bit 14_46 bit 14_48 bit 14_50 bit 14_52 -bit 14_54 bit 14_58 -bit 14_62 +bit 14_60 bit 14_64 -bit 14_65 bit 14_66 -bit 14_67 bit 14_68 -bit 14_69 -bit 14_70 -bit 14_71 -bit 14_73 bit 14_74 -bit 14_75 bit 14_76 -bit 14_77 -bit 14_78 -bit 14_79 bit 14_80 bit 14_82 -bit 14_83 bit 14_84 -bit 14_85 -bit 14_87 -bit 14_89 bit 14_90 -bit 14_91 bit 14_92 -bit 14_93 -bit 14_95 bit 14_96 bit 14_98 bit 14_100 @@ -1123,40 +626,22 @@ bit 14_112 bit 14_114 bit 14_116 +bit 14_120 bit 14_122 bit 14_124 -bit 14_126 -bit 15_00 bit 15_01 -bit 15_02 bit 15_03 -bit 15_04 bit 15_05 -bit 15_06 bit 15_07 -bit 15_08 bit 15_09 -bit 15_10 -bit 15_11 -bit 15_12 bit 15_13 -bit 15_14 bit 15_15 -bit 15_16 bit 15_17 -bit 15_18 bit 15_19 -bit 15_20 -bit 15_21 -bit 15_22 bit 15_23 -bit 15_24 bit 15_25 -bit 15_26 bit 15_27 -bit 15_28 bit 15_29 -bit 15_30 bit 15_31 bit 15_33 bit 15_35 @@ -1173,36 +658,21 @@ bit 15_59 bit 15_61 bit 15_63 -bit 15_64 bit 15_65 -bit 15_66 bit 15_67 -bit 15_68 bit 15_69 -bit 15_70 bit 15_71 -bit 15_72 bit 15_73 -bit 15_74 bit 15_75 -bit 15_76 bit 15_77 -bit 15_78 bit 15_79 -bit 15_80 bit 15_81 bit 15_83 -bit 15_84 bit 15_85 -bit 15_86 bit 15_87 -bit 15_88 bit 15_89 -bit 15_90 bit 15_91 -bit 15_92 bit 15_93 -bit 15_94 bit 15_95 bit 15_97 bit 15_99 @@ -1232,7 +702,6 @@ bit 16_30 bit 16_31 bit 16_32 -bit 16_35 bit 16_38 bit 16_39 bit 16_40 @@ -1242,7 +711,6 @@ bit 16_46 bit 16_47 bit 16_48 -bit 16_51 bit 16_54 bit 16_56 bit 16_57 @@ -1262,7 +730,6 @@ bit 16_94 bit 16_95 bit 16_96 -bit 16_99 bit 16_102 bit 16_103 bit 16_104 @@ -1272,7 +739,6 @@ bit 16_110 bit 16_111 bit 16_112 -bit 16_115 bit 16_118 bit 16_120 bit 16_121 @@ -1292,7 +758,6 @@ bit 17_30 bit 17_31 bit 17_32 -bit 17_35 bit 17_38 bit 17_39 bit 17_40 @@ -1302,7 +767,6 @@ bit 17_46 bit 17_47 bit 17_48 -bit 17_51 bit 17_54 bit 17_55 bit 17_56 @@ -1315,14 +779,12 @@ bit 17_71 bit 17_73 bit 17_79 -bit 17_80 bit 17_85 bit 17_86 bit 17_87 bit 17_88 bit 17_94 bit 17_95 -bit 17_99 bit 17_102 bit 17_103 bit 17_104 @@ -1332,9 +794,7 @@ bit 17_110 bit 17_111 bit 17_112 -bit 17_115 bit 17_118 -bit 17_119 bit 17_120 bit 17_121 bit 17_122 @@ -1352,8 +812,6 @@ bit 18_25 bit 18_30 bit 18_31 -bit 18_33 -bit 18_34 bit 18_38 bit 18_39 bit 18_41 @@ -1363,7 +821,6 @@ bit 18_46 bit 18_47 bit 18_49 -bit 18_50 bit 18_54 bit 18_55 bit 18_56 @@ -1380,10 +837,10 @@ bit 18_84 bit 18_86 bit 18_87 +bit 18_89 bit 18_94 bit 18_95 bit 18_97 -bit 18_98 bit 18_102 bit 18_103 bit 18_105 @@ -1393,7 +850,6 @@ bit 18_110 bit 18_111 bit 18_113 -bit 18_114 bit 18_119 bit 18_120 bit 18_121 @@ -1401,9 +857,9 @@ bit 18_125 bit 18_127 bit 19_03 +bit 19_06 bit 19_07 bit 19_08 -bit 19_09 bit 19_14 bit 19_17 bit 19_20 @@ -1413,7 +869,6 @@ bit 19_30 bit 19_31 bit 19_33 -bit 19_34 bit 19_38 bit 19_39 bit 19_41 @@ -1423,7 +878,6 @@ bit 19_46 bit 19_47 bit 19_49 -bit 19_50 bit 19_54 bit 19_55 bit 19_56 @@ -1445,7 +899,6 @@ bit 19_94 bit 19_95 bit 19_97 -bit 19_98 bit 19_102 bit 19_103 bit 19_105 @@ -1455,19 +908,15 @@ bit 19_110 bit 19_111 bit 19_113 -bit 19_114 bit 19_119 bit 19_120 bit 19_121 bit 19_123 bit 19_125 bit 19_127 -bit 20_01 bit 20_02 -bit 20_05 bit 20_06 bit 20_09 -bit 20_13 bit 20_21 bit 20_22 bit 20_30 @@ -1476,20 +925,14 @@ bit 20_43 bit 20_44 bit 20_46 -bit 20_48 bit 20_54 -bit 20_55 bit 20_57 bit 20_58 bit 20_60 bit 20_62 -bit 20_65 bit 20_66 -bit 20_69 bit 20_70 bit 20_73 -bit 20_77 -bit 20_84 bit 20_85 bit 20_86 bit 20_94 @@ -1498,8 +941,8 @@ bit 20_107 bit 20_108 bit 20_110 +bit 20_112 bit 20_118 -bit 20_119 bit 20_121 bit 20_122 bit 20_124 @@ -1507,39 +950,30 @@ bit 21_02 bit 21_06 bit 21_09 -bit 21_20 bit 21_21 bit 21_22 bit 21_30 -bit 21_34 -bit 21_35 bit 21_38 bit 21_42 bit 21_43 bit 21_44 bit 21_46 -bit 21_51 -bit 21_52 bit 21_54 bit 21_57 bit 21_58 bit 21_60 bit 21_62 bit 21_66 -bit 21_69 bit 21_70 bit 21_73 -bit 21_84 bit 21_85 bit 21_86 bit 21_94 -bit 21_98 bit 21_102 bit 21_106 bit 21_107 bit 21_108 bit 21_110 -bit 21_116 bit 21_118 bit 21_121 bit 21_122 @@ -1558,17 +992,14 @@ bit 22_30 bit 22_31 bit 22_32 -bit 22_35 bit 22_38 bit 22_39 -bit 22_40 bit 22_42 bit 22_43 bit 22_44 bit 22_46 bit 22_47 bit 22_48 -bit 22_51 bit 22_54 bit 22_55 bit 22_56 @@ -1588,10 +1019,7 @@ bit 22_88 bit 22_94 bit 22_95 -bit 22_96 -bit 22_99 bit 22_102 -bit 22_103 bit 22_104 bit 22_106 bit 22_107 @@ -1599,7 +1027,6 @@ bit 22_110 bit 22_111 bit 22_112 -bit 22_115 bit 22_118 bit 22_120 bit 22_121 @@ -1619,7 +1046,6 @@ bit 23_30 bit 23_31 bit 23_32 -bit 23_35 bit 23_38 bit 23_39 bit 23_40 @@ -1629,7 +1055,6 @@ bit 23_46 bit 23_47 bit 23_48 -bit 23_51 bit 23_54 bit 23_56 bit 23_57 @@ -1648,7 +1073,6 @@ bit 23_94 bit 23_95 bit 23_96 -bit 23_99 bit 23_102 bit 23_103 bit 23_104 @@ -1658,20 +1082,16 @@ bit 23_110 bit 23_111 bit 23_112 -bit 23_115 bit 23_118 bit 23_120 bit 23_121 bit 23_122 bit 23_124 bit 23_126 -bit 24_01 bit 24_02 -bit 24_05 bit 24_06 bit 24_07 bit 24_09 -bit 24_13 bit 24_15 bit 24_16 bit 24_21 @@ -1681,7 +1101,6 @@ bit 24_30 bit 24_31 bit 24_32 -bit 24_35 bit 24_38 bit 24_39 bit 24_40 @@ -1691,7 +1110,6 @@ bit 24_46 bit 24_47 bit 24_48 -bit 24_51 bit 24_54 bit 24_55 bit 24_56 @@ -1699,16 +1117,12 @@ bit 24_58 bit 24_60 bit 24_62 -bit 24_65 bit 24_66 -bit 24_69 bit 24_70 bit 24_71 bit 24_73 -bit 24_77 bit 24_79 bit 24_80 -bit 24_84 bit 24_85 bit 24_86 bit 24_87 @@ -1716,7 +1130,6 @@ bit 24_94 bit 24_95 bit 24_96 -bit 24_99 bit 24_102 bit 24_103 bit 24_104 @@ -1726,9 +1139,7 @@ bit 24_110 bit 24_111 bit 24_112 -bit 24_115 bit 24_118 -bit 24_119 bit 24_120 bit 24_121 bit 24_122 @@ -1851,12 +1262,18 @@ bit 28_64 bit 28_67 bit 28_72 +bit 28_75 bit 28_76 bit 28_77 +bit 28_79 +bit 28_81 bit 28_83 bit 28_86 +bit 28_89 bit 28_93 bit 28_94 +bit 28_95 +bit 28_97 bit 28_110 bit 28_111 bit 28_116 @@ -1871,12 +1288,18 @@ bit 29_11 bit 29_16 bit 29_17 +bit 29_30 +bit 29_32 bit 29_33 bit 29_34 +bit 29_38 bit 29_41 bit 29_44 +bit 29_46 +bit 29_48 bit 29_50 bit 29_51 +bit 29_52 bit 29_55 bit 29_60 bit 29_63 @@ -1909,13 +1332,19 @@ bit 30_25 bit 30_27 bit 30_29 +bit 30_30 +bit 30_32 bit 30_34 bit 30_35 bit 30_37 +bit 30_38 bit 30_41 bit 30_44 +bit 30_46 +bit 30_48 bit 30_50 bit 30_51 +bit 30_52 bit 30_60 bit 30_67 bit 30_71 @@ -1950,13 +1379,19 @@ bit 31_56 bit 31_60 bit 31_67 +bit 31_75 bit 31_76 bit 31_77 +bit 31_79 +bit 31_81 bit 31_83 bit 31_86 +bit 31_89 bit 31_90 bit 31_92 bit 31_93 +bit 31_95 +bit 31_97 bit 31_98 bit 31_100 bit 31_102
diff --git a/artix7/segbits_clblm_l.db b/artix7/segbits_clblm_l.db index 115e380..582dbd1 100644 --- a/artix7/segbits_clblm_l.db +++ b/artix7/segbits_clblm_l.db
@@ -610,6 +610,7 @@ CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62 CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62 +CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62 CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63 @@ -682,6 +683,7 @@ CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57 CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57 CLBLM_L.SLICEM_X0.FFSYNC 00_48
diff --git a/artix7/segbits_clblm_l.origin_info.db b/artix7/segbits_clblm_l.origin_info.db index 7ae36ee..5bf41c7 100644 --- a/artix7/segbits_clblm_l.origin_info.db +++ b/artix7/segbits_clblm_l.origin_info.db
@@ -613,6 +613,7 @@ CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_L.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 @@ -685,6 +686,7 @@ CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
diff --git a/artix7/segbits_clblm_r.db b/artix7/segbits_clblm_r.db index 95499ca..78fbb06 100644 --- a/artix7/segbits_clblm_r.db +++ b/artix7/segbits_clblm_r.db
@@ -610,6 +610,7 @@ CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62 CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62 +CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62 CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63 @@ -682,6 +683,7 @@ CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57 CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57 CLBLM_R.SLICEM_X0.FFSYNC 00_48
diff --git a/artix7/segbits_clblm_r.origin_info.db b/artix7/segbits_clblm_r.origin_info.db index 2bbeb93..4a9cecc 100644 --- a/artix7/segbits_clblm_r.origin_info.db +++ b/artix7/segbits_clblm_r.origin_info.db
@@ -613,6 +613,7 @@ CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_R.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 @@ -685,6 +686,7 @@ CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
diff --git a/artix7/segbits_cmt_top_l_upper_t.db b/artix7/segbits_cmt_top_l_upper_t.db new file mode 100644 index 0000000..272af2a --- /dev/null +++ b/artix7/segbits_cmt_top_l_upper_t.db
@@ -0,0 +1,351 @@ +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07 +CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_06 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_06 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183 +CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327 +CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
diff --git a/artix7/segbits_cmt_top_l_upper_t.origin_info.db b/artix7/segbits_cmt_top_l_upper_t.origin_info.db new file mode 100644 index 0000000..a4a7967 --- /dev/null +++ b/artix7/segbits_cmt_top_l_upper_t.origin_info.db
@@ -0,0 +1,351 @@ +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07 +CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63 +CMT_TOP_L_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_06 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_06 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639 +CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722 +CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324 +CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
diff --git a/artix7/segbits_cmt_top_r_upper_t.db b/artix7/segbits_cmt_top_r_upper_t.db new file mode 100644 index 0000000..e5f8c62 --- /dev/null +++ b/artix7/segbits_cmt_top_r_upper_t.db
@@ -0,0 +1,351 @@ +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT 29_10 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT 29_07 +CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK 29_11 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP 28_06 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP 29_06 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183 +CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327 +CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
diff --git a/artix7/segbits_cmt_top_r_upper_t.origin_info.db b/artix7/segbits_cmt_top_r_upper_t.origin_info.db new file mode 100644 index 0000000..0cf3328 --- /dev/null +++ b/artix7/segbits_cmt_top_r_upper_t.origin_info.db
@@ -0,0 +1,351 @@ +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07 +CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63 +CMT_TOP_R_UPPER_T.PLLE2.COMP.ZHOLD_NO_CLKIN_BUF_TOP origin:032-cmt-pll 28_06 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF_NO_TOP origin:032-cmt-pll 29_06 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639 +CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722 +CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324 +CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
diff --git a/artix7/segbits_int_l.origin_info.db b/artix7/segbits_int_l.origin_info.db index 156db7d..13cf444 100644 --- a/artix7/segbits_int_l.origin_info.db +++ b/artix7/segbits_int_l.origin_info.db
@@ -676,7 +676,7 @@ INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08 INT_L.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08 INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 +INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 INT_L.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 @@ -2173,7 +2173,7 @@ INT_L.NE6BEG2.SE2END2 origin:050-pip-seed 02_37 05_39 INT_L.NE6BEG2.SE6END2 origin:050-pip-seed 05_39 06_36 INT_L.NE6BEG2.WW2END1 origin:050-pip-seed 03_36 04_37 -INT_L.NE6BEG2.WW4END2 origin:050-pip-seed 04_37 05_36 +INT_L.NE6BEG2.WW4END2 origin:056-pip-rem 04_37 05_36 INT_L.NE6BEG3.EE2END3 origin:050-pip-seed 03_52 05_55 INT_L.NE6BEG3.EE4END3 origin:050-pip-seed 05_52 05_55 INT_L.NE6BEG3.LH0 origin:056-pip-rem 04_54 05_52 @@ -2191,9 +2191,9 @@ INT_L.NE6BEG3.NW2END3 origin:050-pip-seed 02_53 04_53 INT_L.NE6BEG3.NW6END3 origin:050-pip-seed 04_53 06_52 INT_L.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 -INT_L.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 +INT_L.NE6BEG3.SE6END3 origin:056-pip-rem 05_55 06_52 INT_L.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_L.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 +INT_L.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 INT_L.NL1BEG0.LOGIC_OUTS_L1 origin:050-pip-seed 07_16 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L13 origin:050-pip-seed 10_17 14_17 INT_L.NL1BEG0.LOGIC_OUTS_L19 origin:050-pip-seed 08_17 14_17 @@ -2827,7 +2827,7 @@ INT_L.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56 INT_L.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59 INT_L.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56 -INT_L.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59 +INT_L.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59 INT_L.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58 INT_L.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59 INT_L.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58 @@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31 INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 +INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46 INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45 INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44 @@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35 -INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35 +INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
diff --git a/artix7/segbits_int_r.origin_info.db b/artix7/segbits_int_r.origin_info.db index 2b6e151..e165b86 100644 --- a/artix7/segbits_int_r.origin_info.db +++ b/artix7/segbits_int_r.origin_info.db
@@ -353,7 +353,7 @@ INT_R.EE4BEG0.SS2END0 origin:050-pip-seed 03_08 05_11 INT_R.EE4BEG0.SS6END0 origin:050-pip-seed 05_11 06_08 INT_R.EE4BEG0.SW2END0 origin:050-pip-seed 02_09 05_11 -INT_R.EE4BEG0.SW6END0 origin:056-pip-rem 05_08 05_11 +INT_R.EE4BEG0.SW6END0 origin:050-pip-seed 05_08 05_11 INT_R.EE4BEG1.EE2END1 origin:050-pip-seed 03_24 03_25 INT_R.EE4BEG1.EE4END1 origin:050-pip-seed 03_25 05_24 INT_R.EE4BEG1.LH6 origin:056-pip-rem 05_24 07_25 @@ -393,7 +393,7 @@ INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43 INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40 INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43 -INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43 +INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43 INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57 INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56 INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56 @@ -584,7 +584,7 @@ INT_R.FAN_ALT0.GFAN0 origin:054-pip-fan-alt !22_00 !23_00 !24_00 21_00 25_00 INT_R.FAN_ALT0.LOGIC_OUTS0 origin:050-pip-seed !23_00 21_00 22_00 24_00 25_00 INT_R.FAN_ALT0.LOGIC_OUTS12 origin:050-pip-seed !22_00 21_00 23_00 24_00 25_00 -INT_R.FAN_ALT0.LOGIC_OUTS22 origin:056-pip-rem !22_00 !23_00 !25_00 21_00 24_00 +INT_R.FAN_ALT0.LOGIC_OUTS22 origin:050-pip-seed !22_00 !23_00 !25_00 21_00 24_00 INT_R.FAN_ALT0.NE2END0 origin:050-pip-seed !22_00 !23_00 !25_00 18_01 24_00 INT_R.FAN_ALT0.NL1END0 origin:050-pip-seed !22_00 19_01 23_00 24_00 25_00 INT_R.FAN_ALT0.NN2END0 origin:050-pip-seed !22_00 !23_00 !24_00 18_01 25_00 @@ -3275,7 +3275,7 @@ INT_R.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31 INT_R.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31 INT_R.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_R.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 +INT_R.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 INT_R.SW6BEG2.LOGIC_OUTS10 origin:050-pip-seed 03_44 04_46 INT_R.SW6BEG2.LOGIC_OUTS14 origin:050-pip-seed 03_44 07_45 INT_R.SW6BEG2.LOGIC_OUTS16 origin:050-pip-seed 04_46 06_44
diff --git a/artix7/segbits_liob33.db b/artix7/segbits_liob33.db index 2d951a6..207cb3a 100644 --- a/artix7/segbits_liob33.db +++ b/artix7/segbits_liob33.db
@@ -1,6 +1,8 @@ LIOB33.IOB_Y0.IBUFDISABLE.I 38_82 +LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 +LIOB33.IOB_Y0.IFF.INV_OCLK 28_124 LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67 LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72 LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76 @@ -16,8 +18,11 @@ LIOB33.IOB_Y0.INOUT 30_67 LIOB33.IOB_Y0.INTERMDISABLE.I 39_89 LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108 +LIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121 LIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 39_117 39_119 !39_125 !39_127 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92 @@ -63,8 +68,10 @@ LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 !39_119 39_125 39_127 LIOB33.IOB_Y1.IBUFDISABLE.I 39_45 +LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28 +LIOB33.IOB_Y1.IFF.INV_OCLK 29_03 LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60 LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55 LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51 @@ -80,8 +87,11 @@ LIOB33.IOB_Y1.INOUT 31_60 LIOB33.IOB_Y1.INTERMDISABLE.I 38_38 LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19 +LIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
diff --git a/artix7/segbits_liob33.origin_info.db b/artix7/segbits_liob33.origin_info.db index d22584e..703b24f 100644 --- a/artix7/segbits_liob33.origin_info.db +++ b/artix7/segbits_liob33.origin_info.db
@@ -1,7 +1,9 @@ LIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82 +LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67 LIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99 +LIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 LIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 LIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72 LIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76 @@ -19,7 +21,10 @@ LIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125 LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121 +LIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83 LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95 LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95 LIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95 @@ -63,9 +68,11 @@ LIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75 LIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 +LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60 LIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28 +LIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 LIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 LIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55 LIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51 @@ -83,7 +90,10 @@ LIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09 LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06 +LIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
diff --git a/artix7/segbits_riob33.db b/artix7/segbits_riob33.db index 955caa1..a046b59 100644 --- a/artix7/segbits_riob33.db +++ b/artix7/segbits_riob33.db
@@ -1,6 +1,8 @@ RIOB33.IOB_Y0.IBUFDISABLE.I 38_82 +RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 +RIOB33.IOB_Y0.IFF.INV_OCLK 28_124 RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67 RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72 RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76 @@ -16,8 +18,11 @@ RIOB33.IOB_Y0.INOUT 30_67 RIOB33.IOB_Y0.INTERMDISABLE.I 39_89 RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108 +RIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121 RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 39_117 39_119 !39_125 !39_127 RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92 RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92 @@ -63,8 +68,10 @@ RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 !39_119 39_125 39_127 RIOB33.IOB_Y1.IBUFDISABLE.I 39_45 +RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28 +RIOB33.IOB_Y1.IFF.INV_OCLK 29_03 RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60 RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55 RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51 @@ -80,8 +87,11 @@ RIOB33.IOB_Y1.INOUT 31_60 RIOB33.IOB_Y1.INTERMDISABLE.I 38_38 RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19 +RIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
diff --git a/artix7/segbits_riob33.origin_info.db b/artix7/segbits_riob33.origin_info.db index b6a5e96..20af015 100644 --- a/artix7/segbits_riob33.origin_info.db +++ b/artix7/segbits_riob33.origin_info.db
@@ -1,7 +1,9 @@ RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82 +RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67 RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99 +RIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72 RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76 @@ -19,7 +21,10 @@ RIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125 RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121 +RIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95 @@ -63,9 +68,11 @@ RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75 RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 +RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60 RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28 +RIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 RIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 RIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55 RIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51 @@ -83,7 +90,10 @@ RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09 RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06 +RIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
diff --git a/artix7/tilegrid.json b/artix7/tilegrid.json index 115f465..a965a8d 100644 --- a/artix7/tilegrid.json +++ b/artix7/tilegrid.json
@@ -76261,7 +76261,7 @@ "CMT_TOP_L_LOWER_B_X106Y61": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00020080", + "baseaddr": "0x00001500", "frames": 30, "offset": 0, "words": 101 @@ -76277,7 +76277,7 @@ "CMT_TOP_L_LOWER_B_X106Y9": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00000080", + "baseaddr": "0x00401500", "frames": 30, "offset": 0, "words": 101 @@ -76347,8 +76347,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00401500", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 106, @@ -76363,8 +76363,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00001500", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 106, @@ -76377,7 +76377,7 @@ "CMT_TOP_R_LOWER_B_X8Y113": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00001500", + "baseaddr": "0x00020080", "frames": 30, "offset": 0, "words": 101 @@ -76393,7 +76393,7 @@ "CMT_TOP_R_LOWER_B_X8Y61": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00400080", + "baseaddr": "0x00000080", "frames": 30, "offset": 0, "words": 101 @@ -76409,7 +76409,7 @@ "CMT_TOP_R_LOWER_B_X8Y9": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00401500", + "baseaddr": "0x00400080", "frames": 30, "offset": 0, "words": 101 @@ -76505,8 +76505,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00020080", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 8, @@ -76521,8 +76521,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00400080", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 8, @@ -76537,8 +76537,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00000080", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 8,
diff --git a/kintex7/mask_liob33.db b/kintex7/mask_liob33.db index f55897d..f3540f3 100644 --- a/kintex7/mask_liob33.db +++ b/kintex7/mask_liob33.db
@@ -1,9 +1,3 @@ -bit 00_01 -bit 00_02 -bit 00_03 -bit 00_07 -bit 00_09 -bit 00_10 bit 00_11 bit 00_14 bit 00_17 @@ -12,19 +6,6 @@ bit 00_35 bit 00_38 bit 00_39 -bit 00_42 -bit 00_43 -bit 00_45 -bit 00_46 -bit 00_50 -bit 00_51 -bit 00_54 -bit 00_65 -bit 00_66 -bit 00_67 -bit 00_69 -bit 00_71 -bit 00_73 bit 00_75 bit 00_78 bit 00_81 @@ -33,692 +14,251 @@ bit 00_99 bit 00_102 bit 00_103 -bit 00_106 -bit 00_109 -bit 00_110 -bit 00_111 -bit 00_114 -bit 00_115 -bit 00_118 -bit 01_00 -bit 01_01 -bit 01_02 -bit 01_04 -bit 01_05 -bit 01_06 -bit 01_08 bit 01_09 bit 01_10 bit 01_13 bit 01_14 -bit 01_32 bit 01_33 -bit 01_36 bit 01_37 bit 01_38 bit 01_40 -bit 01_41 -bit 01_42 -bit 01_44 -bit 01_45 -bit 01_46 -bit 01_50 -bit 01_52 -bit 01_64 -bit 01_65 -bit 01_66 -bit 01_68 -bit 01_69 -bit 01_70 -bit 01_72 bit 01_73 bit 01_74 bit 01_77 bit 01_78 -bit 01_96 bit 01_97 -bit 01_100 bit 01_101 bit 01_102 bit 01_104 -bit 01_105 -bit 01_106 -bit 01_108 -bit 01_109 -bit 01_110 -bit 01_112 -bit 01_114 -bit 01_116 -bit 02_05 -bit 02_06 -bit 02_07 -bit 02_09 -bit 02_11 -bit 02_13 -bit 02_14 -bit 02_15 -bit 02_18 -bit 02_22 -bit 02_23 -bit 02_30 -bit 02_31 -bit 02_34 -bit 02_35 -bit 02_38 -bit 02_39 -bit 02_46 -bit 02_47 -bit 02_50 -bit 02_51 -bit 02_54 bit 02_55 -bit 02_59 -bit 02_62 -bit 02_63 -bit 02_66 -bit 02_69 -bit 02_70 -bit 02_71 -bit 02_74 -bit 02_77 -bit 02_78 -bit 02_79 -bit 02_82 -bit 02_86 -bit 02_87 -bit 02_94 -bit 02_95 -bit 02_98 -bit 02_99 -bit 02_102 -bit 02_103 -bit 02_106 -bit 02_110 -bit 02_111 -bit 02_118 -bit 02_119 -bit 02_126 -bit 02_127 -bit 03_02 -bit 03_05 -bit 03_06 -bit 03_10 -bit 03_13 -bit 03_14 -bit 03_29 -bit 03_30 -bit 03_37 -bit 03_38 -bit 03_45 -bit 03_52 -bit 03_53 -bit 03_54 -bit 03_60 -bit 03_61 -bit 03_62 -bit 03_66 -bit 03_69 -bit 03_70 -bit 03_74 -bit 03_77 -bit 03_78 -bit 03_85 -bit 03_86 -bit 03_93 -bit 03_101 -bit 03_102 -bit 03_109 -bit 03_110 -bit 03_116 -bit 03_117 -bit 03_118 -bit 03_122 -bit 03_125 -bit 03_126 -bit 04_05 -bit 04_06 -bit 04_07 -bit 04_10 -bit 04_11 -bit 04_12 -bit 04_14 -bit 04_15 -bit 04_20 -bit 04_21 -bit 04_22 -bit 04_27 -bit 04_30 -bit 04_31 -bit 04_35 -bit 04_36 -bit 04_37 -bit 04_39 -bit 04_43 -bit 04_44 -bit 04_47 -bit 04_51 bit 04_52 -bit 04_53 -bit 04_55 -bit 04_59 -bit 04_60 -bit 04_61 -bit 04_63 -bit 04_64 -bit 04_67 -bit 04_68 -bit 04_69 -bit 04_70 -bit 04_75 -bit 04_76 -bit 04_77 -bit 04_78 -bit 04_79 -bit 04_84 -bit 04_85 -bit 04_86 -bit 04_87 -bit 04_91 -bit 04_94 -bit 04_95 -bit 04_99 -bit 04_100 -bit 04_101 -bit 04_103 -bit 04_107 -bit 04_108 -bit 04_111 -bit 04_115 -bit 04_116 -bit 04_117 -bit 04_119 -bit 04_124 -bit 05_01 -bit 05_05 -bit 05_07 -bit 05_09 -bit 05_10 -bit 05_12 -bit 05_13 -bit 05_14 -bit 05_17 -bit 05_18 -bit 05_22 -bit 05_25 -bit 05_26 -bit 05_28 -bit 05_33 -bit 05_34 -bit 05_36 -bit 05_37 -bit 05_38 -bit 05_42 -bit 05_44 -bit 05_46 -bit 05_49 -bit 05_50 -bit 05_52 -bit 05_53 -bit 05_54 -bit 05_58 -bit 05_60 -bit 05_65 -bit 05_66 -bit 05_68 -bit 05_69 -bit 05_73 -bit 05_74 -bit 05_76 -bit 05_77 -bit 05_81 -bit 05_86 -bit 05_89 -bit 05_90 -bit 05_92 -bit 05_97 -bit 05_98 -bit 05_101 -bit 05_102 -bit 05_106 -bit 05_108 -bit 05_113 -bit 05_114 -bit 05_116 -bit 05_117 -bit 05_122 -bit 05_124 bit 06_01 -bit 06_02 bit 06_03 -bit 06_04 -bit 06_05 -bit 06_06 -bit 06_10 -bit 06_12 bit 06_13 -bit 06_14 bit 06_17 -bit 06_20 -bit 06_22 -bit 06_28 -bit 06_29 -bit 06_30 bit 06_33 bit 06_35 -bit 06_36 -bit 06_37 -bit 06_39 -bit 06_44 -bit 06_45 -bit 06_46 bit 06_49 bit 06_51 -bit 06_52 -bit 06_53 -bit 06_55 -bit 06_59 -bit 06_60 bit 06_61 bit 06_65 -bit 06_66 bit 06_67 -bit 06_68 -bit 06_69 -bit 06_70 -bit 06_71 -bit 06_74 -bit 06_75 -bit 06_76 -bit 06_77 -bit 06_78 bit 06_81 bit 06_83 -bit 06_84 -bit 06_86 -bit 06_92 -bit 06_94 bit 06_97 bit 06_99 -bit 06_100 -bit 06_101 -bit 06_107 -bit 06_109 -bit 06_110 bit 06_113 bit 06_115 -bit 06_116 -bit 06_117 -bit 06_119 bit 06_121 -bit 06_123 -bit 06_125 bit 07_00 -bit 07_03 -bit 07_04 -bit 07_05 bit 07_06 -bit 07_07 bit 07_08 -bit 07_10 -bit 07_11 bit 07_12 -bit 07_13 bit 07_14 -bit 07_15 bit 07_16 -bit 07_19 bit 07_22 -bit 07_23 -bit 07_24 -bit 07_26 -bit 07_27 bit 07_28 bit 07_30 -bit 07_31 bit 07_32 bit 07_34 -bit 07_35 -bit 07_37 bit 07_38 -bit 07_39 bit 07_40 bit 07_44 bit 07_46 -bit 07_47 bit 07_48 -bit 07_50 -bit 07_51 -bit 07_53 bit 07_54 -bit 07_55 bit 07_56 -bit 07_58 -bit 07_59 bit 07_60 bit 07_62 -bit 07_63 bit 07_64 -bit 07_67 -bit 07_68 -bit 07_69 bit 07_70 -bit 07_71 bit 07_72 -bit 07_74 -bit 07_75 bit 07_76 -bit 07_77 bit 07_78 -bit 07_79 bit 07_80 -bit 07_82 -bit 07_83 bit 07_86 -bit 07_87 bit 07_88 -bit 07_90 -bit 07_91 bit 07_92 bit 07_94 -bit 07_95 bit 07_96 bit 07_98 -bit 07_99 bit 07_102 -bit 07_103 bit 07_104 -bit 07_107 bit 07_108 bit 07_110 -bit 07_111 bit 07_112 -bit 07_114 -bit 07_115 -bit 07_117 bit 07_118 -bit 07_119 bit 07_120 -bit 07_123 bit 07_124 bit 07_126 -bit 07_127 bit 08_00 bit 08_01 bit 08_02 -bit 08_03 -bit 08_04 -bit 08_05 -bit 08_06 bit 08_07 bit 08_08 bit 08_09 -bit 08_10 -bit 08_12 -bit 08_13 bit 08_14 bit 08_15 bit 08_16 bit 08_17 bit 08_18 bit 08_19 -bit 08_20 bit 08_22 bit 08_23 bit 08_24 bit 08_25 -bit 08_26 bit 08_30 bit 08_31 bit 08_32 bit 08_33 bit 08_34 bit 08_35 -bit 08_36 -bit 08_38 bit 08_39 bit 08_40 bit 08_41 -bit 08_45 bit 08_46 -bit 08_47 bit 08_48 bit 08_49 bit 08_50 bit 08_51 -bit 08_52 -bit 08_53 bit 08_54 bit 08_55 bit 08_56 bit 08_57 -bit 08_59 -bit 08_60 -bit 08_61 bit 08_62 bit 08_63 bit 08_64 bit 08_65 bit 08_66 bit 08_67 -bit 08_68 -bit 08_69 -bit 08_70 bit 08_71 bit 08_72 bit 08_73 -bit 08_74 -bit 08_76 -bit 08_77 bit 08_78 bit 08_79 bit 08_80 bit 08_81 bit 08_82 bit 08_83 -bit 08_84 -bit 08_86 bit 08_87 bit 08_88 bit 08_89 -bit 08_90 bit 08_94 bit 08_95 bit 08_96 bit 08_97 bit 08_98 bit 08_99 -bit 08_102 bit 08_103 bit 08_104 bit 08_105 -bit 08_109 bit 08_110 -bit 08_111 bit 08_112 bit 08_113 bit 08_114 -bit 08_115 -bit 08_116 -bit 08_117 -bit 08_118 bit 08_119 bit 08_120 bit 08_121 -bit 08_124 bit 08_125 bit 08_126 bit 08_127 bit 09_00 -bit 09_02 bit 09_03 bit 09_04 -bit 09_05 -bit 09_07 -bit 09_08 -bit 09_09 -bit 09_10 bit 09_11 bit 09_12 bit 09_13 bit 09_16 -bit 09_18 -bit 09_19 -bit 09_23 -bit 09_24 -bit 09_26 +bit 09_20 bit 09_27 bit 09_28 bit 09_29 -bit 09_30 -bit 09_31 -bit 09_32 -bit 09_33 bit 09_34 bit 09_35 bit 09_36 -bit 09_40 +bit 09_42 bit 09_43 bit 09_44 bit 09_45 -bit 09_46 -bit 09_47 bit 09_48 bit 09_49 -bit 09_50 bit 09_51 -bit 09_52 -bit 09_56 -bit 09_57 bit 09_58 bit 09_59 bit 09_60 bit 09_61 -bit 09_64 bit 09_66 bit 09_67 -bit 09_69 -bit 09_71 -bit 09_72 -bit 09_73 +bit 09_68 +bit 09_74 bit 09_75 bit 09_76 bit 09_77 bit 09_78 -bit 09_79 -bit 09_82 bit 09_83 -bit 09_87 -bit 09_88 bit 09_90 bit 09_91 bit 09_92 bit 09_93 bit 09_96 bit 09_98 -bit 09_99 -bit 09_104 -bit 09_106 +bit 09_100 bit 09_107 bit 09_108 bit 09_109 bit 09_110 -bit 09_111 -bit 09_112 -bit 09_113 -bit 09_114 bit 09_115 -bit 09_122 bit 09_123 bit 09_124 bit 09_125 bit 10_00 bit 10_01 bit 10_02 -bit 10_04 -bit 10_06 bit 10_07 -bit 10_08 -bit 10_09 -bit 10_10 -bit 10_11 bit 10_13 -bit 10_14 bit 10_15 bit 10_16 bit 10_17 bit 10_18 bit 10_20 -bit 10_22 bit 10_23 -bit 10_24 -bit 10_25 -bit 10_26 -bit 10_27 bit 10_29 bit 10_31 bit 10_32 bit 10_33 bit 10_34 -bit 10_35 -bit 10_36 bit 10_39 bit 10_41 -bit 10_45 -bit 10_46 bit 10_47 bit 10_48 bit 10_49 bit 10_50 -bit 10_51 -bit 10_52 -bit 10_54 bit 10_55 bit 10_57 -bit 10_59 -bit 10_60 -bit 10_61 bit 10_63 -bit 10_64 bit 10_65 bit 10_66 bit 10_67 -bit 10_68 -bit 10_70 bit 10_71 -bit 10_72 bit 10_73 bit 10_74 -bit 10_75 -bit 10_76 bit 10_77 -bit 10_78 bit 10_79 bit 10_80 bit 10_81 bit 10_82 -bit 10_83 -bit 10_84 -bit 10_86 bit 10_87 -bit 10_88 -bit 10_90 -bit 10_91 bit 10_93 bit 10_95 bit 10_96 -bit 10_97 bit 10_98 bit 10_99 -bit 10_100 -bit 10_102 bit 10_103 bit 10_106 bit 10_109 bit 10_111 bit 10_113 bit 10_114 -bit 10_115 -bit 10_118 bit 10_119 bit 10_121 bit 10_122 @@ -727,123 +267,83 @@ bit 11_01 bit 11_02 bit 11_03 -bit 11_05 bit 11_07 -bit 11_08 bit 11_09 -bit 11_10 -bit 11_11 bit 11_12 bit 11_13 bit 11_15 bit 11_16 bit 11_17 -bit 11_18 bit 11_19 bit 11_23 bit 11_25 -bit 11_26 -bit 11_27 -bit 11_28 bit 11_29 bit 11_30 bit 11_31 -bit 11_32 bit 11_33 -bit 11_34 bit 11_35 -bit 11_36 bit 11_39 bit 11_41 -bit 11_42 -bit 11_44 bit 11_45 bit 11_46 bit 11_47 bit 11_48 bit 11_49 -bit 11_50 bit 11_51 -bit 11_52 bit 11_55 -bit 11_56 bit 11_57 -bit 11_58 -bit 11_60 bit 11_61 bit 11_63 bit 11_64 bit 11_65 -bit 11_66 bit 11_67 -bit 11_69 bit 11_71 -bit 11_72 bit 11_73 -bit 11_74 -bit 11_75 bit 11_76 bit 11_77 bit 11_79 -bit 11_80 bit 11_81 -bit 11_82 bit 11_83 bit 11_87 bit 11_89 -bit 11_90 -bit 11_91 bit 11_93 bit 11_95 bit 11_96 bit 11_97 -bit 11_98 bit 11_99 bit 11_103 bit 11_105 -bit 11_106 bit 11_108 bit 11_109 bit 11_111 bit 11_112 bit 11_113 -bit 11_114 bit 11_115 bit 11_119 bit 11_121 -bit 11_122 bit 11_125 bit 11_127 bit 12_00 bit 12_01 bit 12_02 bit 12_03 -bit 12_05 -bit 12_06 bit 12_07 -bit 12_08 bit 12_09 bit 12_10 -bit 12_11 +bit 12_12 bit 12_13 bit 12_15 bit 12_16 bit 12_17 bit 12_18 bit 12_19 -bit 12_22 bit 12_23 bit 12_25 -bit 12_26 -bit 12_27 bit 12_29 bit 12_31 -bit 12_32 bit 12_33 bit 12_34 bit 12_35 -bit 12_37 -bit 12_38 bit 12_39 bit 12_41 bit 12_45 @@ -852,38 +352,28 @@ bit 12_49 bit 12_50 bit 12_51 -bit 12_52 -bit 12_53 -bit 12_54 bit 12_55 bit 12_57 bit 12_58 -bit 12_59 bit 12_60 bit 12_61 bit 12_63 -bit 12_64 bit 12_65 bit 12_66 bit 12_67 -bit 12_69 -bit 12_70 bit 12_71 bit 12_73 -bit 12_75 +bit 12_76 bit 12_77 bit 12_79 bit 12_81 bit 12_82 bit 12_83 -bit 12_86 bit 12_87 bit 12_89 -bit 12_90 bit 12_93 bit 12_95 bit 12_96 -bit 12_97 bit 12_98 bit 12_99 bit 12_103 @@ -891,11 +381,8 @@ bit 12_106 bit 12_109 bit 12_111 -bit 12_113 bit 12_114 bit 12_115 -bit 12_117 -bit 12_118 bit 12_119 bit 12_121 bit 12_122 @@ -905,27 +392,18 @@ bit 13_01 bit 13_02 bit 13_04 -bit 13_05 -bit 13_06 bit 13_07 -bit 13_08 bit 13_09 -bit 13_10 -bit 13_11 bit 13_12 bit 13_13 -bit 13_14 bit 13_15 bit 13_16 bit 13_17 bit 13_18 bit 13_19 -bit 13_22 +bit 13_20 bit 13_23 -bit 13_24 bit 13_25 -bit 13_26 -bit 13_27 bit 13_28 bit 13_30 bit 13_31 @@ -935,23 +413,15 @@ bit 13_35 bit 13_36 bit 13_39 -bit 13_40 bit 13_41 -bit 13_42 bit 13_44 bit 13_46 bit 13_47 bit 13_48 bit 13_49 bit 13_50 -bit 13_51 -bit 13_52 -bit 13_53 -bit 13_54 bit 13_55 -bit 13_56 bit 13_57 -bit 13_58 bit 13_60 bit 13_63 bit 13_64 @@ -959,48 +429,32 @@ bit 13_66 bit 13_67 bit 13_68 -bit 13_69 -bit 13_70 bit 13_71 -bit 13_72 bit 13_73 bit 13_74 -bit 13_75 bit 13_76 bit 13_78 bit 13_79 bit 13_80 bit 13_81 bit 13_82 -bit 13_83 -bit 13_86 bit 13_87 -bit 13_88 bit 13_89 -bit 13_90 -bit 13_91 bit 13_92 bit 13_93 bit 13_95 bit 13_96 bit 13_97 -bit 13_98 bit 13_99 bit 13_100 -bit 13_102 bit 13_103 -bit 13_104 bit 13_105 -bit 13_106 bit 13_108 bit 13_110 bit 13_111 bit 13_112 bit 13_113 bit 13_114 -bit 13_116 -bit 13_117 -bit 13_118 bit 13_119 bit 13_120 bit 13_121 @@ -1009,58 +463,27 @@ bit 13_125 bit 13_127 bit 14_00 -bit 14_01 bit 14_02 -bit 14_03 -bit 14_05 -bit 14_06 -bit 14_07 -bit 14_08 -bit 14_09 -bit 14_10 -bit 14_11 bit 14_12 -bit 14_15 bit 14_16 -bit 14_17 bit 14_18 bit 14_20 -bit 14_21 -bit 14_22 -bit 14_23 -bit 14_25 bit 14_26 -bit 14_27 +bit 14_28 bit 14_32 bit 14_34 bit 14_42 bit 14_48 bit 14_50 -bit 14_52 -bit 14_54 bit 14_58 bit 14_60 bit 14_64 -bit 14_65 bit 14_66 -bit 14_67 -bit 14_69 -bit 14_70 -bit 14_71 -bit 14_72 -bit 14_73 bit 14_74 -bit 14_75 bit 14_76 -bit 14_79 bit 14_80 bit 14_82 -bit 14_85 -bit 14_86 -bit 14_87 -bit 14_89 bit 14_90 -bit 14_91 bit 14_92 bit 14_96 bit 14_98 @@ -1071,29 +494,15 @@ bit 14_122 bit 14_124 bit 15_01 -bit 15_02 bit 15_03 -bit 15_04 -bit 15_05 -bit 15_06 bit 15_07 -bit 15_08 bit 15_09 -bit 15_10 -bit 15_11 -bit 15_12 bit 15_13 bit 15_15 bit 15_17 -bit 15_18 bit 15_19 -bit 15_20 -bit 15_22 bit 15_23 -bit 15_24 bit 15_25 -bit 15_26 -bit 15_27 bit 15_29 bit 15_31 bit 15_33 @@ -1109,29 +518,15 @@ bit 15_61 bit 15_63 bit 15_65 -bit 15_66 bit 15_67 -bit 15_68 -bit 15_69 -bit 15_70 bit 15_71 -bit 15_72 bit 15_73 -bit 15_74 -bit 15_75 -bit 15_76 bit 15_77 bit 15_79 bit 15_81 -bit 15_82 bit 15_83 -bit 15_84 -bit 15_86 bit 15_87 -bit 15_88 bit 15_89 -bit 15_90 -bit 15_91 bit 15_93 bit 15_95 bit 15_97 @@ -1148,7 +543,6 @@ bit 15_127 bit 16_02 bit 16_06 -bit 16_07 bit 16_09 bit 16_15 bit 16_16 @@ -1159,7 +553,6 @@ bit 16_30 bit 16_31 bit 16_32 -bit 16_35 bit 16_38 bit 16_39 bit 16_40 @@ -1169,7 +562,6 @@ bit 16_46 bit 16_47 bit 16_48 -bit 16_51 bit 16_54 bit 16_56 bit 16_57 @@ -1189,7 +581,6 @@ bit 16_94 bit 16_95 bit 16_96 -bit 16_99 bit 16_102 bit 16_103 bit 16_106 @@ -1198,7 +589,6 @@ bit 16_110 bit 16_111 bit 16_112 -bit 16_115 bit 16_118 bit 16_120 bit 16_121 @@ -1208,7 +598,6 @@ bit 17_02 bit 17_06 bit 17_07 -bit 17_08 bit 17_09 bit 17_15 bit 17_16 @@ -1219,7 +608,6 @@ bit 17_30 bit 17_31 bit 17_32 -bit 17_35 bit 17_38 bit 17_39 bit 17_40 @@ -1229,7 +617,6 @@ bit 17_46 bit 17_47 bit 17_48 -bit 17_51 bit 17_54 bit 17_55 bit 17_56 @@ -1249,17 +636,14 @@ bit 17_94 bit 17_95 bit 17_96 -bit 17_99 bit 17_102 bit 17_103 -bit 17_104 bit 17_106 bit 17_107 bit 17_108 bit 17_110 bit 17_111 bit 17_112 -bit 17_115 bit 17_118 bit 17_119 bit 17_120 @@ -1271,16 +655,14 @@ bit 18_06 bit 18_07 bit 18_08 -bit 18_09 bit 18_14 -bit 18_17 bit 18_20 bit 18_22 bit 18_23 bit 18_25 bit 18_30 bit 18_31 -bit 18_34 +bit 18_38 bit 18_39 bit 18_41 bit 18_42 @@ -1289,7 +671,6 @@ bit 18_46 bit 18_47 bit 18_49 -bit 18_50 bit 18_55 bit 18_56 bit 18_57 @@ -1306,7 +687,6 @@ bit 18_87 bit 18_94 bit 18_95 -bit 18_98 bit 18_102 bit 18_103 bit 18_105 @@ -1316,7 +696,6 @@ bit 18_110 bit 18_111 bit 18_113 -bit 18_114 bit 18_119 bit 18_120 bit 18_121 @@ -1335,8 +714,6 @@ bit 19_30 bit 19_31 bit 19_33 -bit 19_34 -bit 19_38 bit 19_39 bit 19_41 bit 19_42 @@ -1345,7 +722,6 @@ bit 19_46 bit 19_47 bit 19_49 -bit 19_50 bit 19_55 bit 19_56 bit 19_57 @@ -1365,8 +741,6 @@ bit 19_89 bit 19_94 bit 19_95 -bit 19_98 -bit 19_102 bit 19_103 bit 19_105 bit 19_106 @@ -1375,41 +749,31 @@ bit 19_110 bit 19_111 bit 19_113 -bit 19_114 bit 19_119 bit 19_120 bit 19_121 bit 19_123 bit 19_125 bit 19_127 -bit 20_01 bit 20_02 -bit 20_05 bit 20_06 bit 20_09 -bit 20_13 bit 20_21 bit 20_22 bit 20_30 -bit 20_35 bit 20_38 bit 20_42 bit 20_43 bit 20_44 bit 20_46 bit 20_54 -bit 20_55 bit 20_57 bit 20_58 bit 20_60 bit 20_62 -bit 20_65 bit 20_66 -bit 20_69 bit 20_70 bit 20_73 -bit 20_77 -bit 20_84 bit 20_85 bit 20_86 bit 20_94 @@ -1419,7 +783,6 @@ bit 20_108 bit 20_110 bit 20_118 -bit 20_119 bit 20_121 bit 20_122 bit 20_124 @@ -1427,57 +790,45 @@ bit 21_02 bit 21_06 bit 21_09 -bit 21_20 bit 21_21 bit 21_22 bit 21_23 bit 21_30 -bit 21_34 -bit 21_35 bit 21_38 bit 21_42 bit 21_43 bit 21_44 bit 21_46 -bit 21_51 -bit 21_52 bit 21_54 bit 21_57 bit 21_58 bit 21_60 bit 21_62 bit 21_66 -bit 21_69 bit 21_70 bit 21_73 -bit 21_84 bit 21_85 -bit 21_98 +bit 21_86 bit 21_102 bit 21_106 bit 21_107 bit 21_108 bit 21_110 -bit 21_115 -bit 21_116 bit 21_118 bit 21_121 bit 21_122 bit 21_126 bit 22_02 bit 22_06 -bit 22_08 bit 22_09 bit 22_15 bit 22_16 bit 22_21 bit 22_22 bit 22_23 -bit 22_24 bit 22_30 bit 22_31 bit 22_32 -bit 22_35 bit 22_38 bit 22_39 bit 22_42 @@ -1486,7 +837,6 @@ bit 22_46 bit 22_47 bit 22_48 -bit 22_51 bit 22_54 bit 22_56 bit 22_57 @@ -1505,7 +855,7 @@ bit 22_88 bit 22_94 bit 22_95 -bit 22_99 +bit 22_96 bit 22_102 bit 22_103 bit 22_104 @@ -1515,7 +865,6 @@ bit 22_110 bit 22_111 bit 22_112 -bit 22_115 bit 22_118 bit 22_120 bit 22_121 @@ -1524,7 +873,6 @@ bit 22_126 bit 23_02 bit 23_06 -bit 23_07 bit 23_09 bit 23_15 bit 23_16 @@ -1535,7 +883,6 @@ bit 23_30 bit 23_31 bit 23_32 -bit 23_35 bit 23_38 bit 23_39 bit 23_40 @@ -1545,7 +892,6 @@ bit 23_46 bit 23_47 bit 23_48 -bit 23_51 bit 23_54 bit 23_56 bit 23_57 @@ -1565,7 +911,6 @@ bit 23_94 bit 23_95 bit 23_96 -bit 23_99 bit 23_102 bit 23_103 bit 23_106 @@ -1574,21 +919,15 @@ bit 23_110 bit 23_111 bit 23_112 -bit 23_115 bit 23_118 -bit 23_120 bit 23_121 bit 23_122 bit 23_124 bit 23_126 -bit 24_01 bit 24_02 -bit 24_05 bit 24_06 bit 24_07 -bit 24_08 bit 24_09 -bit 24_13 bit 24_15 bit 24_16 bit 24_21 @@ -1598,7 +937,6 @@ bit 24_30 bit 24_31 bit 24_32 -bit 24_35 bit 24_38 bit 24_39 bit 24_40 @@ -1608,7 +946,6 @@ bit 24_46 bit 24_47 bit 24_48 -bit 24_51 bit 24_54 bit 24_55 bit 24_56 @@ -1616,16 +953,12 @@ bit 24_58 bit 24_60 bit 24_62 -bit 24_65 bit 24_66 -bit 24_69 bit 24_70 bit 24_71 bit 24_73 -bit 24_77 bit 24_79 bit 24_80 -bit 24_84 bit 24_85 bit 24_86 bit 24_87 @@ -1633,7 +966,6 @@ bit 24_94 bit 24_95 bit 24_96 -bit 24_99 bit 24_102 bit 24_103 bit 24_104 @@ -1643,7 +975,6 @@ bit 24_110 bit 24_111 bit 24_112 -bit 24_115 bit 24_118 bit 24_119 bit 24_120 @@ -1654,7 +985,6 @@ bit 25_02 bit 25_06 bit 25_07 -bit 25_08 bit 25_09 bit 25_15 bit 25_16 @@ -1767,12 +1097,18 @@ bit 28_64 bit 28_67 bit 28_72 +bit 28_75 bit 28_76 bit 28_77 +bit 28_79 +bit 28_81 bit 28_83 bit 28_86 +bit 28_89 bit 28_93 bit 28_94 +bit 28_95 +bit 28_97 bit 28_110 bit 28_111 bit 28_116 @@ -1787,12 +1123,18 @@ bit 29_11 bit 29_16 bit 29_17 +bit 29_30 +bit 29_32 bit 29_33 bit 29_34 +bit 29_38 bit 29_41 bit 29_44 +bit 29_46 +bit 29_48 bit 29_50 bit 29_51 +bit 29_52 bit 29_55 bit 29_60 bit 29_63 @@ -1825,13 +1167,19 @@ bit 30_25 bit 30_27 bit 30_29 +bit 30_30 +bit 30_32 bit 30_34 bit 30_35 bit 30_37 +bit 30_38 bit 30_41 bit 30_44 +bit 30_46 +bit 30_48 bit 30_50 bit 30_51 +bit 30_52 bit 30_60 bit 30_67 bit 30_71 @@ -1866,13 +1214,19 @@ bit 31_56 bit 31_60 bit 31_67 +bit 31_75 bit 31_76 bit 31_77 +bit 31_79 +bit 31_81 bit 31_83 bit 31_86 +bit 31_89 bit 31_90 bit 31_92 bit 31_93 +bit 31_95 +bit 31_97 bit 31_98 bit 31_100 bit 31_102
diff --git a/kintex7/mask_riob33.db b/kintex7/mask_riob33.db index f55897d..f3540f3 100644 --- a/kintex7/mask_riob33.db +++ b/kintex7/mask_riob33.db
@@ -1,9 +1,3 @@ -bit 00_01 -bit 00_02 -bit 00_03 -bit 00_07 -bit 00_09 -bit 00_10 bit 00_11 bit 00_14 bit 00_17 @@ -12,19 +6,6 @@ bit 00_35 bit 00_38 bit 00_39 -bit 00_42 -bit 00_43 -bit 00_45 -bit 00_46 -bit 00_50 -bit 00_51 -bit 00_54 -bit 00_65 -bit 00_66 -bit 00_67 -bit 00_69 -bit 00_71 -bit 00_73 bit 00_75 bit 00_78 bit 00_81 @@ -33,692 +14,251 @@ bit 00_99 bit 00_102 bit 00_103 -bit 00_106 -bit 00_109 -bit 00_110 -bit 00_111 -bit 00_114 -bit 00_115 -bit 00_118 -bit 01_00 -bit 01_01 -bit 01_02 -bit 01_04 -bit 01_05 -bit 01_06 -bit 01_08 bit 01_09 bit 01_10 bit 01_13 bit 01_14 -bit 01_32 bit 01_33 -bit 01_36 bit 01_37 bit 01_38 bit 01_40 -bit 01_41 -bit 01_42 -bit 01_44 -bit 01_45 -bit 01_46 -bit 01_50 -bit 01_52 -bit 01_64 -bit 01_65 -bit 01_66 -bit 01_68 -bit 01_69 -bit 01_70 -bit 01_72 bit 01_73 bit 01_74 bit 01_77 bit 01_78 -bit 01_96 bit 01_97 -bit 01_100 bit 01_101 bit 01_102 bit 01_104 -bit 01_105 -bit 01_106 -bit 01_108 -bit 01_109 -bit 01_110 -bit 01_112 -bit 01_114 -bit 01_116 -bit 02_05 -bit 02_06 -bit 02_07 -bit 02_09 -bit 02_11 -bit 02_13 -bit 02_14 -bit 02_15 -bit 02_18 -bit 02_22 -bit 02_23 -bit 02_30 -bit 02_31 -bit 02_34 -bit 02_35 -bit 02_38 -bit 02_39 -bit 02_46 -bit 02_47 -bit 02_50 -bit 02_51 -bit 02_54 bit 02_55 -bit 02_59 -bit 02_62 -bit 02_63 -bit 02_66 -bit 02_69 -bit 02_70 -bit 02_71 -bit 02_74 -bit 02_77 -bit 02_78 -bit 02_79 -bit 02_82 -bit 02_86 -bit 02_87 -bit 02_94 -bit 02_95 -bit 02_98 -bit 02_99 -bit 02_102 -bit 02_103 -bit 02_106 -bit 02_110 -bit 02_111 -bit 02_118 -bit 02_119 -bit 02_126 -bit 02_127 -bit 03_02 -bit 03_05 -bit 03_06 -bit 03_10 -bit 03_13 -bit 03_14 -bit 03_29 -bit 03_30 -bit 03_37 -bit 03_38 -bit 03_45 -bit 03_52 -bit 03_53 -bit 03_54 -bit 03_60 -bit 03_61 -bit 03_62 -bit 03_66 -bit 03_69 -bit 03_70 -bit 03_74 -bit 03_77 -bit 03_78 -bit 03_85 -bit 03_86 -bit 03_93 -bit 03_101 -bit 03_102 -bit 03_109 -bit 03_110 -bit 03_116 -bit 03_117 -bit 03_118 -bit 03_122 -bit 03_125 -bit 03_126 -bit 04_05 -bit 04_06 -bit 04_07 -bit 04_10 -bit 04_11 -bit 04_12 -bit 04_14 -bit 04_15 -bit 04_20 -bit 04_21 -bit 04_22 -bit 04_27 -bit 04_30 -bit 04_31 -bit 04_35 -bit 04_36 -bit 04_37 -bit 04_39 -bit 04_43 -bit 04_44 -bit 04_47 -bit 04_51 bit 04_52 -bit 04_53 -bit 04_55 -bit 04_59 -bit 04_60 -bit 04_61 -bit 04_63 -bit 04_64 -bit 04_67 -bit 04_68 -bit 04_69 -bit 04_70 -bit 04_75 -bit 04_76 -bit 04_77 -bit 04_78 -bit 04_79 -bit 04_84 -bit 04_85 -bit 04_86 -bit 04_87 -bit 04_91 -bit 04_94 -bit 04_95 -bit 04_99 -bit 04_100 -bit 04_101 -bit 04_103 -bit 04_107 -bit 04_108 -bit 04_111 -bit 04_115 -bit 04_116 -bit 04_117 -bit 04_119 -bit 04_124 -bit 05_01 -bit 05_05 -bit 05_07 -bit 05_09 -bit 05_10 -bit 05_12 -bit 05_13 -bit 05_14 -bit 05_17 -bit 05_18 -bit 05_22 -bit 05_25 -bit 05_26 -bit 05_28 -bit 05_33 -bit 05_34 -bit 05_36 -bit 05_37 -bit 05_38 -bit 05_42 -bit 05_44 -bit 05_46 -bit 05_49 -bit 05_50 -bit 05_52 -bit 05_53 -bit 05_54 -bit 05_58 -bit 05_60 -bit 05_65 -bit 05_66 -bit 05_68 -bit 05_69 -bit 05_73 -bit 05_74 -bit 05_76 -bit 05_77 -bit 05_81 -bit 05_86 -bit 05_89 -bit 05_90 -bit 05_92 -bit 05_97 -bit 05_98 -bit 05_101 -bit 05_102 -bit 05_106 -bit 05_108 -bit 05_113 -bit 05_114 -bit 05_116 -bit 05_117 -bit 05_122 -bit 05_124 bit 06_01 -bit 06_02 bit 06_03 -bit 06_04 -bit 06_05 -bit 06_06 -bit 06_10 -bit 06_12 bit 06_13 -bit 06_14 bit 06_17 -bit 06_20 -bit 06_22 -bit 06_28 -bit 06_29 -bit 06_30 bit 06_33 bit 06_35 -bit 06_36 -bit 06_37 -bit 06_39 -bit 06_44 -bit 06_45 -bit 06_46 bit 06_49 bit 06_51 -bit 06_52 -bit 06_53 -bit 06_55 -bit 06_59 -bit 06_60 bit 06_61 bit 06_65 -bit 06_66 bit 06_67 -bit 06_68 -bit 06_69 -bit 06_70 -bit 06_71 -bit 06_74 -bit 06_75 -bit 06_76 -bit 06_77 -bit 06_78 bit 06_81 bit 06_83 -bit 06_84 -bit 06_86 -bit 06_92 -bit 06_94 bit 06_97 bit 06_99 -bit 06_100 -bit 06_101 -bit 06_107 -bit 06_109 -bit 06_110 bit 06_113 bit 06_115 -bit 06_116 -bit 06_117 -bit 06_119 bit 06_121 -bit 06_123 -bit 06_125 bit 07_00 -bit 07_03 -bit 07_04 -bit 07_05 bit 07_06 -bit 07_07 bit 07_08 -bit 07_10 -bit 07_11 bit 07_12 -bit 07_13 bit 07_14 -bit 07_15 bit 07_16 -bit 07_19 bit 07_22 -bit 07_23 -bit 07_24 -bit 07_26 -bit 07_27 bit 07_28 bit 07_30 -bit 07_31 bit 07_32 bit 07_34 -bit 07_35 -bit 07_37 bit 07_38 -bit 07_39 bit 07_40 bit 07_44 bit 07_46 -bit 07_47 bit 07_48 -bit 07_50 -bit 07_51 -bit 07_53 bit 07_54 -bit 07_55 bit 07_56 -bit 07_58 -bit 07_59 bit 07_60 bit 07_62 -bit 07_63 bit 07_64 -bit 07_67 -bit 07_68 -bit 07_69 bit 07_70 -bit 07_71 bit 07_72 -bit 07_74 -bit 07_75 bit 07_76 -bit 07_77 bit 07_78 -bit 07_79 bit 07_80 -bit 07_82 -bit 07_83 bit 07_86 -bit 07_87 bit 07_88 -bit 07_90 -bit 07_91 bit 07_92 bit 07_94 -bit 07_95 bit 07_96 bit 07_98 -bit 07_99 bit 07_102 -bit 07_103 bit 07_104 -bit 07_107 bit 07_108 bit 07_110 -bit 07_111 bit 07_112 -bit 07_114 -bit 07_115 -bit 07_117 bit 07_118 -bit 07_119 bit 07_120 -bit 07_123 bit 07_124 bit 07_126 -bit 07_127 bit 08_00 bit 08_01 bit 08_02 -bit 08_03 -bit 08_04 -bit 08_05 -bit 08_06 bit 08_07 bit 08_08 bit 08_09 -bit 08_10 -bit 08_12 -bit 08_13 bit 08_14 bit 08_15 bit 08_16 bit 08_17 bit 08_18 bit 08_19 -bit 08_20 bit 08_22 bit 08_23 bit 08_24 bit 08_25 -bit 08_26 bit 08_30 bit 08_31 bit 08_32 bit 08_33 bit 08_34 bit 08_35 -bit 08_36 -bit 08_38 bit 08_39 bit 08_40 bit 08_41 -bit 08_45 bit 08_46 -bit 08_47 bit 08_48 bit 08_49 bit 08_50 bit 08_51 -bit 08_52 -bit 08_53 bit 08_54 bit 08_55 bit 08_56 bit 08_57 -bit 08_59 -bit 08_60 -bit 08_61 bit 08_62 bit 08_63 bit 08_64 bit 08_65 bit 08_66 bit 08_67 -bit 08_68 -bit 08_69 -bit 08_70 bit 08_71 bit 08_72 bit 08_73 -bit 08_74 -bit 08_76 -bit 08_77 bit 08_78 bit 08_79 bit 08_80 bit 08_81 bit 08_82 bit 08_83 -bit 08_84 -bit 08_86 bit 08_87 bit 08_88 bit 08_89 -bit 08_90 bit 08_94 bit 08_95 bit 08_96 bit 08_97 bit 08_98 bit 08_99 -bit 08_102 bit 08_103 bit 08_104 bit 08_105 -bit 08_109 bit 08_110 -bit 08_111 bit 08_112 bit 08_113 bit 08_114 -bit 08_115 -bit 08_116 -bit 08_117 -bit 08_118 bit 08_119 bit 08_120 bit 08_121 -bit 08_124 bit 08_125 bit 08_126 bit 08_127 bit 09_00 -bit 09_02 bit 09_03 bit 09_04 -bit 09_05 -bit 09_07 -bit 09_08 -bit 09_09 -bit 09_10 bit 09_11 bit 09_12 bit 09_13 bit 09_16 -bit 09_18 -bit 09_19 -bit 09_23 -bit 09_24 -bit 09_26 +bit 09_20 bit 09_27 bit 09_28 bit 09_29 -bit 09_30 -bit 09_31 -bit 09_32 -bit 09_33 bit 09_34 bit 09_35 bit 09_36 -bit 09_40 +bit 09_42 bit 09_43 bit 09_44 bit 09_45 -bit 09_46 -bit 09_47 bit 09_48 bit 09_49 -bit 09_50 bit 09_51 -bit 09_52 -bit 09_56 -bit 09_57 bit 09_58 bit 09_59 bit 09_60 bit 09_61 -bit 09_64 bit 09_66 bit 09_67 -bit 09_69 -bit 09_71 -bit 09_72 -bit 09_73 +bit 09_68 +bit 09_74 bit 09_75 bit 09_76 bit 09_77 bit 09_78 -bit 09_79 -bit 09_82 bit 09_83 -bit 09_87 -bit 09_88 bit 09_90 bit 09_91 bit 09_92 bit 09_93 bit 09_96 bit 09_98 -bit 09_99 -bit 09_104 -bit 09_106 +bit 09_100 bit 09_107 bit 09_108 bit 09_109 bit 09_110 -bit 09_111 -bit 09_112 -bit 09_113 -bit 09_114 bit 09_115 -bit 09_122 bit 09_123 bit 09_124 bit 09_125 bit 10_00 bit 10_01 bit 10_02 -bit 10_04 -bit 10_06 bit 10_07 -bit 10_08 -bit 10_09 -bit 10_10 -bit 10_11 bit 10_13 -bit 10_14 bit 10_15 bit 10_16 bit 10_17 bit 10_18 bit 10_20 -bit 10_22 bit 10_23 -bit 10_24 -bit 10_25 -bit 10_26 -bit 10_27 bit 10_29 bit 10_31 bit 10_32 bit 10_33 bit 10_34 -bit 10_35 -bit 10_36 bit 10_39 bit 10_41 -bit 10_45 -bit 10_46 bit 10_47 bit 10_48 bit 10_49 bit 10_50 -bit 10_51 -bit 10_52 -bit 10_54 bit 10_55 bit 10_57 -bit 10_59 -bit 10_60 -bit 10_61 bit 10_63 -bit 10_64 bit 10_65 bit 10_66 bit 10_67 -bit 10_68 -bit 10_70 bit 10_71 -bit 10_72 bit 10_73 bit 10_74 -bit 10_75 -bit 10_76 bit 10_77 -bit 10_78 bit 10_79 bit 10_80 bit 10_81 bit 10_82 -bit 10_83 -bit 10_84 -bit 10_86 bit 10_87 -bit 10_88 -bit 10_90 -bit 10_91 bit 10_93 bit 10_95 bit 10_96 -bit 10_97 bit 10_98 bit 10_99 -bit 10_100 -bit 10_102 bit 10_103 bit 10_106 bit 10_109 bit 10_111 bit 10_113 bit 10_114 -bit 10_115 -bit 10_118 bit 10_119 bit 10_121 bit 10_122 @@ -727,123 +267,83 @@ bit 11_01 bit 11_02 bit 11_03 -bit 11_05 bit 11_07 -bit 11_08 bit 11_09 -bit 11_10 -bit 11_11 bit 11_12 bit 11_13 bit 11_15 bit 11_16 bit 11_17 -bit 11_18 bit 11_19 bit 11_23 bit 11_25 -bit 11_26 -bit 11_27 -bit 11_28 bit 11_29 bit 11_30 bit 11_31 -bit 11_32 bit 11_33 -bit 11_34 bit 11_35 -bit 11_36 bit 11_39 bit 11_41 -bit 11_42 -bit 11_44 bit 11_45 bit 11_46 bit 11_47 bit 11_48 bit 11_49 -bit 11_50 bit 11_51 -bit 11_52 bit 11_55 -bit 11_56 bit 11_57 -bit 11_58 -bit 11_60 bit 11_61 bit 11_63 bit 11_64 bit 11_65 -bit 11_66 bit 11_67 -bit 11_69 bit 11_71 -bit 11_72 bit 11_73 -bit 11_74 -bit 11_75 bit 11_76 bit 11_77 bit 11_79 -bit 11_80 bit 11_81 -bit 11_82 bit 11_83 bit 11_87 bit 11_89 -bit 11_90 -bit 11_91 bit 11_93 bit 11_95 bit 11_96 bit 11_97 -bit 11_98 bit 11_99 bit 11_103 bit 11_105 -bit 11_106 bit 11_108 bit 11_109 bit 11_111 bit 11_112 bit 11_113 -bit 11_114 bit 11_115 bit 11_119 bit 11_121 -bit 11_122 bit 11_125 bit 11_127 bit 12_00 bit 12_01 bit 12_02 bit 12_03 -bit 12_05 -bit 12_06 bit 12_07 -bit 12_08 bit 12_09 bit 12_10 -bit 12_11 +bit 12_12 bit 12_13 bit 12_15 bit 12_16 bit 12_17 bit 12_18 bit 12_19 -bit 12_22 bit 12_23 bit 12_25 -bit 12_26 -bit 12_27 bit 12_29 bit 12_31 -bit 12_32 bit 12_33 bit 12_34 bit 12_35 -bit 12_37 -bit 12_38 bit 12_39 bit 12_41 bit 12_45 @@ -852,38 +352,28 @@ bit 12_49 bit 12_50 bit 12_51 -bit 12_52 -bit 12_53 -bit 12_54 bit 12_55 bit 12_57 bit 12_58 -bit 12_59 bit 12_60 bit 12_61 bit 12_63 -bit 12_64 bit 12_65 bit 12_66 bit 12_67 -bit 12_69 -bit 12_70 bit 12_71 bit 12_73 -bit 12_75 +bit 12_76 bit 12_77 bit 12_79 bit 12_81 bit 12_82 bit 12_83 -bit 12_86 bit 12_87 bit 12_89 -bit 12_90 bit 12_93 bit 12_95 bit 12_96 -bit 12_97 bit 12_98 bit 12_99 bit 12_103 @@ -891,11 +381,8 @@ bit 12_106 bit 12_109 bit 12_111 -bit 12_113 bit 12_114 bit 12_115 -bit 12_117 -bit 12_118 bit 12_119 bit 12_121 bit 12_122 @@ -905,27 +392,18 @@ bit 13_01 bit 13_02 bit 13_04 -bit 13_05 -bit 13_06 bit 13_07 -bit 13_08 bit 13_09 -bit 13_10 -bit 13_11 bit 13_12 bit 13_13 -bit 13_14 bit 13_15 bit 13_16 bit 13_17 bit 13_18 bit 13_19 -bit 13_22 +bit 13_20 bit 13_23 -bit 13_24 bit 13_25 -bit 13_26 -bit 13_27 bit 13_28 bit 13_30 bit 13_31 @@ -935,23 +413,15 @@ bit 13_35 bit 13_36 bit 13_39 -bit 13_40 bit 13_41 -bit 13_42 bit 13_44 bit 13_46 bit 13_47 bit 13_48 bit 13_49 bit 13_50 -bit 13_51 -bit 13_52 -bit 13_53 -bit 13_54 bit 13_55 -bit 13_56 bit 13_57 -bit 13_58 bit 13_60 bit 13_63 bit 13_64 @@ -959,48 +429,32 @@ bit 13_66 bit 13_67 bit 13_68 -bit 13_69 -bit 13_70 bit 13_71 -bit 13_72 bit 13_73 bit 13_74 -bit 13_75 bit 13_76 bit 13_78 bit 13_79 bit 13_80 bit 13_81 bit 13_82 -bit 13_83 -bit 13_86 bit 13_87 -bit 13_88 bit 13_89 -bit 13_90 -bit 13_91 bit 13_92 bit 13_93 bit 13_95 bit 13_96 bit 13_97 -bit 13_98 bit 13_99 bit 13_100 -bit 13_102 bit 13_103 -bit 13_104 bit 13_105 -bit 13_106 bit 13_108 bit 13_110 bit 13_111 bit 13_112 bit 13_113 bit 13_114 -bit 13_116 -bit 13_117 -bit 13_118 bit 13_119 bit 13_120 bit 13_121 @@ -1009,58 +463,27 @@ bit 13_125 bit 13_127 bit 14_00 -bit 14_01 bit 14_02 -bit 14_03 -bit 14_05 -bit 14_06 -bit 14_07 -bit 14_08 -bit 14_09 -bit 14_10 -bit 14_11 bit 14_12 -bit 14_15 bit 14_16 -bit 14_17 bit 14_18 bit 14_20 -bit 14_21 -bit 14_22 -bit 14_23 -bit 14_25 bit 14_26 -bit 14_27 +bit 14_28 bit 14_32 bit 14_34 bit 14_42 bit 14_48 bit 14_50 -bit 14_52 -bit 14_54 bit 14_58 bit 14_60 bit 14_64 -bit 14_65 bit 14_66 -bit 14_67 -bit 14_69 -bit 14_70 -bit 14_71 -bit 14_72 -bit 14_73 bit 14_74 -bit 14_75 bit 14_76 -bit 14_79 bit 14_80 bit 14_82 -bit 14_85 -bit 14_86 -bit 14_87 -bit 14_89 bit 14_90 -bit 14_91 bit 14_92 bit 14_96 bit 14_98 @@ -1071,29 +494,15 @@ bit 14_122 bit 14_124 bit 15_01 -bit 15_02 bit 15_03 -bit 15_04 -bit 15_05 -bit 15_06 bit 15_07 -bit 15_08 bit 15_09 -bit 15_10 -bit 15_11 -bit 15_12 bit 15_13 bit 15_15 bit 15_17 -bit 15_18 bit 15_19 -bit 15_20 -bit 15_22 bit 15_23 -bit 15_24 bit 15_25 -bit 15_26 -bit 15_27 bit 15_29 bit 15_31 bit 15_33 @@ -1109,29 +518,15 @@ bit 15_61 bit 15_63 bit 15_65 -bit 15_66 bit 15_67 -bit 15_68 -bit 15_69 -bit 15_70 bit 15_71 -bit 15_72 bit 15_73 -bit 15_74 -bit 15_75 -bit 15_76 bit 15_77 bit 15_79 bit 15_81 -bit 15_82 bit 15_83 -bit 15_84 -bit 15_86 bit 15_87 -bit 15_88 bit 15_89 -bit 15_90 -bit 15_91 bit 15_93 bit 15_95 bit 15_97 @@ -1148,7 +543,6 @@ bit 15_127 bit 16_02 bit 16_06 -bit 16_07 bit 16_09 bit 16_15 bit 16_16 @@ -1159,7 +553,6 @@ bit 16_30 bit 16_31 bit 16_32 -bit 16_35 bit 16_38 bit 16_39 bit 16_40 @@ -1169,7 +562,6 @@ bit 16_46 bit 16_47 bit 16_48 -bit 16_51 bit 16_54 bit 16_56 bit 16_57 @@ -1189,7 +581,6 @@ bit 16_94 bit 16_95 bit 16_96 -bit 16_99 bit 16_102 bit 16_103 bit 16_106 @@ -1198,7 +589,6 @@ bit 16_110 bit 16_111 bit 16_112 -bit 16_115 bit 16_118 bit 16_120 bit 16_121 @@ -1208,7 +598,6 @@ bit 17_02 bit 17_06 bit 17_07 -bit 17_08 bit 17_09 bit 17_15 bit 17_16 @@ -1219,7 +608,6 @@ bit 17_30 bit 17_31 bit 17_32 -bit 17_35 bit 17_38 bit 17_39 bit 17_40 @@ -1229,7 +617,6 @@ bit 17_46 bit 17_47 bit 17_48 -bit 17_51 bit 17_54 bit 17_55 bit 17_56 @@ -1249,17 +636,14 @@ bit 17_94 bit 17_95 bit 17_96 -bit 17_99 bit 17_102 bit 17_103 -bit 17_104 bit 17_106 bit 17_107 bit 17_108 bit 17_110 bit 17_111 bit 17_112 -bit 17_115 bit 17_118 bit 17_119 bit 17_120 @@ -1271,16 +655,14 @@ bit 18_06 bit 18_07 bit 18_08 -bit 18_09 bit 18_14 -bit 18_17 bit 18_20 bit 18_22 bit 18_23 bit 18_25 bit 18_30 bit 18_31 -bit 18_34 +bit 18_38 bit 18_39 bit 18_41 bit 18_42 @@ -1289,7 +671,6 @@ bit 18_46 bit 18_47 bit 18_49 -bit 18_50 bit 18_55 bit 18_56 bit 18_57 @@ -1306,7 +687,6 @@ bit 18_87 bit 18_94 bit 18_95 -bit 18_98 bit 18_102 bit 18_103 bit 18_105 @@ -1316,7 +696,6 @@ bit 18_110 bit 18_111 bit 18_113 -bit 18_114 bit 18_119 bit 18_120 bit 18_121 @@ -1335,8 +714,6 @@ bit 19_30 bit 19_31 bit 19_33 -bit 19_34 -bit 19_38 bit 19_39 bit 19_41 bit 19_42 @@ -1345,7 +722,6 @@ bit 19_46 bit 19_47 bit 19_49 -bit 19_50 bit 19_55 bit 19_56 bit 19_57 @@ -1365,8 +741,6 @@ bit 19_89 bit 19_94 bit 19_95 -bit 19_98 -bit 19_102 bit 19_103 bit 19_105 bit 19_106 @@ -1375,41 +749,31 @@ bit 19_110 bit 19_111 bit 19_113 -bit 19_114 bit 19_119 bit 19_120 bit 19_121 bit 19_123 bit 19_125 bit 19_127 -bit 20_01 bit 20_02 -bit 20_05 bit 20_06 bit 20_09 -bit 20_13 bit 20_21 bit 20_22 bit 20_30 -bit 20_35 bit 20_38 bit 20_42 bit 20_43 bit 20_44 bit 20_46 bit 20_54 -bit 20_55 bit 20_57 bit 20_58 bit 20_60 bit 20_62 -bit 20_65 bit 20_66 -bit 20_69 bit 20_70 bit 20_73 -bit 20_77 -bit 20_84 bit 20_85 bit 20_86 bit 20_94 @@ -1419,7 +783,6 @@ bit 20_108 bit 20_110 bit 20_118 -bit 20_119 bit 20_121 bit 20_122 bit 20_124 @@ -1427,57 +790,45 @@ bit 21_02 bit 21_06 bit 21_09 -bit 21_20 bit 21_21 bit 21_22 bit 21_23 bit 21_30 -bit 21_34 -bit 21_35 bit 21_38 bit 21_42 bit 21_43 bit 21_44 bit 21_46 -bit 21_51 -bit 21_52 bit 21_54 bit 21_57 bit 21_58 bit 21_60 bit 21_62 bit 21_66 -bit 21_69 bit 21_70 bit 21_73 -bit 21_84 bit 21_85 -bit 21_98 +bit 21_86 bit 21_102 bit 21_106 bit 21_107 bit 21_108 bit 21_110 -bit 21_115 -bit 21_116 bit 21_118 bit 21_121 bit 21_122 bit 21_126 bit 22_02 bit 22_06 -bit 22_08 bit 22_09 bit 22_15 bit 22_16 bit 22_21 bit 22_22 bit 22_23 -bit 22_24 bit 22_30 bit 22_31 bit 22_32 -bit 22_35 bit 22_38 bit 22_39 bit 22_42 @@ -1486,7 +837,6 @@ bit 22_46 bit 22_47 bit 22_48 -bit 22_51 bit 22_54 bit 22_56 bit 22_57 @@ -1505,7 +855,7 @@ bit 22_88 bit 22_94 bit 22_95 -bit 22_99 +bit 22_96 bit 22_102 bit 22_103 bit 22_104 @@ -1515,7 +865,6 @@ bit 22_110 bit 22_111 bit 22_112 -bit 22_115 bit 22_118 bit 22_120 bit 22_121 @@ -1524,7 +873,6 @@ bit 22_126 bit 23_02 bit 23_06 -bit 23_07 bit 23_09 bit 23_15 bit 23_16 @@ -1535,7 +883,6 @@ bit 23_30 bit 23_31 bit 23_32 -bit 23_35 bit 23_38 bit 23_39 bit 23_40 @@ -1545,7 +892,6 @@ bit 23_46 bit 23_47 bit 23_48 -bit 23_51 bit 23_54 bit 23_56 bit 23_57 @@ -1565,7 +911,6 @@ bit 23_94 bit 23_95 bit 23_96 -bit 23_99 bit 23_102 bit 23_103 bit 23_106 @@ -1574,21 +919,15 @@ bit 23_110 bit 23_111 bit 23_112 -bit 23_115 bit 23_118 -bit 23_120 bit 23_121 bit 23_122 bit 23_124 bit 23_126 -bit 24_01 bit 24_02 -bit 24_05 bit 24_06 bit 24_07 -bit 24_08 bit 24_09 -bit 24_13 bit 24_15 bit 24_16 bit 24_21 @@ -1598,7 +937,6 @@ bit 24_30 bit 24_31 bit 24_32 -bit 24_35 bit 24_38 bit 24_39 bit 24_40 @@ -1608,7 +946,6 @@ bit 24_46 bit 24_47 bit 24_48 -bit 24_51 bit 24_54 bit 24_55 bit 24_56 @@ -1616,16 +953,12 @@ bit 24_58 bit 24_60 bit 24_62 -bit 24_65 bit 24_66 -bit 24_69 bit 24_70 bit 24_71 bit 24_73 -bit 24_77 bit 24_79 bit 24_80 -bit 24_84 bit 24_85 bit 24_86 bit 24_87 @@ -1633,7 +966,6 @@ bit 24_94 bit 24_95 bit 24_96 -bit 24_99 bit 24_102 bit 24_103 bit 24_104 @@ -1643,7 +975,6 @@ bit 24_110 bit 24_111 bit 24_112 -bit 24_115 bit 24_118 bit 24_119 bit 24_120 @@ -1654,7 +985,6 @@ bit 25_02 bit 25_06 bit 25_07 -bit 25_08 bit 25_09 bit 25_15 bit 25_16 @@ -1767,12 +1097,18 @@ bit 28_64 bit 28_67 bit 28_72 +bit 28_75 bit 28_76 bit 28_77 +bit 28_79 +bit 28_81 bit 28_83 bit 28_86 +bit 28_89 bit 28_93 bit 28_94 +bit 28_95 +bit 28_97 bit 28_110 bit 28_111 bit 28_116 @@ -1787,12 +1123,18 @@ bit 29_11 bit 29_16 bit 29_17 +bit 29_30 +bit 29_32 bit 29_33 bit 29_34 +bit 29_38 bit 29_41 bit 29_44 +bit 29_46 +bit 29_48 bit 29_50 bit 29_51 +bit 29_52 bit 29_55 bit 29_60 bit 29_63 @@ -1825,13 +1167,19 @@ bit 30_25 bit 30_27 bit 30_29 +bit 30_30 +bit 30_32 bit 30_34 bit 30_35 bit 30_37 +bit 30_38 bit 30_41 bit 30_44 +bit 30_46 +bit 30_48 bit 30_50 bit 30_51 +bit 30_52 bit 30_60 bit 30_67 bit 30_71 @@ -1866,13 +1214,19 @@ bit 31_56 bit 31_60 bit 31_67 +bit 31_75 bit 31_76 bit 31_77 +bit 31_79 +bit 31_81 bit 31_83 bit 31_86 +bit 31_89 bit 31_90 bit 31_92 bit 31_93 +bit 31_95 +bit 31_97 bit 31_98 bit 31_100 bit 31_102
diff --git a/kintex7/segbits_clblm_l.db b/kintex7/segbits_clblm_l.db index 115e380..582dbd1 100644 --- a/kintex7/segbits_clblm_l.db +++ b/kintex7/segbits_clblm_l.db
@@ -610,6 +610,7 @@ CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62 CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62 +CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62 CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63 @@ -682,6 +683,7 @@ CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57 CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57 CLBLM_L.SLICEM_X0.FFSYNC 00_48
diff --git a/kintex7/segbits_clblm_l.origin_info.db b/kintex7/segbits_clblm_l.origin_info.db index 7ae36ee..5bf41c7 100644 --- a/kintex7/segbits_clblm_l.origin_info.db +++ b/kintex7/segbits_clblm_l.origin_info.db
@@ -613,6 +613,7 @@ CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_L.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 @@ -685,6 +686,7 @@ CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
diff --git a/kintex7/segbits_clblm_r.db b/kintex7/segbits_clblm_r.db index 95499ca..78fbb06 100644 --- a/kintex7/segbits_clblm_r.db +++ b/kintex7/segbits_clblm_r.db
@@ -610,6 +610,7 @@ CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62 CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62 +CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62 CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63 @@ -682,6 +683,7 @@ CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57 CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57 CLBLM_R.SLICEM_X0.FFSYNC 00_48
diff --git a/kintex7/segbits_clblm_r.origin_info.db b/kintex7/segbits_clblm_r.origin_info.db index 2bbeb93..4a9cecc 100644 --- a/kintex7/segbits_clblm_r.origin_info.db +++ b/kintex7/segbits_clblm_r.origin_info.db
@@ -613,6 +613,7 @@ CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_R.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 @@ -685,6 +686,7 @@ CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
diff --git a/kintex7/segbits_cmt_top_l_upper_t.db b/kintex7/segbits_cmt_top_l_upper_t.db new file mode 100644 index 0000000..f26c716 --- /dev/null +++ b/kintex7/segbits_cmt_top_l_upper_t.db
@@ -0,0 +1,349 @@ +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07 +CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183 +CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327 +CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
diff --git a/kintex7/segbits_cmt_top_l_upper_t.origin_info.db b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db new file mode 100644 index 0000000..71acb66 --- /dev/null +++ b/kintex7/segbits_cmt_top_l_upper_t.origin_info.db
@@ -0,0 +1,349 @@ +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07 +CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639 +CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722 +CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324 +CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
diff --git a/kintex7/segbits_cmt_top_r_upper_t.db b/kintex7/segbits_cmt_top_r_upper_t.db new file mode 100644 index 0000000..3ae7c06 --- /dev/null +++ b/kintex7/segbits_cmt_top_r_upper_t.db
@@ -0,0 +1,349 @@ +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT 29_10 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT 28_09 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT 29_07 +CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK 29_11 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF 28_41 29_04 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183 +CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327 +CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
diff --git a/kintex7/segbits_cmt_top_r_upper_t.origin_info.db b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db new file mode 100644 index 0000000..9ba05c1 --- /dev/null +++ b/kintex7/segbits_cmt_top_r_upper_t.origin_info.db
@@ -0,0 +1,349 @@ +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_R_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09 +CMT_TOP_R_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_R_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07 +CMT_TOP_R_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.ZHOLD_NO_CLKIN_BUF origin:032-cmt-pll 28_41 29_04 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639 +CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722 +CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324 +CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
diff --git a/kintex7/segbits_int_l.origin_info.db b/kintex7/segbits_int_l.origin_info.db index 9751df2..c135250 100644 --- a/kintex7/segbits_int_l.origin_info.db +++ b/kintex7/segbits_int_l.origin_info.db
@@ -373,7 +373,7 @@ INT_L.EE4BEG1.SS2END1 origin:050-pip-seed 03_24 05_27 INT_L.EE4BEG1.SS6END1 origin:050-pip-seed 05_27 06_24 INT_L.EE4BEG1.SW2END1 origin:050-pip-seed 02_25 05_27 -INT_L.EE4BEG1.SW6END1 origin:050-pip-seed 05_24 05_27 +INT_L.EE4BEG1.SW6END1 origin:056-pip-rem 05_24 05_27 INT_L.EE4BEG2.EE2END2 origin:050-pip-seed 03_40 03_41 INT_L.EE4BEG2.EE4END2 origin:050-pip-seed 03_41 05_40 INT_L.EE4BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_40 07_41 @@ -676,7 +676,7 @@ INT_L.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08 INT_L.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08 INT_L.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_L.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 +INT_L.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 INT_L.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08 INT_L.FAN_ALT4.LOGIC_OUTS_L18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 INT_L.FAN_ALT4.LOGIC_OUTS_L4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 @@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31 INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 +INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46 INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45 INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44 @@ -3603,7 +3603,7 @@ INT_L.WW4BEG2.LVB_L0 origin:056-pip-rem 04_34 05_32 INT_L.WW4BEG2.LVB_L12 origin:056-pip-rem 05_32 07_33 INT_L.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35 -INT_L.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35 +INT_L.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35 INT_L.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35 INT_L.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32 INT_L.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
diff --git a/kintex7/segbits_int_r.origin_info.db b/kintex7/segbits_int_r.origin_info.db index 147d004..f1344a8 100644 --- a/kintex7/segbits_int_r.origin_info.db +++ b/kintex7/segbits_int_r.origin_info.db
@@ -413,7 +413,7 @@ INT_R.EE4BEG3.SS2END3 origin:050-pip-seed 03_56 05_59 INT_R.EE4BEG3.SS6END3 origin:050-pip-seed 05_59 06_56 INT_R.EE4BEG3.SW2END3 origin:050-pip-seed 02_57 05_59 -INT_R.EE4BEG3.SW6END3 origin:056-pip-rem 05_56 05_59 +INT_R.EE4BEG3.SW6END3 origin:050-pip-seed 05_56 05_59 INT_R.EL1BEG0.EE2END1 origin:050-pip-seed 07_20 15_21 INT_R.EL1BEG0.EE4END1 origin:050-pip-seed 07_20 12_21 INT_R.EL1BEG0.EL1END1 origin:050-pip-seed 11_21 13_21 @@ -676,7 +676,7 @@ INT_R.FAN_ALT4.EL1END0 origin:050-pip-seed !22_08 16_08 23_08 24_08 25_08 INT_R.FAN_ALT4.ER1END0 origin:050-pip-seed !23_08 17_08 22_08 24_08 25_08 INT_R.FAN_ALT4.FAN_BOUNCE2 origin:050-pip-seed !23_08 20_08 22_08 24_08 25_08 -INT_R.FAN_ALT4.FAN_BOUNCE7 origin:050-pip-seed !22_08 20_08 23_08 24_08 25_08 +INT_R.FAN_ALT4.FAN_BOUNCE7 origin:056-pip-rem !22_08 20_08 23_08 24_08 25_08 INT_R.FAN_ALT4.GFAN0 origin:054-pip-fan-alt !22_08 !23_08 !24_08 21_08 25_08 INT_R.FAN_ALT4.LOGIC_OUTS18 origin:050-pip-seed !22_08 !23_08 !25_08 21_08 24_08 INT_R.FAN_ALT4.LOGIC_OUTS4 origin:050-pip-seed !23_08 21_08 22_08 24_08 25_08 @@ -2193,7 +2193,7 @@ INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 +INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17 INT_R.NL1BEG0.LOGIC_OUTS13 origin:050-pip-seed 10_17 14_17 INT_R.NL1BEG0.LOGIC_OUTS19 origin:050-pip-seed 08_17 14_17 @@ -3295,7 +3295,7 @@ INT_R.SW6BEG2.WW2END2 origin:050-pip-seed 03_44 05_47 INT_R.SW6BEG2.WW4END3 origin:050-pip-seed 05_44 05_47 INT_R.SW6BEG3.EE2END3 origin:050-pip-seed 03_60 04_61 -INT_R.SW6BEG3.EE4END3 origin:056-pip-rem 04_61 05_60 +INT_R.SW6BEG3.EE4END3 origin:050-pip-seed 04_61 05_60 INT_R.SW6BEG3.LH0 origin:056-pip-rem 04_62 05_60 INT_R.SW6BEG3.LOGIC_OUTS11 origin:050-pip-seed 03_60 07_61 INT_R.SW6BEG3.LOGIC_OUTS15 origin:050-pip-seed 03_60 04_62
diff --git a/kintex7/segbits_liob33.db b/kintex7/segbits_liob33.db index ac8d613..0857100 100644 --- a/kintex7/segbits_liob33.db +++ b/kintex7/segbits_liob33.db
@@ -1,6 +1,8 @@ LIOB33.IOB_Y0.IBUFDISABLE.I 38_82 +LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 +LIOB33.IOB_Y0.IFF.INV_OCLK 28_124 LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67 LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72 LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76 @@ -15,8 +17,11 @@ LIOB33.IOB_Y0.INOUT 30_67 LIOB33.IOB_Y0.INTERMDISABLE.I 39_89 LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108 +LIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121 LIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92 @@ -60,8 +65,10 @@ LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127 LIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127 LIOB33.IOB_Y1.IBUFDISABLE.I 39_45 +LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28 +LIOB33.IOB_Y1.IFF.INV_OCLK 29_03 LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60 LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55 LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51 @@ -77,8 +84,11 @@ LIOB33.IOB_Y1.INOUT 31_60 LIOB33.IOB_Y1.INTERMDISABLE.I 38_38 LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19 +LIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06 LIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
diff --git a/kintex7/segbits_liob33.origin_info.db b/kintex7/segbits_liob33.origin_info.db index 27ab2ef..0ab0920 100644 --- a/kintex7/segbits_liob33.origin_info.db +++ b/kintex7/segbits_liob33.origin_info.db
@@ -1,7 +1,9 @@ LIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82 +LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67 LIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99 +LIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 LIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 LIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72 LIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76 @@ -18,7 +20,10 @@ LIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121 +LIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83 LIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_127 39_65 39_95 LIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_125 39_65 39_95 LIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_119 39_65 39_95 @@ -60,9 +65,11 @@ LIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75 LIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109 LIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 +LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60 LIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28 +LIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 LIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 LIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55 LIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51 @@ -80,7 +87,10 @@ LIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09 LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06 +LIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63 LIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
diff --git a/kintex7/segbits_riob33.db b/kintex7/segbits_riob33.db index 96ec3b9..f23f63d 100644 --- a/kintex7/segbits_riob33.db +++ b/kintex7/segbits_riob33.db
@@ -1,6 +1,8 @@ RIOB33.IOB_Y0.IBUFDISABLE.I 38_82 +RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 +RIOB33.IOB_Y0.IFF.INV_OCLK 28_124 RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67 RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72 RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76 @@ -15,8 +17,11 @@ RIOB33.IOB_Y0.INOUT 30_67 RIOB33.IOB_Y0.INTERMDISABLE.I 39_89 RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108 +RIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121 RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 39_117 39_119 !39_125 !39_127 RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92 RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92 @@ -60,8 +65,10 @@ RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_117 !39_119 39_125 39_127 RIOB33.IOB_Y1.IBUFDISABLE.I 39_45 +RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28 +RIOB33.IOB_Y1.IFF.INV_OCLK 29_03 RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60 RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55 RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51 @@ -77,8 +84,11 @@ RIOB33.IOB_Y1.INOUT 31_60 RIOB33.IOB_Y1.INTERMDISABLE.I 38_38 RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19 +RIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
diff --git a/kintex7/segbits_riob33.origin_info.db b/kintex7/segbits_riob33.origin_info.db index 1f70902..f56fd42 100644 --- a/kintex7/segbits_riob33.origin_info.db +++ b/kintex7/segbits_riob33.origin_info.db
@@ -1,7 +1,9 @@ RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82 +RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67 RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99 +RIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72 RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76 @@ -18,7 +20,10 @@ RIOB33.IOB_Y0.INTERMDISABLE.I origin:030-iob 39_89 RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121 +RIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_127 39_65 39_95 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_125 39_65 39_95 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_119 39_65 39_95 @@ -60,9 +65,11 @@ RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75 RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 +RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60 RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28 +RIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 RIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 RIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55 RIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51 @@ -80,7 +87,10 @@ RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09 RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06 +RIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
diff --git a/kintex7/tilegrid.json b/kintex7/tilegrid.json index df741f5..896af4e 100644 --- a/kintex7/tilegrid.json +++ b/kintex7/tilegrid.json
@@ -98556,7 +98556,7 @@ "CMT_TOP_L_LOWER_B_X108Y61": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00020080", + "baseaddr": "0x00401500", "frames": 30, "offset": 0, "words": 101 @@ -98572,7 +98572,7 @@ "CMT_TOP_L_LOWER_B_X108Y9": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00000080", + "baseaddr": "0x00421500", "frames": 30, "offset": 0, "words": 101 @@ -98642,8 +98642,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00421500", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 108, @@ -98658,8 +98658,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00401500", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 108, @@ -98672,7 +98672,7 @@ "CMT_TOP_R_LOWER_B_X8Y113": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00401500", + "baseaddr": "0x00000080", "frames": 30, "offset": 0, "words": 101 @@ -98688,7 +98688,7 @@ "CMT_TOP_R_LOWER_B_X8Y165": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00400080", + "baseaddr": "0x00020080", "frames": 30, "offset": 0, "words": 101 @@ -98704,7 +98704,7 @@ "CMT_TOP_R_LOWER_B_X8Y61": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00420080", + "baseaddr": "0x00400080", "frames": 30, "offset": 0, "words": 101 @@ -98720,7 +98720,7 @@ "CMT_TOP_R_LOWER_B_X8Y9": { "bits": { "CLB_IO_CLK": { - "baseaddr": "0x00421500", + "baseaddr": "0x00420080", "frames": 30, "offset": 0, "words": 101 @@ -98842,8 +98842,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00000080", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 8, @@ -98858,8 +98858,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00020080", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 8, @@ -98874,8 +98874,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00420080", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 8, @@ -98890,8 +98890,8 @@ "CLB_IO_CLK": { "baseaddr": "0x00400080", "frames": 30, - "offset": 0, - "words": 101 + "offset": 75, + "words": 26 } }, "grid_x": 8,
diff --git a/zynq7/mask_liob33.db b/zynq7/mask_liob33.db index fb1e304..2256ff1 100644 --- a/zynq7/mask_liob33.db +++ b/zynq7/mask_liob33.db
@@ -1,8 +1,3 @@ -bit 00_01 -bit 00_02 -bit 00_03 -bit 00_07 -bit 00_09 bit 00_10 bit 00_11 bit 00_14 @@ -12,14 +7,6 @@ bit 00_35 bit 00_38 bit 00_39 -bit 00_42 -bit 00_45 -bit 00_46 -bit 00_65 -bit 00_67 -bit 00_70 -bit 00_71 -bit 00_73 bit 00_75 bit 00_78 bit 00_81 @@ -28,300 +15,93 @@ bit 00_99 bit 00_102 bit 00_103 -bit 00_106 -bit 01_05 -bit 01_06 -bit 01_08 bit 01_09 bit 01_10 bit 01_13 bit 01_14 -bit 01_32 bit 01_33 -bit 01_36 bit 01_37 bit 01_38 bit 01_40 -bit 01_41 -bit 01_45 -bit 01_65 -bit 01_70 bit 01_73 bit 01_74 bit 01_77 bit 01_78 -bit 01_96 bit 01_97 -bit 01_100 bit 01_101 bit 01_102 bit 01_104 -bit 01_105 -bit 02_02 -bit 02_05 -bit 02_06 -bit 02_07 -bit 02_10 -bit 02_11 -bit 02_13 -bit 02_14 -bit 02_15 -bit 02_22 -bit 02_23 -bit 02_26 -bit 02_30 -bit 02_31 -bit 02_42 -bit 02_43 -bit 02_46 -bit 02_47 -bit 02_54 -bit 02_55 -bit 02_58 -bit 02_59 -bit 02_62 -bit 02_63 -bit 02_66 -bit 02_69 -bit 02_70 -bit 02_71 -bit 02_74 -bit 02_77 -bit 02_78 -bit 02_79 -bit 02_86 bit 02_87 -bit 02_94 -bit 02_95 -bit 02_102 -bit 02_106 -bit 02_110 -bit 02_111 -bit 02_118 -bit 02_125 -bit 02_126 -bit 02_127 -bit 03_02 bit 03_04 -bit 03_06 -bit 03_10 -bit 03_12 -bit 03_13 -bit 03_14 -bit 03_29 -bit 03_44 -bit 03_45 -bit 03_53 -bit 03_60 -bit 03_61 -bit 03_66 -bit 03_70 -bit 03_74 -bit 03_77 -bit 03_78 -bit 03_93 -bit 03_110 bit 03_116 -bit 03_125 -bit 03_126 -bit 04_06 -bit 04_07 -bit 04_11 -bit 04_12 -bit 04_13 -bit 04_14 -bit 04_15 -bit 04_19 -bit 04_28 -bit 04_30 -bit 04_44 -bit 04_47 -bit 04_51 -bit 04_55 -bit 04_59 -bit 04_60 -bit 04_61 -bit 04_63 -bit 04_70 -bit 04_71 -bit 04_76 -bit 04_77 -bit 04_78 -bit 04_79 -bit 04_83 -bit 04_87 -bit 04_92 -bit 04_93 -bit 04_94 -bit 04_103 -bit 04_108 -bit 04_111 -bit 04_115 -bit 04_119 -bit 04_124 -bit 04_127 -bit 05_01 -bit 05_02 -bit 05_05 bit 05_07 -bit 05_10 -bit 05_13 -bit 05_17 -bit 05_18 -bit 05_42 -bit 05_49 -bit 05_50 -bit 05_52 -bit 05_53 -bit 05_54 -bit 05_58 -bit 05_60 -bit 05_65 -bit 05_66 -bit 05_69 -bit 05_73 -bit 05_74 -bit 05_76 -bit 05_77 -bit 05_81 -bit 05_82 -bit 05_110 -bit 05_113 -bit 05_114 -bit 05_117 +bit 05_70 +bit 05_86 +bit 05_118 bit 05_119 -bit 05_122 -bit 05_126 -bit 05_127 bit 06_01 -bit 06_02 bit 06_03 -bit 06_04 bit 06_05 -bit 06_06 bit 06_07 -bit 06_10 bit 06_11 -bit 06_12 -bit 06_13 -bit 06_14 -bit 06_15 bit 06_17 -bit 06_22 -bit 06_23 bit 06_27 -bit 06_28 -bit 06_30 -bit 06_31 +bit 06_39 bit 06_43 -bit 06_44 -bit 06_45 -bit 06_46 -bit 06_49 -bit 06_53 -bit 06_57 bit 06_59 -bit 06_60 -bit 06_61 -bit 06_63 bit 06_65 -bit 06_66 -bit 06_68 -bit 06_70 bit 06_71 -bit 06_74 -bit 06_75 -bit 06_76 -bit 06_77 -bit 06_78 -bit 06_79 -bit 06_86 bit 06_87 bit 06_89 bit 06_91 -bit 06_92 -bit 06_93 -bit 06_94 bit 06_103 +bit 06_105 bit 06_107 +bit 06_121 bit 06_123 -bit 06_124 bit 07_00 -bit 07_02 -bit 07_03 bit 07_04 -bit 07_05 bit 07_06 -bit 07_07 bit 07_08 -bit 07_11 -bit 07_13 bit 07_14 -bit 07_15 bit 07_16 -bit 07_19 bit 07_20 bit 07_22 -bit 07_23 bit 07_24 -bit 07_27 bit 07_30 -bit 07_31 bit 07_32 bit 07_36 bit 07_38 bit 07_40 -bit 07_42 -bit 07_43 bit 07_46 -bit 07_47 bit 07_48 -bit 07_51 bit 07_54 -bit 07_55 bit 07_56 bit 07_58 -bit 07_59 -bit 07_62 -bit 07_63 bit 07_64 -bit 07_67 +bit 07_66 bit 07_68 -bit 07_69 bit 07_70 bit 07_71 bit 07_72 -bit 07_75 -bit 07_77 -bit 07_79 bit 07_80 -bit 07_83 bit 07_84 bit 07_86 -bit 07_87 bit 07_88 bit 07_94 -bit 07_95 bit 07_96 bit 07_100 bit 07_102 -bit 07_103 bit 07_104 bit 07_106 -bit 07_107 bit 07_110 -bit 07_111 bit 07_112 -bit 07_115 bit 07_118 bit 07_119 bit 07_120 -bit 07_123 bit 07_126 -bit 07_127 bit 08_00 bit 08_01 -bit 08_02 bit 08_04 bit 08_05 bit 08_07 @@ -329,20 +109,14 @@ bit 08_09 bit 08_10 bit 08_11 -bit 08_12 -bit 08_13 -bit 08_14 bit 08_15 bit 08_16 bit 08_17 -bit 08_18 bit 08_22 bit 08_23 bit 08_24 bit 08_25 -bit 08_27 -bit 08_28 -bit 08_29 +bit 08_26 bit 08_30 bit 08_31 bit 08_32 @@ -352,11 +126,8 @@ bit 08_40 bit 08_41 bit 08_42 -bit 08_43 -bit 08_46 bit 08_47 bit 08_49 -bit 08_53 bit 08_54 bit 08_55 bit 08_56 @@ -367,45 +138,30 @@ bit 08_63 bit 08_64 bit 08_65 -bit 08_66 -bit 08_68 -bit 08_69 -bit 08_70 bit 08_71 bit 08_72 bit 08_73 bit 08_74 bit 08_75 -bit 08_76 -bit 08_77 bit 08_78 bit 08_79 bit 08_80 bit 08_81 -bit 08_82 -bit 08_86 bit 08_87 bit 08_88 bit 08_89 bit 08_90 -bit 08_92 -bit 08_93 -bit 08_94 bit 08_95 -bit 08_96 bit 08_97 -bit 08_100 bit 08_101 bit 08_103 bit 08_104 bit 08_105 bit 08_106 bit 08_107 -bit 08_110 bit 08_111 bit 08_112 bit 08_113 -bit 08_117 bit 08_118 bit 08_119 bit 08_120 @@ -414,92 +170,50 @@ bit 08_123 bit 08_126 bit 08_127 -bit 09_00 -bit 09_01 bit 09_02 bit 09_03 bit 09_04 bit 09_05 -bit 09_06 -bit 09_07 -bit 09_08 -bit 09_11 -bit 09_13 -bit 09_15 -bit 09_16 bit 09_19 bit 09_20 bit 09_21 -bit 09_22 -bit 09_23 -bit 09_24 -bit 09_27 bit 09_34 bit 09_35 bit 09_36 bit 09_37 -bit 09_40 -bit 09_41 -bit 09_47 -bit 09_48 -bit 09_50 bit 09_51 bit 09_52 -bit 09_53 -bit 09_56 -bit 09_57 bit 09_58 -bit 09_59 -bit 09_63 -bit 09_64 -bit 09_65 bit 09_66 bit 09_67 bit 09_68 bit 09_69 bit 09_75 -bit 09_77 -bit 09_79 -bit 09_80 bit 09_82 bit 09_83 +bit 09_84 +bit 09_89 bit 09_91 +bit 09_98 bit 09_99 bit 09_100 -bit 09_106 bit 09_107 -bit 09_111 bit 09_114 bit 09_115 bit 09_116 -bit 09_120 -bit 09_121 -bit 09_122 -bit 09_123 -bit 09_127 -bit 10_00 bit 10_01 bit 10_02 -bit 10_03 bit 10_05 -bit 10_06 bit 10_07 bit 10_09 bit 10_10 -bit 10_11 -bit 10_12 -bit 10_14 bit 10_15 -bit 10_16 +bit 10_17 bit 10_18 -bit 10_19 bit 10_21 bit 10_23 bit 10_25 bit 10_26 -bit 10_27 -bit 10_28 -bit 10_30 bit 10_31 bit 10_33 bit 10_34 @@ -507,9 +221,6 @@ bit 10_39 bit 10_41 bit 10_42 -bit 10_43 -bit 10_44 -bit 10_46 bit 10_47 bit 10_50 bit 10_52 @@ -518,152 +229,92 @@ bit 10_56 bit 10_57 bit 10_58 -bit 10_59 -bit 10_60 bit 10_63 -bit 10_64 bit 10_65 bit 10_66 -bit 10_67 bit 10_69 bit 10_71 bit 10_72 bit 10_73 bit 10_74 -bit 10_75 -bit 10_76 -bit 10_78 bit 10_79 -bit 10_80 bit 10_81 bit 10_82 -bit 10_83 bit 10_87 bit 10_88 bit 10_89 -bit 10_90 -bit 10_91 -bit 10_92 -bit 10_94 bit 10_95 +bit 10_97 bit 10_98 bit 10_101 bit 10_103 bit 10_104 bit 10_105 -bit 10_106 -bit 10_107 -bit 10_110 bit 10_111 bit 10_114 -bit 10_115 bit 10_117 bit 10_119 bit 10_120 bit 10_121 -bit 10_122 bit 10_127 bit 11_01 -bit 11_02 -bit 11_03 -bit 11_04 bit 11_05 bit 11_07 -bit 11_08 -bit 11_09 -bit 11_10 -bit 11_13 bit 11_15 bit 11_17 -bit 11_18 -bit 11_19 bit 11_20 bit 11_21 bit 11_23 -bit 11_24 bit 11_25 -bit 11_26 bit 11_27 bit 11_31 bit 11_33 -bit 11_36 -bit 11_37 bit 11_39 -bit 11_40 bit 11_41 -bit 11_42 bit 11_43 bit 11_47 bit 11_49 -bit 11_50 bit 11_52 -bit 11_53 bit 11_55 -bit 11_56 bit 11_57 -bit 11_58 bit 11_59 -bit 11_60 bit 11_63 bit 11_65 -bit 11_66 -bit 11_67 -bit 11_68 -bit 11_69 bit 11_71 -bit 11_73 -bit 11_74 bit 11_75 -bit 11_77 bit 11_79 bit 11_81 -bit 11_82 -bit 11_83 bit 11_87 -bit 11_89 -bit 11_90 bit 11_91 bit 11_95 bit 11_97 +bit 11_98 bit 11_100 bit 11_101 bit 11_103 bit 11_105 -bit 11_106 bit 11_107 bit 11_111 bit 11_113 bit 11_116 -bit 11_117 bit 11_119 -bit 11_121 -bit 11_122 bit 11_123 -bit 11_125 bit 11_127 bit 12_01 bit 12_02 -bit 12_03 bit 12_04 bit 12_05 bit 12_07 bit 12_09 bit 12_10 -bit 12_11 -bit 12_13 -bit 12_14 bit 12_15 -bit 12_16 bit 12_17 -bit 12_19 bit 12_20 bit 12_21 bit 12_23 bit 12_25 bit 12_26 bit 12_27 -bit 12_29 -bit 12_30 bit 12_31 bit 12_33 bit 12_34 @@ -672,50 +323,39 @@ bit 12_41 bit 12_42 bit 12_43 -bit 12_46 bit 12_47 bit 12_49 -bit 12_50 bit 12_52 bit 12_53 bit 12_55 bit 12_57 bit 12_58 bit 12_59 -bit 12_62 bit 12_63 -bit 12_64 bit 12_65 bit 12_67 bit 12_69 bit 12_71 bit 12_73 -bit 12_74 bit 12_75 -bit 12_77 -bit 12_78 bit 12_79 bit 12_81 bit 12_82 -bit 12_83 bit 12_87 +bit 12_88 bit 12_89 bit 12_90 bit 12_91 -bit 12_94 bit 12_95 bit 12_97 bit 12_98 bit 12_101 -bit 12_103 bit 12_105 bit 12_106 bit 12_107 -bit 12_110 bit 12_111 bit 12_113 bit 12_114 -bit 12_115 bit 12_117 bit 12_119 bit 12_121 @@ -725,77 +365,53 @@ bit 13_00 bit 13_01 bit 13_02 -bit 13_03 -bit 13_04 bit 13_05 bit 13_06 bit 13_07 -bit 13_08 bit 13_09 -bit 13_10 -bit 13_12 -bit 13_13 -bit 13_14 +bit 13_11 bit 13_15 bit 13_16 bit 13_17 bit 13_18 -bit 13_19 bit 13_20 -bit 13_22 bit 13_23 -bit 13_24 bit 13_25 -bit 13_26 -bit 13_30 bit 13_31 bit 13_33 bit 13_34 bit 13_36 +bit 13_38 bit 13_39 -bit 13_40 bit 13_41 -bit 13_42 -bit 13_44 -bit 13_46 bit 13_47 -bit 13_48 bit 13_49 bit 13_50 bit 13_52 bit 13_55 bit 13_56 bit 13_57 -bit 13_58 bit 13_59 -bit 13_60 -bit 13_62 bit 13_63 bit 13_64 bit 13_65 bit 13_66 bit 13_68 -bit 13_69 bit 13_70 bit 13_71 +bit 13_72 bit 13_73 bit 13_74 bit 13_75 -bit 13_76 -bit 13_77 -bit 13_78 bit 13_79 -bit 13_80 bit 13_81 bit 13_82 -bit 13_83 bit 13_86 bit 13_87 bit 13_88 bit 13_89 bit 13_90 -bit 13_92 -bit 13_94 +bit 13_91 bit 13_95 bit 13_97 bit 13_98 @@ -807,7 +423,6 @@ bit 13_105 bit 13_106 bit 13_107 -bit 13_110 bit 13_111 bit 13_113 bit 13_114 @@ -815,90 +430,42 @@ bit 13_119 bit 13_120 bit 13_121 -bit 13_122 -bit 13_123 -bit 13_126 bit 13_127 -bit 14_00 -bit 14_01 bit 14_02 -bit 14_03 bit 14_04 -bit 14_07 -bit 14_09 bit 14_10 -bit 14_11 -bit 14_12 -bit 14_13 -bit 14_14 -bit 14_15 -bit 14_16 bit 14_18 -bit 14_19 bit 14_20 -bit 14_23 bit 14_26 -bit 14_29 -bit 14_30 -bit 14_31 bit 14_34 bit 14_36 bit 14_42 -bit 14_46 bit 14_50 bit 14_52 -bit 14_56 bit 14_58 -bit 14_60 -bit 14_64 bit 14_66 -bit 14_67 bit 14_68 -bit 14_69 -bit 14_71 -bit 14_73 bit 14_74 -bit 14_77 -bit 14_78 -bit 14_79 bit 14_82 -bit 14_83 -bit 14_87 +bit 14_84 bit 14_88 -bit 14_89 -bit 14_90 -bit 14_93 -bit 14_94 -bit 14_95 bit 14_98 bit 14_100 -bit 14_106 +bit 14_104 bit 14_114 bit 14_116 -bit 14_122 -bit 15_00 +bit 14_120 bit 15_01 -bit 15_02 -bit 15_03 bit 15_05 bit 15_07 bit 15_09 -bit 15_10 -bit 15_12 -bit 15_13 -bit 15_14 +bit 15_11 bit 15_15 -bit 15_16 bit 15_17 -bit 15_18 -bit 15_19 bit 15_21 bit 15_23 bit 15_25 -bit 15_26 bit 15_27 -bit 15_28 -bit 15_30 bit 15_31 bit 15_33 bit 15_37 @@ -911,32 +478,17 @@ bit 15_57 bit 15_59 bit 15_63 -bit 15_64 bit 15_65 -bit 15_66 -bit 15_67 -bit 15_68 bit 15_69 bit 15_71 -bit 15_72 bit 15_73 -bit 15_74 bit 15_75 -bit 15_76 -bit 15_77 -bit 15_78 bit 15_79 -bit 15_80 bit 15_81 -bit 15_82 bit 15_85 bit 15_87 bit 15_89 -bit 15_90 bit 15_91 -bit 15_92 -bit 15_93 -bit 15_94 bit 15_95 bit 15_97 bit 15_101 @@ -945,11 +497,9 @@ bit 15_107 bit 15_111 bit 15_113 -bit 15_117 bit 15_119 bit 15_121 bit 15_123 -bit 15_125 bit 15_127 bit 16_02 bit 16_06 @@ -962,8 +512,6 @@ bit 16_24 bit 16_30 bit 16_31 -bit 16_32 -bit 16_35 bit 16_38 bit 16_40 bit 16_42 @@ -972,7 +520,6 @@ bit 16_46 bit 16_47 bit 16_48 -bit 16_51 bit 16_54 bit 16_56 bit 16_57 @@ -990,7 +537,6 @@ bit 16_88 bit 16_94 bit 16_95 -bit 16_99 bit 16_102 bit 16_104 bit 16_106 @@ -999,7 +545,6 @@ bit 16_110 bit 16_111 bit 16_112 -bit 16_115 bit 16_118 bit 16_120 bit 16_121 @@ -1019,7 +564,6 @@ bit 17_30 bit 17_31 bit 17_32 -bit 17_35 bit 17_38 bit 17_39 bit 17_40 @@ -1029,7 +573,6 @@ bit 17_46 bit 17_47 bit 17_48 -bit 17_51 bit 17_54 bit 17_55 bit 17_56 @@ -1042,14 +585,11 @@ bit 17_71 bit 17_73 bit 17_79 -bit 17_80 bit 17_85 bit 17_86 bit 17_87 -bit 17_88 bit 17_94 bit 17_95 -bit 17_99 bit 17_102 bit 17_103 bit 17_104 @@ -1059,7 +599,6 @@ bit 17_110 bit 17_111 bit 17_112 -bit 17_115 bit 17_118 bit 17_120 bit 17_121 @@ -1070,15 +609,14 @@ bit 18_06 bit 18_07 bit 18_08 +bit 18_09 bit 18_14 -bit 18_17 bit 18_20 bit 18_22 bit 18_23 bit 18_25 bit 18_30 bit 18_31 -bit 18_34 bit 18_38 bit 18_39 bit 18_42 @@ -1087,7 +625,6 @@ bit 18_46 bit 18_47 bit 18_49 -bit 18_50 bit 18_54 bit 18_55 bit 18_56 @@ -1106,24 +643,23 @@ bit 18_94 bit 18_95 bit 18_97 -bit 18_98 bit 18_102 bit 18_103 +bit 18_105 bit 18_106 bit 18_107 bit 18_109 bit 18_110 bit 18_111 bit 18_113 -bit 18_114 bit 18_119 bit 18_120 bit 18_121 bit 18_123 bit 18_125 bit 18_127 -bit 19_01 bit 19_03 +bit 19_06 bit 19_07 bit 19_08 bit 19_14 @@ -1134,7 +670,6 @@ bit 19_30 bit 19_31 bit 19_33 -bit 19_34 bit 19_38 bit 19_39 bit 19_41 @@ -1144,8 +679,6 @@ bit 19_46 bit 19_47 bit 19_49 -bit 19_50 -bit 19_54 bit 19_55 bit 19_56 bit 19_57 @@ -1164,7 +697,6 @@ bit 19_94 bit 19_95 bit 19_97 -bit 19_98 bit 19_102 bit 19_103 bit 19_106 @@ -1173,19 +705,15 @@ bit 19_110 bit 19_111 bit 19_113 -bit 19_114 bit 19_119 bit 19_120 bit 19_121 bit 19_123 bit 19_125 bit 19_127 -bit 20_01 bit 20_02 -bit 20_05 bit 20_06 bit 20_09 -bit 20_13 bit 20_21 bit 20_22 bit 20_30 @@ -1195,18 +723,13 @@ bit 20_44 bit 20_46 bit 20_54 -bit 20_55 bit 20_57 bit 20_58 bit 20_60 bit 20_62 -bit 20_65 bit 20_66 -bit 20_69 bit 20_70 bit 20_73 -bit 20_77 -bit 20_84 bit 20_85 bit 20_86 bit 20_94 @@ -1216,55 +739,43 @@ bit 20_108 bit 20_110 bit 20_118 -bit 20_119 bit 20_121 bit 20_122 bit 20_124 bit 20_126 +bit 21_02 bit 21_06 bit 21_09 -bit 21_20 bit 21_21 bit 21_22 bit 21_30 -bit 21_34 -bit 21_35 bit 21_38 bit 21_42 bit 21_43 bit 21_44 bit 21_46 -bit 21_51 -bit 21_52 bit 21_54 bit 21_57 bit 21_58 bit 21_60 bit 21_62 bit 21_66 -bit 21_69 bit 21_70 bit 21_73 -bit 21_84 bit 21_85 bit 21_86 bit 21_94 -bit 21_98 -bit 21_99 bit 21_102 bit 21_106 bit 21_107 bit 21_108 bit 21_110 -bit 21_115 -bit 21_116 bit 21_118 bit 21_121 bit 21_122 bit 21_126 bit 22_02 bit 22_06 -bit 22_07 bit 22_09 bit 22_15 bit 22_21 @@ -1273,7 +784,6 @@ bit 22_30 bit 22_31 bit 22_32 -bit 22_35 bit 22_38 bit 22_40 bit 22_42 @@ -1282,8 +792,8 @@ bit 22_46 bit 22_47 bit 22_48 -bit 22_51 bit 22_54 +bit 22_56 bit 22_57 bit 22_58 bit 22_60 @@ -1298,8 +808,6 @@ bit 22_87 bit 22_94 bit 22_95 -bit 22_96 -bit 22_99 bit 22_102 bit 22_106 bit 22_107 @@ -1307,7 +815,6 @@ bit 22_110 bit 22_111 bit 22_112 -bit 22_115 bit 22_118 bit 22_121 bit 22_122 @@ -1326,9 +833,7 @@ bit 23_30 bit 23_31 bit 23_32 -bit 23_35 bit 23_38 -bit 23_39 bit 23_40 bit 23_42 bit 23_43 @@ -1336,9 +841,7 @@ bit 23_46 bit 23_47 bit 23_48 -bit 23_51 bit 23_54 -bit 23_55 bit 23_56 bit 23_57 bit 23_58 @@ -1349,17 +852,12 @@ bit 23_71 bit 23_73 bit 23_79 -bit 23_80 bit 23_85 bit 23_86 bit 23_87 -bit 23_88 bit 23_94 bit 23_95 -bit 23_96 -bit 23_99 bit 23_102 -bit 23_103 bit 23_104 bit 23_106 bit 23_107 @@ -1367,20 +865,17 @@ bit 23_110 bit 23_111 bit 23_112 -bit 23_115 bit 23_118 bit 23_120 bit 23_121 bit 23_122 bit 23_124 bit 23_126 -bit 24_01 bit 24_02 -bit 24_05 bit 24_06 bit 24_07 +bit 24_08 bit 24_09 -bit 24_13 bit 24_15 bit 24_16 bit 24_21 @@ -1390,7 +885,6 @@ bit 24_30 bit 24_31 bit 24_32 -bit 24_35 bit 24_38 bit 24_39 bit 24_40 @@ -1400,7 +894,6 @@ bit 24_46 bit 24_47 bit 24_48 -bit 24_51 bit 24_54 bit 24_55 bit 24_56 @@ -1408,24 +901,18 @@ bit 24_58 bit 24_60 bit 24_62 -bit 24_65 bit 24_66 -bit 24_69 bit 24_70 bit 24_71 bit 24_73 -bit 24_77 bit 24_79 bit 24_80 -bit 24_84 bit 24_85 bit 24_86 bit 24_87 -bit 24_88 bit 24_94 bit 24_95 bit 24_96 -bit 24_99 bit 24_102 bit 24_103 bit 24_104 @@ -1435,9 +922,7 @@ bit 24_110 bit 24_111 bit 24_112 -bit 24_115 bit 24_118 -bit 24_119 bit 24_120 bit 24_121 bit 24_122 @@ -1472,7 +957,6 @@ bit 25_51 bit 25_52 bit 25_54 -bit 25_55 bit 25_56 bit 25_57 bit 25_58 @@ -1559,12 +1043,18 @@ bit 28_64 bit 28_67 bit 28_72 +bit 28_75 bit 28_76 bit 28_77 +bit 28_79 +bit 28_81 bit 28_83 bit 28_86 +bit 28_89 bit 28_93 bit 28_94 +bit 28_95 +bit 28_97 bit 28_110 bit 28_111 bit 28_116 @@ -1579,12 +1069,18 @@ bit 29_11 bit 29_16 bit 29_17 +bit 29_30 +bit 29_32 bit 29_33 bit 29_34 +bit 29_38 bit 29_41 bit 29_44 +bit 29_46 +bit 29_48 bit 29_50 bit 29_51 +bit 29_52 bit 29_55 bit 29_60 bit 29_63 @@ -1617,13 +1113,19 @@ bit 30_25 bit 30_27 bit 30_29 +bit 30_30 +bit 30_32 bit 30_34 bit 30_35 bit 30_37 +bit 30_38 bit 30_41 bit 30_44 +bit 30_46 +bit 30_48 bit 30_50 bit 30_51 +bit 30_52 bit 30_60 bit 30_67 bit 30_71 @@ -1658,13 +1160,19 @@ bit 31_56 bit 31_60 bit 31_67 +bit 31_75 bit 31_76 bit 31_77 +bit 31_79 +bit 31_81 bit 31_83 bit 31_86 +bit 31_89 bit 31_90 bit 31_92 bit 31_93 +bit 31_95 +bit 31_97 bit 31_98 bit 31_100 bit 31_102 @@ -1694,7 +1202,6 @@ bit 32_66 bit 32_70 bit 32_72 -bit 32_73 bit 32_82 bit 32_90 bit 32_94 @@ -1705,7 +1212,6 @@ bit 33_33 bit 33_37 bit 33_45 -bit 33_54 bit 33_55 bit 33_57 bit 33_61 @@ -1721,18 +1227,6 @@ bit 33_97 bit 33_107 bit 33_111 -bit 34_72 -bit 34_94 -bit 34_100 -bit 34_108 -bit 34_114 -bit 34_120 -bit 35_07 -bit 35_13 -bit 35_19 -bit 35_27 -bit 35_33 -bit 35_55 bit 38_00 bit 38_02 bit 38_08
diff --git a/zynq7/mask_riob33.db b/zynq7/mask_riob33.db index 6461e8c..201cc9b 100644 --- a/zynq7/mask_riob33.db +++ b/zynq7/mask_riob33.db
@@ -1,8 +1,3 @@ -bit 00_01 -bit 00_02 -bit 00_03 -bit 00_07 -bit 00_09 bit 00_10 bit 00_11 bit 00_14 @@ -12,14 +7,6 @@ bit 00_35 bit 00_38 bit 00_39 -bit 00_42 -bit 00_45 -bit 00_46 -bit 00_65 -bit 00_67 -bit 00_70 -bit 00_71 -bit 00_73 bit 00_75 bit 00_78 bit 00_81 @@ -28,300 +15,93 @@ bit 00_99 bit 00_102 bit 00_103 -bit 00_106 -bit 01_05 -bit 01_06 -bit 01_08 bit 01_09 bit 01_10 bit 01_13 bit 01_14 -bit 01_32 bit 01_33 -bit 01_36 bit 01_37 bit 01_38 bit 01_40 -bit 01_41 -bit 01_45 -bit 01_65 -bit 01_70 bit 01_73 bit 01_74 bit 01_77 bit 01_78 -bit 01_96 bit 01_97 -bit 01_100 bit 01_101 bit 01_102 bit 01_104 -bit 01_105 -bit 02_02 -bit 02_05 -bit 02_06 -bit 02_07 -bit 02_10 -bit 02_11 -bit 02_13 -bit 02_14 -bit 02_15 -bit 02_22 -bit 02_23 -bit 02_26 -bit 02_30 -bit 02_31 -bit 02_42 -bit 02_43 -bit 02_46 -bit 02_47 -bit 02_54 -bit 02_55 -bit 02_58 -bit 02_59 -bit 02_62 -bit 02_63 -bit 02_66 -bit 02_69 -bit 02_70 -bit 02_71 -bit 02_74 -bit 02_77 -bit 02_78 -bit 02_79 -bit 02_86 bit 02_87 -bit 02_94 -bit 02_95 -bit 02_102 -bit 02_106 -bit 02_110 -bit 02_111 -bit 02_118 -bit 02_125 -bit 02_126 -bit 02_127 -bit 03_02 bit 03_04 -bit 03_06 -bit 03_10 -bit 03_12 -bit 03_13 -bit 03_14 -bit 03_29 -bit 03_44 -bit 03_45 -bit 03_53 -bit 03_60 -bit 03_61 -bit 03_66 -bit 03_70 -bit 03_74 -bit 03_77 -bit 03_78 -bit 03_93 -bit 03_110 bit 03_116 -bit 03_125 -bit 03_126 -bit 04_06 -bit 04_07 -bit 04_11 -bit 04_12 -bit 04_13 -bit 04_14 -bit 04_15 -bit 04_19 -bit 04_28 -bit 04_30 -bit 04_44 -bit 04_47 -bit 04_51 -bit 04_55 -bit 04_59 -bit 04_60 -bit 04_61 -bit 04_63 -bit 04_70 -bit 04_71 -bit 04_76 -bit 04_77 -bit 04_78 -bit 04_79 -bit 04_83 -bit 04_87 -bit 04_92 -bit 04_93 -bit 04_94 -bit 04_103 -bit 04_108 -bit 04_111 -bit 04_115 -bit 04_119 -bit 04_124 -bit 04_127 -bit 05_01 -bit 05_02 -bit 05_05 bit 05_07 -bit 05_10 -bit 05_13 -bit 05_17 -bit 05_18 -bit 05_42 -bit 05_49 -bit 05_50 -bit 05_52 -bit 05_53 -bit 05_54 -bit 05_58 -bit 05_60 -bit 05_65 -bit 05_66 -bit 05_69 -bit 05_73 -bit 05_74 -bit 05_76 -bit 05_77 -bit 05_81 -bit 05_82 -bit 05_110 -bit 05_113 -bit 05_114 -bit 05_117 +bit 05_70 +bit 05_86 +bit 05_118 bit 05_119 -bit 05_122 -bit 05_126 -bit 05_127 bit 06_01 -bit 06_02 bit 06_03 -bit 06_04 bit 06_05 -bit 06_06 bit 06_07 -bit 06_10 bit 06_11 -bit 06_12 -bit 06_13 -bit 06_14 -bit 06_15 bit 06_17 -bit 06_22 -bit 06_23 bit 06_27 -bit 06_28 -bit 06_30 -bit 06_31 +bit 06_39 bit 06_43 -bit 06_44 -bit 06_45 -bit 06_46 -bit 06_49 -bit 06_53 -bit 06_57 bit 06_59 -bit 06_60 -bit 06_61 -bit 06_63 bit 06_65 -bit 06_66 -bit 06_68 -bit 06_70 bit 06_71 -bit 06_74 -bit 06_75 -bit 06_76 -bit 06_77 -bit 06_78 -bit 06_79 -bit 06_86 bit 06_87 bit 06_89 bit 06_91 -bit 06_92 -bit 06_93 -bit 06_94 bit 06_103 +bit 06_105 bit 06_107 +bit 06_121 bit 06_123 -bit 06_124 bit 07_00 -bit 07_02 -bit 07_03 bit 07_04 -bit 07_05 bit 07_06 -bit 07_07 bit 07_08 -bit 07_11 -bit 07_13 bit 07_14 -bit 07_15 bit 07_16 -bit 07_19 bit 07_20 bit 07_22 -bit 07_23 bit 07_24 -bit 07_27 bit 07_30 -bit 07_31 bit 07_32 bit 07_36 bit 07_38 bit 07_40 -bit 07_42 -bit 07_43 bit 07_46 -bit 07_47 bit 07_48 -bit 07_51 bit 07_54 -bit 07_55 bit 07_56 bit 07_58 -bit 07_59 -bit 07_62 -bit 07_63 bit 07_64 -bit 07_67 +bit 07_66 bit 07_68 -bit 07_69 bit 07_70 bit 07_71 bit 07_72 -bit 07_75 -bit 07_77 -bit 07_79 bit 07_80 -bit 07_83 bit 07_84 bit 07_86 -bit 07_87 bit 07_88 bit 07_94 -bit 07_95 bit 07_96 bit 07_100 bit 07_102 -bit 07_103 bit 07_104 bit 07_106 -bit 07_107 bit 07_110 -bit 07_111 bit 07_112 -bit 07_115 bit 07_118 bit 07_119 bit 07_120 -bit 07_123 bit 07_126 -bit 07_127 bit 08_00 bit 08_01 -bit 08_02 bit 08_04 bit 08_05 bit 08_07 @@ -329,20 +109,14 @@ bit 08_09 bit 08_10 bit 08_11 -bit 08_12 -bit 08_13 -bit 08_14 bit 08_15 bit 08_16 bit 08_17 -bit 08_18 bit 08_22 bit 08_23 bit 08_24 bit 08_25 -bit 08_27 -bit 08_28 -bit 08_29 +bit 08_26 bit 08_30 bit 08_31 bit 08_32 @@ -352,11 +126,8 @@ bit 08_40 bit 08_41 bit 08_42 -bit 08_43 -bit 08_46 bit 08_47 bit 08_49 -bit 08_53 bit 08_54 bit 08_55 bit 08_56 @@ -367,45 +138,30 @@ bit 08_63 bit 08_64 bit 08_65 -bit 08_66 -bit 08_68 -bit 08_69 -bit 08_70 bit 08_71 bit 08_72 bit 08_73 bit 08_74 bit 08_75 -bit 08_76 -bit 08_77 bit 08_78 bit 08_79 bit 08_80 bit 08_81 -bit 08_82 -bit 08_86 bit 08_87 bit 08_88 bit 08_89 bit 08_90 -bit 08_92 -bit 08_93 -bit 08_94 bit 08_95 -bit 08_96 bit 08_97 -bit 08_100 bit 08_101 bit 08_103 bit 08_104 bit 08_105 bit 08_106 bit 08_107 -bit 08_110 bit 08_111 bit 08_112 bit 08_113 -bit 08_117 bit 08_118 bit 08_119 bit 08_120 @@ -414,92 +170,50 @@ bit 08_123 bit 08_126 bit 08_127 -bit 09_00 -bit 09_01 bit 09_02 bit 09_03 bit 09_04 bit 09_05 -bit 09_06 -bit 09_07 -bit 09_08 -bit 09_11 -bit 09_13 -bit 09_15 -bit 09_16 bit 09_19 bit 09_20 bit 09_21 -bit 09_22 -bit 09_23 -bit 09_24 -bit 09_27 bit 09_34 bit 09_35 bit 09_36 bit 09_37 -bit 09_40 -bit 09_41 -bit 09_47 -bit 09_48 -bit 09_50 bit 09_51 bit 09_52 -bit 09_53 -bit 09_56 -bit 09_57 bit 09_58 -bit 09_59 -bit 09_63 -bit 09_64 -bit 09_65 bit 09_66 bit 09_67 bit 09_68 bit 09_69 bit 09_75 -bit 09_77 -bit 09_79 -bit 09_80 bit 09_82 bit 09_83 +bit 09_84 +bit 09_89 bit 09_91 +bit 09_98 bit 09_99 bit 09_100 -bit 09_106 bit 09_107 -bit 09_111 bit 09_114 bit 09_115 bit 09_116 -bit 09_120 -bit 09_121 -bit 09_122 -bit 09_123 -bit 09_127 -bit 10_00 bit 10_01 bit 10_02 -bit 10_03 bit 10_05 -bit 10_06 bit 10_07 bit 10_09 bit 10_10 -bit 10_11 -bit 10_12 -bit 10_14 bit 10_15 -bit 10_16 +bit 10_17 bit 10_18 -bit 10_19 bit 10_21 bit 10_23 bit 10_25 bit 10_26 -bit 10_27 -bit 10_28 -bit 10_30 bit 10_31 bit 10_33 bit 10_34 @@ -507,9 +221,6 @@ bit 10_39 bit 10_41 bit 10_42 -bit 10_43 -bit 10_44 -bit 10_46 bit 10_47 bit 10_50 bit 10_52 @@ -518,152 +229,92 @@ bit 10_56 bit 10_57 bit 10_58 -bit 10_59 -bit 10_60 bit 10_63 -bit 10_64 bit 10_65 bit 10_66 -bit 10_67 bit 10_69 bit 10_71 bit 10_72 bit 10_73 bit 10_74 -bit 10_75 -bit 10_76 -bit 10_78 bit 10_79 -bit 10_80 bit 10_81 bit 10_82 -bit 10_83 bit 10_87 bit 10_88 bit 10_89 -bit 10_90 -bit 10_91 -bit 10_92 -bit 10_94 bit 10_95 +bit 10_97 bit 10_98 bit 10_101 bit 10_103 bit 10_104 bit 10_105 -bit 10_106 -bit 10_107 -bit 10_110 bit 10_111 bit 10_114 -bit 10_115 bit 10_117 bit 10_119 bit 10_120 bit 10_121 -bit 10_122 bit 10_127 bit 11_01 -bit 11_02 -bit 11_03 -bit 11_04 bit 11_05 bit 11_07 -bit 11_08 -bit 11_09 -bit 11_10 -bit 11_13 bit 11_15 bit 11_17 -bit 11_18 -bit 11_19 bit 11_20 bit 11_21 bit 11_23 -bit 11_24 bit 11_25 -bit 11_26 bit 11_27 bit 11_31 bit 11_33 -bit 11_36 -bit 11_37 bit 11_39 -bit 11_40 bit 11_41 -bit 11_42 bit 11_43 bit 11_47 bit 11_49 -bit 11_50 bit 11_52 -bit 11_53 bit 11_55 -bit 11_56 bit 11_57 -bit 11_58 bit 11_59 -bit 11_60 bit 11_63 bit 11_65 -bit 11_66 -bit 11_67 -bit 11_68 -bit 11_69 bit 11_71 -bit 11_73 -bit 11_74 bit 11_75 -bit 11_77 bit 11_79 bit 11_81 -bit 11_82 -bit 11_83 bit 11_87 -bit 11_89 -bit 11_90 bit 11_91 bit 11_95 bit 11_97 +bit 11_98 bit 11_100 bit 11_101 bit 11_103 bit 11_105 -bit 11_106 bit 11_107 bit 11_111 bit 11_113 bit 11_116 -bit 11_117 bit 11_119 -bit 11_121 -bit 11_122 bit 11_123 -bit 11_125 bit 11_127 bit 12_01 bit 12_02 -bit 12_03 bit 12_04 bit 12_05 bit 12_07 bit 12_09 bit 12_10 -bit 12_11 -bit 12_13 -bit 12_14 bit 12_15 -bit 12_16 bit 12_17 -bit 12_19 bit 12_20 bit 12_21 bit 12_23 bit 12_25 bit 12_26 bit 12_27 -bit 12_29 -bit 12_30 bit 12_31 bit 12_33 bit 12_34 @@ -672,50 +323,39 @@ bit 12_41 bit 12_42 bit 12_43 -bit 12_46 bit 12_47 bit 12_49 -bit 12_50 bit 12_52 bit 12_53 bit 12_55 bit 12_57 bit 12_58 bit 12_59 -bit 12_62 bit 12_63 -bit 12_64 bit 12_65 bit 12_67 bit 12_69 bit 12_71 bit 12_73 -bit 12_74 bit 12_75 -bit 12_77 -bit 12_78 bit 12_79 bit 12_81 bit 12_82 -bit 12_83 bit 12_87 +bit 12_88 bit 12_89 bit 12_90 bit 12_91 -bit 12_94 bit 12_95 bit 12_97 bit 12_98 bit 12_101 -bit 12_103 bit 12_105 bit 12_106 bit 12_107 -bit 12_110 bit 12_111 bit 12_113 bit 12_114 -bit 12_115 bit 12_117 bit 12_119 bit 12_121 @@ -725,77 +365,53 @@ bit 13_00 bit 13_01 bit 13_02 -bit 13_03 -bit 13_04 bit 13_05 bit 13_06 bit 13_07 -bit 13_08 bit 13_09 -bit 13_10 -bit 13_12 -bit 13_13 -bit 13_14 +bit 13_11 bit 13_15 bit 13_16 bit 13_17 bit 13_18 -bit 13_19 bit 13_20 -bit 13_22 bit 13_23 -bit 13_24 bit 13_25 -bit 13_26 -bit 13_30 bit 13_31 bit 13_33 bit 13_34 bit 13_36 +bit 13_38 bit 13_39 -bit 13_40 bit 13_41 -bit 13_42 -bit 13_44 -bit 13_46 bit 13_47 -bit 13_48 bit 13_49 bit 13_50 bit 13_52 bit 13_55 bit 13_56 bit 13_57 -bit 13_58 bit 13_59 -bit 13_60 -bit 13_62 bit 13_63 bit 13_64 bit 13_65 bit 13_66 bit 13_68 -bit 13_69 bit 13_70 bit 13_71 +bit 13_72 bit 13_73 bit 13_74 bit 13_75 -bit 13_76 -bit 13_77 -bit 13_78 bit 13_79 -bit 13_80 bit 13_81 bit 13_82 -bit 13_83 bit 13_86 bit 13_87 bit 13_88 bit 13_89 bit 13_90 -bit 13_92 -bit 13_94 +bit 13_91 bit 13_95 bit 13_97 bit 13_98 @@ -807,7 +423,6 @@ bit 13_105 bit 13_106 bit 13_107 -bit 13_110 bit 13_111 bit 13_113 bit 13_114 @@ -815,90 +430,42 @@ bit 13_119 bit 13_120 bit 13_121 -bit 13_122 -bit 13_123 -bit 13_126 bit 13_127 -bit 14_00 -bit 14_01 bit 14_02 -bit 14_03 bit 14_04 -bit 14_07 -bit 14_09 bit 14_10 -bit 14_11 -bit 14_12 -bit 14_13 -bit 14_14 -bit 14_15 -bit 14_16 bit 14_18 -bit 14_19 bit 14_20 -bit 14_23 bit 14_26 -bit 14_29 -bit 14_30 -bit 14_31 bit 14_34 bit 14_36 bit 14_42 -bit 14_46 bit 14_50 bit 14_52 -bit 14_56 bit 14_58 -bit 14_60 -bit 14_64 bit 14_66 -bit 14_67 bit 14_68 -bit 14_69 -bit 14_71 -bit 14_73 bit 14_74 -bit 14_77 -bit 14_78 -bit 14_79 bit 14_82 -bit 14_83 -bit 14_87 +bit 14_84 bit 14_88 -bit 14_89 -bit 14_90 -bit 14_93 -bit 14_94 -bit 14_95 bit 14_98 bit 14_100 -bit 14_106 +bit 14_104 bit 14_114 bit 14_116 -bit 14_122 -bit 15_00 +bit 14_120 bit 15_01 -bit 15_02 -bit 15_03 bit 15_05 bit 15_07 bit 15_09 -bit 15_10 -bit 15_12 -bit 15_13 -bit 15_14 +bit 15_11 bit 15_15 -bit 15_16 bit 15_17 -bit 15_18 -bit 15_19 bit 15_21 bit 15_23 bit 15_25 -bit 15_26 bit 15_27 -bit 15_28 -bit 15_30 bit 15_31 bit 15_33 bit 15_37 @@ -911,32 +478,17 @@ bit 15_57 bit 15_59 bit 15_63 -bit 15_64 bit 15_65 -bit 15_66 -bit 15_67 -bit 15_68 bit 15_69 bit 15_71 -bit 15_72 bit 15_73 -bit 15_74 bit 15_75 -bit 15_76 -bit 15_77 -bit 15_78 bit 15_79 -bit 15_80 bit 15_81 -bit 15_82 bit 15_85 bit 15_87 bit 15_89 -bit 15_90 bit 15_91 -bit 15_92 -bit 15_93 -bit 15_94 bit 15_95 bit 15_97 bit 15_101 @@ -945,11 +497,9 @@ bit 15_107 bit 15_111 bit 15_113 -bit 15_117 bit 15_119 bit 15_121 bit 15_123 -bit 15_125 bit 15_127 bit 16_02 bit 16_06 @@ -962,8 +512,6 @@ bit 16_24 bit 16_30 bit 16_31 -bit 16_32 -bit 16_35 bit 16_38 bit 16_40 bit 16_42 @@ -972,7 +520,6 @@ bit 16_46 bit 16_47 bit 16_48 -bit 16_51 bit 16_54 bit 16_56 bit 16_57 @@ -990,7 +537,6 @@ bit 16_88 bit 16_94 bit 16_95 -bit 16_99 bit 16_102 bit 16_104 bit 16_106 @@ -999,7 +545,6 @@ bit 16_110 bit 16_111 bit 16_112 -bit 16_115 bit 16_118 bit 16_120 bit 16_121 @@ -1019,7 +564,6 @@ bit 17_30 bit 17_31 bit 17_32 -bit 17_35 bit 17_38 bit 17_39 bit 17_40 @@ -1029,7 +573,6 @@ bit 17_46 bit 17_47 bit 17_48 -bit 17_51 bit 17_54 bit 17_55 bit 17_56 @@ -1042,14 +585,11 @@ bit 17_71 bit 17_73 bit 17_79 -bit 17_80 bit 17_85 bit 17_86 bit 17_87 -bit 17_88 bit 17_94 bit 17_95 -bit 17_99 bit 17_102 bit 17_103 bit 17_104 @@ -1059,7 +599,6 @@ bit 17_110 bit 17_111 bit 17_112 -bit 17_115 bit 17_118 bit 17_120 bit 17_121 @@ -1070,15 +609,14 @@ bit 18_06 bit 18_07 bit 18_08 +bit 18_09 bit 18_14 -bit 18_17 bit 18_20 bit 18_22 bit 18_23 bit 18_25 bit 18_30 bit 18_31 -bit 18_34 bit 18_38 bit 18_39 bit 18_42 @@ -1087,7 +625,6 @@ bit 18_46 bit 18_47 bit 18_49 -bit 18_50 bit 18_54 bit 18_55 bit 18_56 @@ -1106,24 +643,23 @@ bit 18_94 bit 18_95 bit 18_97 -bit 18_98 bit 18_102 bit 18_103 +bit 18_105 bit 18_106 bit 18_107 bit 18_109 bit 18_110 bit 18_111 bit 18_113 -bit 18_114 bit 18_119 bit 18_120 bit 18_121 bit 18_123 bit 18_125 bit 18_127 -bit 19_01 bit 19_03 +bit 19_06 bit 19_07 bit 19_08 bit 19_14 @@ -1134,7 +670,6 @@ bit 19_30 bit 19_31 bit 19_33 -bit 19_34 bit 19_38 bit 19_39 bit 19_41 @@ -1144,8 +679,6 @@ bit 19_46 bit 19_47 bit 19_49 -bit 19_50 -bit 19_54 bit 19_55 bit 19_56 bit 19_57 @@ -1164,7 +697,6 @@ bit 19_94 bit 19_95 bit 19_97 -bit 19_98 bit 19_102 bit 19_103 bit 19_106 @@ -1173,19 +705,15 @@ bit 19_110 bit 19_111 bit 19_113 -bit 19_114 bit 19_119 bit 19_120 bit 19_121 bit 19_123 bit 19_125 bit 19_127 -bit 20_01 bit 20_02 -bit 20_05 bit 20_06 bit 20_09 -bit 20_13 bit 20_21 bit 20_22 bit 20_30 @@ -1195,18 +723,13 @@ bit 20_44 bit 20_46 bit 20_54 -bit 20_55 bit 20_57 bit 20_58 bit 20_60 bit 20_62 -bit 20_65 bit 20_66 -bit 20_69 bit 20_70 bit 20_73 -bit 20_77 -bit 20_84 bit 20_85 bit 20_86 bit 20_94 @@ -1216,55 +739,43 @@ bit 20_108 bit 20_110 bit 20_118 -bit 20_119 bit 20_121 bit 20_122 bit 20_124 bit 20_126 +bit 21_02 bit 21_06 bit 21_09 -bit 21_20 bit 21_21 bit 21_22 bit 21_30 -bit 21_34 -bit 21_35 bit 21_38 bit 21_42 bit 21_43 bit 21_44 bit 21_46 -bit 21_51 -bit 21_52 bit 21_54 bit 21_57 bit 21_58 bit 21_60 bit 21_62 bit 21_66 -bit 21_69 bit 21_70 bit 21_73 -bit 21_84 bit 21_85 bit 21_86 bit 21_94 -bit 21_98 -bit 21_99 bit 21_102 bit 21_106 bit 21_107 bit 21_108 bit 21_110 -bit 21_115 -bit 21_116 bit 21_118 bit 21_121 bit 21_122 bit 21_126 bit 22_02 bit 22_06 -bit 22_07 bit 22_09 bit 22_15 bit 22_21 @@ -1273,7 +784,6 @@ bit 22_30 bit 22_31 bit 22_32 -bit 22_35 bit 22_38 bit 22_40 bit 22_42 @@ -1282,8 +792,8 @@ bit 22_46 bit 22_47 bit 22_48 -bit 22_51 bit 22_54 +bit 22_56 bit 22_57 bit 22_58 bit 22_60 @@ -1298,8 +808,6 @@ bit 22_87 bit 22_94 bit 22_95 -bit 22_96 -bit 22_99 bit 22_102 bit 22_106 bit 22_107 @@ -1307,7 +815,6 @@ bit 22_110 bit 22_111 bit 22_112 -bit 22_115 bit 22_118 bit 22_121 bit 22_122 @@ -1326,9 +833,7 @@ bit 23_30 bit 23_31 bit 23_32 -bit 23_35 bit 23_38 -bit 23_39 bit 23_40 bit 23_42 bit 23_43 @@ -1336,9 +841,7 @@ bit 23_46 bit 23_47 bit 23_48 -bit 23_51 bit 23_54 -bit 23_55 bit 23_56 bit 23_57 bit 23_58 @@ -1349,17 +852,12 @@ bit 23_71 bit 23_73 bit 23_79 -bit 23_80 bit 23_85 bit 23_86 bit 23_87 -bit 23_88 bit 23_94 bit 23_95 -bit 23_96 -bit 23_99 bit 23_102 -bit 23_103 bit 23_104 bit 23_106 bit 23_107 @@ -1367,20 +865,17 @@ bit 23_110 bit 23_111 bit 23_112 -bit 23_115 bit 23_118 bit 23_120 bit 23_121 bit 23_122 bit 23_124 bit 23_126 -bit 24_01 bit 24_02 -bit 24_05 bit 24_06 bit 24_07 +bit 24_08 bit 24_09 -bit 24_13 bit 24_15 bit 24_16 bit 24_21 @@ -1390,7 +885,6 @@ bit 24_30 bit 24_31 bit 24_32 -bit 24_35 bit 24_38 bit 24_39 bit 24_40 @@ -1400,7 +894,6 @@ bit 24_46 bit 24_47 bit 24_48 -bit 24_51 bit 24_54 bit 24_55 bit 24_56 @@ -1408,24 +901,18 @@ bit 24_58 bit 24_60 bit 24_62 -bit 24_65 bit 24_66 -bit 24_69 bit 24_70 bit 24_71 bit 24_73 -bit 24_77 bit 24_79 bit 24_80 -bit 24_84 bit 24_85 bit 24_86 bit 24_87 -bit 24_88 bit 24_94 bit 24_95 bit 24_96 -bit 24_99 bit 24_102 bit 24_103 bit 24_104 @@ -1435,9 +922,7 @@ bit 24_110 bit 24_111 bit 24_112 -bit 24_115 bit 24_118 -bit 24_119 bit 24_120 bit 24_121 bit 24_122 @@ -1472,7 +957,6 @@ bit 25_51 bit 25_52 bit 25_54 -bit 25_55 bit 25_56 bit 25_57 bit 25_58 @@ -1559,12 +1043,18 @@ bit 28_64 bit 28_67 bit 28_72 +bit 28_75 bit 28_76 bit 28_77 +bit 28_79 +bit 28_81 bit 28_83 bit 28_86 +bit 28_89 bit 28_93 bit 28_94 +bit 28_95 +bit 28_97 bit 28_110 bit 28_111 bit 28_116 @@ -1579,12 +1069,18 @@ bit 29_11 bit 29_16 bit 29_17 +bit 29_30 +bit 29_32 bit 29_33 bit 29_34 +bit 29_38 bit 29_41 bit 29_44 +bit 29_46 +bit 29_48 bit 29_50 bit 29_51 +bit 29_52 bit 29_55 bit 29_60 bit 29_63 @@ -1617,13 +1113,19 @@ bit 30_25 bit 30_27 bit 30_29 +bit 30_30 +bit 30_32 bit 30_34 bit 30_35 bit 30_37 +bit 30_38 bit 30_41 bit 30_44 +bit 30_46 +bit 30_48 bit 30_50 bit 30_51 +bit 30_52 bit 30_60 bit 30_67 bit 30_71 @@ -1658,13 +1160,19 @@ bit 31_56 bit 31_60 bit 31_67 +bit 31_75 bit 31_76 bit 31_77 +bit 31_79 +bit 31_81 bit 31_83 bit 31_86 +bit 31_89 bit 31_90 bit 31_92 bit 31_93 +bit 31_95 +bit 31_97 bit 31_98 bit 31_100 bit 31_102
diff --git a/zynq7/segbits_clblm_l.db b/zynq7/segbits_clblm_l.db index 115e380..582dbd1 100644 --- a/zynq7/segbits_clblm_l.db +++ b/zynq7/segbits_clblm_l.db
@@ -610,6 +610,7 @@ CLBLM_L.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62 CLBLM_L.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62 +CLBLM_L.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62 CLBLM_L.SLICEM_X0.DLUT.INIT[00] 34_63 @@ -682,6 +683,7 @@ CLBLM_L.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57 CLBLM_L.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57 CLBLM_L.SLICEM_X0.FFSYNC 00_48
diff --git a/zynq7/segbits_clblm_l.origin_info.db b/zynq7/segbits_clblm_l.origin_info.db index 7ae36ee..5bf41c7 100644 --- a/zynq7/segbits_clblm_l.origin_info.db +++ b/zynq7/segbits_clblm_l.origin_info.db
@@ -613,6 +613,7 @@ CLBLM_L.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 CLBLM_L.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 CLBLM_L.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_L.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 CLBLM_L.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 CLBLM_L.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 @@ -685,6 +686,7 @@ CLBLM_L.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 CLBLM_L.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 CLBLM_L.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_L.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57 CLBLM_L.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 CLBLM_L.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 CLBLM_L.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
diff --git a/zynq7/segbits_clblm_r.db b/zynq7/segbits_clblm_r.db index 95499ca..78fbb06 100644 --- a/zynq7/segbits_clblm_r.db +++ b/zynq7/segbits_clblm_r.db
@@ -610,6 +610,7 @@ CLBLM_R.SLICEM_X0.DFFMUX.CY !30_59 30_60 !30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.DX !30_59 !30_60 30_61 !30_62 CLBLM_R.SLICEM_X0.DFFMUX.XOR !30_59 30_60 !30_61 !30_62 +CLBLM_R.SLICEM_X0.DFFMUX.MC31 !30_59 !30_60 30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O5 30_59 !30_60 !30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O6 30_59 !30_60 !30_61 !30_62 CLBLM_R.SLICEM_X0.DLUT.INIT[00] 34_63 @@ -682,6 +683,7 @@ CLBLM_R.SLICEM_X0.DOUTMUX.CY 30_51 30_52 !30_56 !30_57 CLBLM_R.SLICEM_X0.DOUTMUX.D5Q !30_51 !30_52 !30_56 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.XOR 30_51 !30_52 !30_56 !30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.MC31 30_10 !30_51 30_52 !30_56 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O5 !30_51 30_52 30_56 !30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O6 !30_51 !30_52 30_56 !30_57 CLBLM_R.SLICEM_X0.FFSYNC 00_48
diff --git a/zynq7/segbits_clblm_r.origin_info.db b/zynq7/segbits_clblm_r.origin_info.db index 2bbeb93..4a9cecc 100644 --- a/zynq7/segbits_clblm_r.origin_info.db +++ b/zynq7/segbits_clblm_r.origin_info.db
@@ -613,6 +613,7 @@ CLBLM_R.SLICEM_X0.DFF.ZRST origin:011-clb-ffconfig 30_50 CLBLM_R.SLICEM_X0.DFFMUX.CY origin:015-clb-nffmux !30_59 !30_61 30_60 30_62 CLBLM_R.SLICEM_X0.DFFMUX.DX origin:015-clb-nffmux !30_59 !30_60 !30_62 30_61 +CLBLM_R.SLICEM_X0.DFFMUX.MC31 origin:015-clb-nffmux !30_59 !30_60 30_61 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O5 origin:015-clb-nffmux !30_60 !30_61 30_59 30_62 CLBLM_R.SLICEM_X0.DFFMUX.O6 origin:015-clb-nffmux !30_60 !30_61 !30_62 30_59 CLBLM_R.SLICEM_X0.DFFMUX.XOR origin:015-clb-nffmux !30_59 !30_61 !30_62 30_60 @@ -685,6 +686,7 @@ CLBLM_R.SLICEM_X0.DLUT.SRL origin:018-clb-ram 30_47 CLBLM_R.SLICEM_X0.DOUTMUX.CY origin:016-clb-noutmux !30_56 !30_57 30_51 30_52 CLBLM_R.SLICEM_X0.DOUTMUX.D5Q origin:016-clb-noutmux !30_51 !30_52 !30_56 30_57 +CLBLM_R.SLICEM_X0.DOUTMUX.MC31 origin:016-clb-noutmux !30_51 !30_56 30_10 30_52 30_57 CLBLM_R.SLICEM_X0.DOUTMUX.O5 origin:016-clb-noutmux !30_51 !30_57 30_52 30_56 CLBLM_R.SLICEM_X0.DOUTMUX.O6 origin:016-clb-noutmux !30_51 !30_52 !30_57 30_56 CLBLM_R.SLICEM_X0.DOUTMUX.XOR origin:016-clb-noutmux !30_52 !30_56 !30_57 30_51
diff --git a/zynq7/segbits_cmt_top_l_upper_t.db b/zynq7/segbits_cmt_top_l_upper_t.db new file mode 100644 index 0000000..24a14b5 --- /dev/null +++ b/zynq7/segbits_cmt_top_l_upper_t.db
@@ -0,0 +1,348 @@ +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT 29_10 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT 28_09 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT 29_07 +CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK 29_11 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183 +CMT_TOP_L_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL 28_722 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] 28_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] 29_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] 28_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] 29_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] 28_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] 29_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] 28_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] 29_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] 28_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] 29_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] 28_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] 29_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] 28_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] 29_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] 28_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] 29_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] 28_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] 29_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] 28_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] 29_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] 28_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] 29_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] 28_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] 29_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] 28_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] 29_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] 28_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] 29_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] 28_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] 29_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] 28_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] 29_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] 28_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] 29_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] 28_207 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] 28_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] 29_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] 28_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] 29_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] 28_215 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327 +CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT 28_737 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] 28_634 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] 29_635 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] 28_636 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] 29_637 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] 28_638 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] 29_639 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] 28_628 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] 29_629 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] 28_630 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] 29_631 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN 29_720 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST 28_720 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
diff --git a/zynq7/segbits_cmt_top_l_upper_t.origin_info.db b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db new file mode 100644 index 0000000..9f58535 --- /dev/null +++ b/zynq7/segbits_cmt_top_l_upper_t.origin_info.db
@@ -0,0 +1,348 @@ +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKFBIN.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT origin:034-cmt-pll-pips 29_10 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN1.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT origin:034-cmt-pll-pips 28_09 +CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKIN2.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT origin:034-cmt-pll-pips 29_07 +CMT_TOP_L_UPPER_T.EXTERNAL_FEEDBACK origin:034-cmt-pll-pips 29_11 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_L_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59 +CMT_TOP_L_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43 +CMT_TOP_L_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183 +CMT_TOP_L_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638 +CMT_TOP_L_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639 +CMT_TOP_L_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722 +CMT_TOP_L_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204 +CMT_TOP_L_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_L_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324 +CMT_TOP_L_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324 +CMT_TOP_L_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630 +CMT_TOP_L_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720 +CMT_TOP_L_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
diff --git a/zynq7/segbits_cmt_top_r_upper_t.db b/zynq7/segbits_cmt_top_r_upper_t.db new file mode 100644 index 0000000..480d571 --- /dev/null +++ b/zynq7/segbits_cmt_top_r_upper_t.db
@@ -0,0 +1,344 @@ +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] 28_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] 29_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] 28_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] 29_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] 28_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] 29_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] 28_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] 29_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] 28_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] 29_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] 28_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] 29_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] 28_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] 29_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] 28_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] 29_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] 28_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] 29_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] 28_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] 29_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] 28_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] 29_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] 29_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] 28_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] 29_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] 28_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] 29_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] 28_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] 28_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] 29_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] 28_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] 29_175 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF 28_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL 28_43 29_42 29_43 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF 29_03 29_44 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] 29_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] 28_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] 29_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] 28_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] 29_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] 28_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] 29_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] 28_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] 29_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] 28_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] 29_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] 28_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] 29_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] 28_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] 28_183 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] 29_183 +CMT_TOP_R_UPPER_T.PLLE2.IN_USE 28_05 28_10 28_16 28_42 28_46 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_45 29_46 29_47 29_236 29_249 29_250 29_251 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL 28_722 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] 28_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] 29_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] 28_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] 29_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] 28_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] 29_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] 28_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] 29_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] 28_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] 29_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] 28_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] 29_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] 28_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] 29_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] 28_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] 29_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] 28_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] 29_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] 28_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] 29_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] 28_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] 29_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] 28_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] 29_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] 28_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] 29_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] 28_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] 29_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] 28_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] 29_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] 28_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] 29_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] 28_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] 29_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] 28_207 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] 28_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] 29_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] 28_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] 29_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] 28_215 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] 28_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] 29_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] 28_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] 29_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] 28_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] 29_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] 28_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] 29_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] 28_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] 29_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] 28_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] 29_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] 28_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] 29_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] 28_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] 29_327 +CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT 28_737 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] 28_634 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] 29_635 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] 28_636 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] 29_637 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] 28_638 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] 29_639 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] 28_628 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] 29_629 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] 28_630 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] 29_631 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN 29_720 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST 28_720 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] 28_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] 29_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] 28_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] 29_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] 28_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] 29_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] 28_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] 29_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] 28_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] 29_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] 28_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] 29_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] 28_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] 29_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] 28_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] 29_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] 28_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] 29_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] 28_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] 29_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] 28_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] 29_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] 29_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] 28_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] 29_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] 28_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] 29_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] 28_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] 28_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] 29_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] 28_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] 29_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] 28_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] 29_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] 28_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] 29_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] 28_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] 29_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] 28_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] 29_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] 28_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] 29_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] 28_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] 29_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] 28_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] 29_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] 28_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] 29_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] 28_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] 29_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] 28_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] 29_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] 28_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] 29_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] 29_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] 28_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] 29_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] 28_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] 29_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] 28_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] 28_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] 29_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] 28_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] 29_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] 28_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] 29_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] 28_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] 29_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] 28_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] 29_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] 28_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] 29_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] 28_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] 29_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] 28_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] 29_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] 28_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] 29_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] 28_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] 29_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] 28_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] 29_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] 28_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] 29_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] 28_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] 29_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] 29_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] 28_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] 29_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] 28_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] 29_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] 28_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] 28_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] 29_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] 28_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] 29_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] 28_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] 29_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] 28_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] 29_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] 28_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] 29_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] 28_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] 29_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] 28_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] 29_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] 28_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] 29_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] 28_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] 29_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] 28_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] 29_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] 28_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] 29_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] 28_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] 29_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] 28_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] 29_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] 29_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] 28_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] 29_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] 28_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] 29_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] 28_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] 28_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] 29_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] 28_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] 29_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] 28_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] 29_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] 28_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] 29_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] 28_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] 29_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] 28_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] 29_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] 28_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] 29_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] 28_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] 29_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] 28_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] 29_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] 28_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] 29_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] 28_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] 29_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] 28_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] 29_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] 28_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] 29_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] 29_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] 28_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] 29_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] 28_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] 29_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] 28_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] 28_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] 29_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] 28_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] 29_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] 28_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] 29_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] 28_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] 29_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] 28_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] 29_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] 28_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] 29_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] 28_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] 29_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] 28_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] 29_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] 28_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] 29_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] 28_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] 29_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] 28_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] 29_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] 28_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] 29_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] 28_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] 29_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] 29_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] 28_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] 29_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] 28_63 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] 29_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] 28_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] 28_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] 29_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] 28_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] 29_63 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] 28_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] 29_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] 28_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] 29_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] 28_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] 29_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] 28_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] 29_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] 29_628 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] 28_629 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] 29_630 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] 28_631 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] 28_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] 29_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] 28_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] 29_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] 29_634 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] 28_635 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] 29_636 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] 28_637 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] 29_638 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] 28_639 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] 28_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] 29_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] 28_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] 29_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] 28_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] 29_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] 29_207 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] 29_215
diff --git a/zynq7/segbits_cmt_top_r_upper_t.origin_info.db b/zynq7/segbits_cmt_top_r_upper_t.origin_info.db new file mode 100644 index 0000000..98dc615 --- /dev/null +++ b/zynq7/segbits_cmt_top_r_upper_t.origin_info.db
@@ -0,0 +1,344 @@ +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_163 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_164 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_165 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_160 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_161 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_162 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_166 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_167 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_168 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_169 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_170 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_174 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_173 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[0] origin:032-cmt-pll 28_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_MX[1] origin:032-cmt-pll 29_172 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_171 +CMT_TOP_R_UPPER_T.PLLE2.CLKFBOUT_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_175 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_67 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_68 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_69 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_64 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_65 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_66 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_70 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_71 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_72 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_73 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_74 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_78 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_77 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[0] origin:032-cmt-pll 28_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_MX[1] origin:032-cmt-pll 29_76 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_75 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT0_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_79 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_83 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_84 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_85 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_80 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_81 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_82 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_86 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_87 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_88 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_89 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_90 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_94 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_93 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[0] origin:032-cmt-pll 28_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_MX[1] origin:032-cmt-pll 29_92 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_91 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT1_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_95 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_99 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_100 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_101 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_96 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_97 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_98 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_102 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_103 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_104 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_105 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_106 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_110 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_109 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[0] origin:032-cmt-pll 28_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_MX[1] origin:032-cmt-pll 29_108 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_107 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT2_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_111 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_115 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_116 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_117 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_112 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_113 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_114 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_118 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_119 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_120 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_121 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_122 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_126 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_125 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[0] origin:032-cmt-pll 28_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_MX[1] origin:032-cmt-pll 29_124 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_123 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT3_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_127 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_131 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_132 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_133 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_128 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_129 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_130 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_134 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_135 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_136 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_137 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_138 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_142 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_141 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[0] origin:032-cmt-pll 28_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_MX[1] origin:032-cmt-pll 29_140 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_139 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT4_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_143 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[0] origin:032-cmt-pll 28_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[1] origin:032-cmt-pll 29_51 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[2] origin:032-cmt-pll 28_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[3] origin:032-cmt-pll 29_52 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[4] origin:032-cmt-pll 28_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_HIGH_TIME[5] origin:032-cmt-pll 29_53 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[0] origin:032-cmt-pll 28_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[1] origin:032-cmt-pll 29_48 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[2] origin:032-cmt-pll 28_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[3] origin:032-cmt-pll 29_49 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[4] origin:032-cmt-pll 28_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_LOW_TIME[5] origin:032-cmt-pll 29_50 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_OUTPUT_ENABLE[0] origin:032-cmt-pll 28_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[0] origin:032-cmt-pll 29_54 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[1] origin:032-cmt-pll 28_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT1_PHASE_MUX[2] origin:032-cmt-pll 29_55 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[0] origin:032-cmt-pll 28_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[1] origin:032-cmt-pll 29_56 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[2] origin:032-cmt-pll 28_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[3] origin:032-cmt-pll 29_57 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[4] origin:032-cmt-pll 28_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_DELAY_TIME[5] origin:032-cmt-pll 29_58 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_EDGE[0] origin:032-cmt-pll 29_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[0] origin:032-cmt-pll 28_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[1] origin:032-cmt-pll 29_62 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC[2] origin:032-cmt-pll 28_63 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_EN[0] origin:032-cmt-pll 29_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_FRAC_WF_R[0] origin:032-cmt-pll 28_61 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[0] origin:032-cmt-pll 28_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_MX[1] origin:032-cmt-pll 29_60 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_NO_COUNT[0] origin:032-cmt-pll 28_59 +CMT_TOP_R_UPPER_T.PLLE2.CLKOUT5_CLKOUT2_RESERVED[0] origin:032-cmt-pll 29_63 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.BUF_IN_OR_EXTERNAL_OR_ZHOLD_CLKIN_BUF origin:032-cmt-pll 28_44 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.INTERNAL origin:032-cmt-pll 28_43 29_42 29_43 +CMT_TOP_R_UPPER_T.PLLE2.COMPENSATION.Z_ZHOLD_OR_CLKIN_BUF origin:032-cmt-pll 29_03 29_44 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_EDGE[0] origin:032-cmt-pll 29_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[0] origin:032-cmt-pll 28_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[1] origin:032-cmt-pll 29_179 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[2] origin:032-cmt-pll 28_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[3] origin:032-cmt-pll 29_180 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[4] origin:032-cmt-pll 28_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_HIGH_TIME[5] origin:032-cmt-pll 29_181 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[0] origin:032-cmt-pll 28_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[1] origin:032-cmt-pll 29_176 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[2] origin:032-cmt-pll 28_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[3] origin:032-cmt-pll 29_177 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[4] origin:032-cmt-pll 28_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_LOW_TIME[5] origin:032-cmt-pll 29_178 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_NO_COUNT[0] origin:032-cmt-pll 28_182 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[0] origin:032-cmt-pll 28_183 +CMT_TOP_R_UPPER_T.PLLE2.DIVCLK_DIVCLK_RESERVED[1] origin:032-cmt-pll 29_183 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[0] origin:032-cmt-pll 28_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[10] origin:032-cmt-pll 29_630 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[11] origin:032-cmt-pll 28_631 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[1] origin:032-cmt-pll 29_624 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[2] origin:032-cmt-pll 28_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[3] origin:032-cmt-pll 29_625 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[4] origin:032-cmt-pll 28_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[5] origin:032-cmt-pll 29_626 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[6] origin:032-cmt-pll 28_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[7] origin:032-cmt-pll 29_627 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[8] origin:032-cmt-pll 29_628 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG1_RESERVED[9] origin:032-cmt-pll 28_629 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[0] origin:032-cmt-pll 28_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[1] origin:032-cmt-pll 29_632 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[2] origin:032-cmt-pll 28_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[3] origin:032-cmt-pll 29_633 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[4] origin:032-cmt-pll 29_634 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[5] origin:032-cmt-pll 28_635 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[6] origin:032-cmt-pll 29_636 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[7] origin:032-cmt-pll 28_637 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[8] origin:032-cmt-pll 29_638 +CMT_TOP_R_UPPER_T.PLLE2.FILTREG2_RESERVED[9] origin:032-cmt-pll 28_639 +CMT_TOP_R_UPPER_T.PLLE2.INV_CLKINSEL origin:032-cmt-pll 28_722 +CMT_TOP_R_UPPER_T.PLLE2.IN_USE origin:032-cmt-pll 28_05 28_10 28_16 28_184 28_187 28_190 28_234 28_248 28_251 28_252 28_42 28_46 28_560 28_590 28_591 28_592 28_595 28_596 28_736 28_753 28_754 28_755 28_756 28_758 28_759 28_760 28_761 28_763 28_764 28_765 28_766 28_767 28_771 28_774 28_775 28_779 28_780 28_783 28_784 28_785 28_786 28_787 28_789 28_790 28_791 28_792 28_794 28_795 28_796 28_797 28_800 28_803 28_806 28_809 28_813 28_815 29_08 29_16 29_236 29_249 29_250 29_251 29_45 29_46 29_47 29_531 29_535 29_557 29_589 29_590 29_593 29_594 29_595 29_753 29_754 29_756 29_758 29_759 29_761 29_765 29_766 29_768 29_777 29_779 29_780 29_781 29_782 29_783 29_784 29_785 29_787 29_791 29_792 29_793 29_794 29_795 29_797 29_798 29_799 29_800 29_803 29_804 29_806 29_807 29_808 29_809 29_810 29_813 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[0] origin:032-cmt-pll 28_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[10] origin:032-cmt-pll 28_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[11] origin:032-cmt-pll 29_208 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[12] origin:032-cmt-pll 28_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[13] origin:032-cmt-pll 29_209 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[14] origin:032-cmt-pll 28_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[15] origin:032-cmt-pll 29_210 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[16] origin:032-cmt-pll 28_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[17] origin:032-cmt-pll 29_211 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[18] origin:032-cmt-pll 28_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[19] origin:032-cmt-pll 29_212 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[1] origin:032-cmt-pll 29_200 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[20] origin:032-cmt-pll 28_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[21] origin:032-cmt-pll 29_192 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[22] origin:032-cmt-pll 28_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[23] origin:032-cmt-pll 29_193 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[24] origin:032-cmt-pll 28_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[25] origin:032-cmt-pll 29_194 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[26] origin:032-cmt-pll 28_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[27] origin:032-cmt-pll 29_195 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[28] origin:032-cmt-pll 28_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[29] origin:032-cmt-pll 29_196 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[2] origin:032-cmt-pll 28_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[30] origin:032-cmt-pll 28_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[31] origin:032-cmt-pll 29_205 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[32] origin:032-cmt-pll 28_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[33] origin:032-cmt-pll 29_206 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[34] origin:032-cmt-pll 28_207 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[35] origin:032-cmt-pll 28_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[36] origin:032-cmt-pll 29_213 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[37] origin:032-cmt-pll 28_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[38] origin:032-cmt-pll 29_214 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[39] origin:032-cmt-pll 28_215 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[3] origin:032-cmt-pll 29_201 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[4] origin:032-cmt-pll 28_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[5] origin:032-cmt-pll 29_202 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[6] origin:032-cmt-pll 28_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[7] origin:032-cmt-pll 29_203 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[8] origin:032-cmt-pll 28_204 +CMT_TOP_R_UPPER_T.PLLE2.LKTABLE[9] origin:032-cmt-pll 29_204 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[0] origin:032-cmt-pll 28_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[1] origin:032-cmt-pll 29_197 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[2] origin:032-cmt-pll 28_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[3] origin:032-cmt-pll 29_198 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[4] origin:032-cmt-pll 28_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG1_RESERVED[5] origin:032-cmt-pll 29_199 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG2_RESERVED[0] origin:032-cmt-pll 29_207 +CMT_TOP_R_UPPER_T.PLLE2.LOCKREG3_RESERVED[0] origin:032-cmt-pll 29_215 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[0] origin:032-cmt-pll 28_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[10] origin:032-cmt-pll 28_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[11] origin:032-cmt-pll 29_325 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[12] origin:032-cmt-pll 28_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[13] origin:032-cmt-pll 29_326 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[14] origin:032-cmt-pll 28_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[15] origin:032-cmt-pll 29_327 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[1] origin:032-cmt-pll 29_320 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[2] origin:032-cmt-pll 28_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[3] origin:032-cmt-pll 29_321 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[4] origin:032-cmt-pll 28_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[5] origin:032-cmt-pll 29_322 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[6] origin:032-cmt-pll 28_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[7] origin:032-cmt-pll 29_323 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[8] origin:032-cmt-pll 28_324 +CMT_TOP_R_UPPER_T.PLLE2.POWER_REG_POWER_REG_POWER_REG[9] origin:032-cmt-pll 29_324 +CMT_TOP_R_UPPER_T.PLLE2.STARTUP_WAIT origin:032-cmt-pll 28_737 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[0] origin:032-cmt-pll 28_634 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[1] origin:032-cmt-pll 29_635 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[2] origin:032-cmt-pll 28_636 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[3] origin:032-cmt-pll 29_637 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[4] origin:032-cmt-pll 28_638 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[5] origin:032-cmt-pll 29_639 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[6] origin:032-cmt-pll 28_628 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[7] origin:032-cmt-pll 29_629 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[8] origin:032-cmt-pll 28_630 +CMT_TOP_R_UPPER_T.PLLE2.TABLE[9] origin:032-cmt-pll 29_631 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_PWRDWN origin:032-cmt-pll 29_720 +CMT_TOP_R_UPPER_T.PLLE2.ZINV_RST origin:032-cmt-pll 28_720
diff --git a/zynq7/segbits_int_l.origin_info.db b/zynq7/segbits_int_l.origin_info.db index 075ad15..8cce496 100644 --- a/zynq7/segbits_int_l.origin_info.db +++ b/zynq7/segbits_int_l.origin_info.db
@@ -2411,7 +2411,7 @@ INT_L.NN6BEG2.NW2END2 origin:050-pip-seed 03_38 04_36 INT_L.NN6BEG2.NW6END2 origin:050-pip-seed 04_36 07_39 INT_L.NN6BEG2.SE2END2 origin:050-pip-seed 03_38 05_38 -INT_L.NN6BEG2.SE6END2 origin:050-pip-seed 05_38 07_39 +INT_L.NN6BEG2.SE6END2 origin:056-pip-rem 05_38 07_39 INT_L.NN6BEG2.WW2END1 origin:050-pip-seed 02_39 04_36 INT_L.NN6BEG2.WW4END2 origin:050-pip-seed 04_36 04_39 INT_L.NN6BEG3.EE2END3 origin:050-pip-seed 02_55 05_54 @@ -2431,7 +2431,7 @@ INT_L.NN6BEG3.NW2END3 origin:050-pip-seed 03_54 04_52 INT_L.NN6BEG3.NW6END3 origin:050-pip-seed 04_52 07_55 INT_L.NN6BEG3.SE2END3 origin:050-pip-seed 03_54 05_54 -INT_L.NN6BEG3.SE6END3 origin:050-pip-seed 05_54 07_55 +INT_L.NN6BEG3.SE6END3 origin:056-pip-rem 05_54 07_55 INT_L.NN6BEG3.WW2END2 origin:050-pip-seed 02_55 04_52 INT_L.NN6BEG3.WW4END3 origin:050-pip-seed 04_52 04_55 INT_L.NR1BEG0.EE2END0 origin:050-pip-seed 10_07 15_07 @@ -3275,7 +3275,7 @@ INT_L.SW6BEG1.WW2END1 origin:050-pip-seed 03_28 05_31 INT_L.SW6BEG1.WW4END2 origin:050-pip-seed 05_28 05_31 INT_L.SW6BEG2.EE2END2 origin:050-pip-seed 03_44 04_45 -INT_L.SW6BEG2.EE4END2 origin:056-pip-rem 04_45 05_44 +INT_L.SW6BEG2.EE4END2 origin:050-pip-seed 04_45 05_44 INT_L.SW6BEG2.LOGIC_OUTS_L10 origin:050-pip-seed 03_44 04_46 INT_L.SW6BEG2.LOGIC_OUTS_L14 origin:050-pip-seed 03_44 07_45 INT_L.SW6BEG2.LOGIC_OUTS_L16 origin:050-pip-seed 04_46 06_44
diff --git a/zynq7/segbits_int_r.origin_info.db b/zynq7/segbits_int_r.origin_info.db index 66d9b4f..d18b77c 100644 --- a/zynq7/segbits_int_r.origin_info.db +++ b/zynq7/segbits_int_r.origin_info.db
@@ -393,7 +393,7 @@ INT_R.EE4BEG2.SS2END2 origin:050-pip-seed 03_40 05_43 INT_R.EE4BEG2.SS6END2 origin:050-pip-seed 05_43 06_40 INT_R.EE4BEG2.SW2END2 origin:050-pip-seed 02_41 05_43 -INT_R.EE4BEG2.SW6END2 origin:050-pip-seed 05_40 05_43 +INT_R.EE4BEG2.SW6END2 origin:056-pip-rem 05_40 05_43 INT_R.EE4BEG3.EE2END3 origin:050-pip-seed 03_56 03_57 INT_R.EE4BEG3.EE4END3 origin:050-pip-seed 03_57 05_56 INT_R.EE4BEG3.LH0 origin:056-pip-rem 04_58 05_56 @@ -2193,7 +2193,7 @@ INT_R.NE6BEG3.SE2END3 origin:050-pip-seed 02_53 05_55 INT_R.NE6BEG3.SE6END3 origin:050-pip-seed 05_55 06_52 INT_R.NE6BEG3.WW2END2 origin:050-pip-seed 03_52 04_53 -INT_R.NE6BEG3.WW4END3 origin:050-pip-seed 04_53 05_52 +INT_R.NE6BEG3.WW4END3 origin:056-pip-rem 04_53 05_52 INT_R.NL1BEG0.LOGIC_OUTS1 origin:050-pip-seed 07_16 14_17 INT_R.NL1BEG0.LOGIC_OUTS13 origin:050-pip-seed 10_17 14_17 INT_R.NL1BEG0.LOGIC_OUTS19 origin:050-pip-seed 08_17 14_17 @@ -2827,7 +2827,7 @@ INT_R.SE6BEG3.NE2END3 origin:050-pip-seed 03_58 04_56 INT_R.SE6BEG3.NE6END3 origin:050-pip-seed 04_56 04_59 INT_R.SE6BEG3.NN2END3 origin:050-pip-seed 02_59 04_56 -INT_R.SE6BEG3.NN6END3 origin:056-pip-rem 04_56 07_59 +INT_R.SE6BEG3.NN6END3 origin:050-pip-seed 04_56 07_59 INT_R.SE6BEG3.SE2END3 origin:050-pip-seed 02_58 03_58 INT_R.SE6BEG3.SE6END3 origin:050-pip-seed 02_58 07_59 INT_R.SE6BEG3.SS2END3 origin:050-pip-seed 02_59 05_58 @@ -3255,7 +3255,7 @@ INT_R.SW6BEG0.WW2END0 origin:050-pip-seed 03_12 05_15 INT_R.SW6BEG0.WW4END1 origin:050-pip-seed 05_12 05_15 INT_R.SW6BEG1.EE2END1 origin:050-pip-seed 03_28 04_29 -INT_R.SW6BEG1.EE4END1 origin:056-pip-rem 04_29 05_28 +INT_R.SW6BEG1.EE4END1 origin:050-pip-seed 04_29 05_28 INT_R.SW6BEG1.LH6 origin:056-pip-rem 05_28 07_29 INT_R.SW6BEG1.LOGIC_OUTS1 origin:050-pip-seed 02_29 04_30 INT_R.SW6BEG1.LOGIC_OUTS13 origin:050-pip-seed 03_28 04_30 @@ -3603,7 +3603,7 @@ INT_R.WW4BEG2.LVB0 origin:056-pip-rem 04_34 05_32 INT_R.WW4BEG2.LVB12 origin:056-pip-rem 05_32 07_33 INT_R.WW4BEG2.NE2END2 origin:050-pip-seed 02_33 05_35 -INT_R.WW4BEG2.NE6END2 origin:056-pip-rem 05_32 05_35 +INT_R.WW4BEG2.NE6END2 origin:050-pip-seed 05_32 05_35 INT_R.WW4BEG2.NN2END2 origin:050-pip-seed 03_32 05_35 INT_R.WW4BEG2.NN6END2 origin:050-pip-seed 05_35 06_32 INT_R.WW4BEG2.NW2END2 origin:050-pip-seed 02_33 03_33
diff --git a/zynq7/segbits_liob33.db b/zynq7/segbits_liob33.db index 7696c69..e8fc88d 100644 --- a/zynq7/segbits_liob33.db +++ b/zynq7/segbits_liob33.db
@@ -1,5 +1,7 @@ +LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 +LIOB33.IOB_Y0.IFF.INV_OCLK 28_124 LIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67 LIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72 LIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76 @@ -12,8 +14,11 @@ LIOB33.IOB_Y0.IFF.ZSRVAL_Q3 29_85 LIOB33.IOB_Y0.IFF.ZSRVAL_Q4 29_93 LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108 +LIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92 LIOB33.IOB_Y0.OFF.ZINIT_Q 33_97 @@ -31,8 +36,10 @@ LIOB33.IOB_Y0.ZINV_D 29_109 LIOB33.IOB_Y0.IDELMUXE3.0 29_101 LIOB33.IOB_Y0.IFFDELMUXE3.0 28_116 +LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28 +LIOB33.IOB_Y1.IFF.INV_OCLK 29_03 LIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60 LIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55 LIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51 @@ -45,8 +52,11 @@ LIOB33.IOB_Y1.IFF.ZSRVAL_Q3 28_42 LIOB33.IOB_Y1.IFF.ZSRVAL_Q4 28_34 LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19 +LIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35 LIOB33.IOB_Y1.OFF.ZINIT_Q 32_30
diff --git a/zynq7/segbits_liob33.origin_info.db b/zynq7/segbits_liob33.origin_info.db index 69e6970..5b5dbe0 100644 --- a/zynq7/segbits_liob33.origin_info.db +++ b/zynq7/segbits_liob33.origin_info.db
@@ -1,6 +1,8 @@ +LIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67 LIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98 LIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99 +LIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 LIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 LIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72 LIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76 @@ -15,7 +17,10 @@ LIOB33.IOB_Y0.IFFDELMUXE3.0 origin:035-iob-ilogic 28_116 LIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107 LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115 +LIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121 +LIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !31_92 LIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 31_92 LIOB33.IOB_Y0.OFF.ZINIT_Q origin:036-iob-ologic 33_97 @@ -31,9 +36,11 @@ LIOB33.IOB_Y0.OSERDESE.DATA_WIDTH.8 origin:036-iob-ologic 31_116 LIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75 LIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109 +LIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60 LIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29 LIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28 +LIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 LIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 LIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55 LIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51 @@ -48,7 +55,10 @@ LIOB33.IOB_Y1.IFFDELMUXE3.0 origin:035-iob-ilogic 29_11 LIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20 LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12 +LIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06 +LIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE origin:036-iob-ologic !30_35 LIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE origin:036-iob-ologic 30_35 LIOB33.IOB_Y1.OFF.ZINIT_Q origin:036-iob-ologic 32_30
diff --git a/zynq7/segbits_riob33.db b/zynq7/segbits_riob33.db index 955caa1..a046b59 100644 --- a/zynq7/segbits_riob33.db +++ b/zynq7/segbits_riob33.db
@@ -1,6 +1,8 @@ RIOB33.IOB_Y0.IBUFDISABLE.I 38_82 +RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE 26_71 28_67 31_67 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 27_98 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE 26_99 +RIOB33.IOB_Y0.IFF.INV_OCLK 28_124 RIOB33.IOB_Y0.IFF.SRTYPE.SYNC 29_67 RIOB33.IOB_Y0.IFF.ZINIT_Q1 28_72 RIOB33.IOB_Y0.IFF.ZINIT_Q2 28_76 @@ -16,8 +18,11 @@ RIOB33.IOB_Y0.INOUT 30_67 RIOB33.IOB_Y0.INTERMDISABLE.I 39_89 RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR 27_108 +RIOB33.IOB_Y0.ISERDES.IN_USE 27_70 27_102 27_110 28_83 28_110 31_83 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 26_117 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY 26_107 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE 26_115 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY 26_121 RIOB33.IOB_Y0.LVTTL.DRIVE.I24 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 39_117 39_119 !39_125 !39_127 RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !31_92 RIOB33.IOB_Y0.ODDR.DDR_CLK_EDGE.SAME_EDGE 31_92 @@ -63,8 +68,10 @@ RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I8 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 39_119 39_125 !39_127 RIOB33.IOB_Y0.LVCMOS33_LVTTL.DRIVE.I12_I16 31_86 32_66 33_111 38_64 !38_112 !38_118 38_126 39_65 !39_95 !39_113 !39_117 !39_119 39_125 39_127 RIOB33.IOB_Y1.IBUFDISABLE.I 39_45 +RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE 27_56 29_60 30_60 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE 26_29 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE 27_28 +RIOB33.IOB_Y1.IFF.INV_OCLK 29_03 RIOB33.IOB_Y1.IFF.SRTYPE.SYNC 28_60 RIOB33.IOB_Y1.IFF.ZINIT_Q1 29_55 RIOB33.IOB_Y1.IFF.ZINIT_Q2 29_51 @@ -80,8 +87,11 @@ RIOB33.IOB_Y1.INOUT 31_60 RIOB33.IOB_Y1.INTERMDISABLE.I 38_38 RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR 26_19 +RIOB33.IOB_Y1.ISERDES.IN_USE 26_17 26_25 26_57 29_17 29_44 30_44 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 27_10 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY 27_20 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE 27_12 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY 27_06 RIOB33.IOB_Y1.LVTTL.DRIVE.I24 30_41 32_16 33_61 !38_00 !38_02 38_08 38_10 !38_14 !38_32 38_62 39_01 !39_09 !39_15 39_63 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.OPPOSITE_EDGE !30_35 RIOB33.IOB_Y1.ODDR.DDR_CLK_EDGE.SAME_EDGE 30_35
diff --git a/zynq7/segbits_riob33.origin_info.db b/zynq7/segbits_riob33.origin_info.db index b6a5e96..20af015 100644 --- a/zynq7/segbits_riob33.origin_info.db +++ b/zynq7/segbits_riob33.origin_info.db
@@ -1,7 +1,9 @@ RIOB33.IOB_Y0.IBUFDISABLE.I origin:030-iob 38_82 +RIOB33.IOB_Y0.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 26_71 28_67 31_67 RIOB33.IOB_Y0.IDELMUXE3.0 origin:035-iob-ilogic 29_101 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 27_98 RIOB33.IOB_Y0.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 26_99 +RIOB33.IOB_Y0.IFF.INV_OCLK origin:035-iob-ilogic 28_124 RIOB33.IOB_Y0.IFF.SRTYPE.SYNC origin:035-iob-ilogic 29_67 RIOB33.IOB_Y0.IFF.ZINIT_Q1 origin:035-iob-ilogic 28_72 RIOB33.IOB_Y0.IFF.ZINIT_Q2 origin:035-iob-ilogic 28_76 @@ -19,7 +21,10 @@ RIOB33.IOB_Y0.IN_ONLY origin:030-iob 38_118 39_119 39_125 RIOB33.IOB_Y0.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 27_108 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 26_117 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 26_107 RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 26_115 +RIOB33.IOB_Y0.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 26_121 +RIOB33.IOB_Y0.ISERDES.IN_USE origin:035-iob-ilogic 27_102 27_110 27_70 28_110 28_83 31_83 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I12 origin:030-iob !38_118 !39_117 !39_119 !39_125 31_86 32_66 33_111 38_112 38_126 38_64 39_113 39_127 39_65 39_95 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I4 origin:030-iob !39_117 !39_119 !39_127 31_86 32_66 33_111 38_112 38_118 38_126 38_64 39_113 39_125 39_65 39_95 RIOB33.IOB_Y0.LVCMOS12.DRIVE.I8 origin:030-iob !38_118 !38_126 !39_117 !39_125 !39_127 31_86 32_66 33_111 38_112 38_64 39_113 39_119 39_65 39_95 @@ -63,9 +68,11 @@ RIOB33.IOB_Y0.TFF.ZINIT_Q origin:036-iob-ologic 30_75 RIOB33.IOB_Y0.ZINV_D origin:035-iob-ilogic 29_109 RIOB33.IOB_Y1.IBUFDISABLE.I origin:030-iob 39_45 +RIOB33.IOB_Y1.IDDR_OR_ISERDES.IN_USE origin:035-iob-ilogic 27_56 29_60 30_60 RIOB33.IOB_Y1.IDELMUXE3.0 origin:035-iob-ilogic 28_26 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.OPPOSITE_EDGE origin:035-iob-ilogic 26_29 RIOB33.IOB_Y1.IFF.DDR_CLK_EDGE.SAME_EDGE origin:035-iob-ilogic 27_28 +RIOB33.IOB_Y1.IFF.INV_OCLK origin:035-iob-ilogic 29_03 RIOB33.IOB_Y1.IFF.SRTYPE.SYNC origin:035-iob-ilogic 28_60 RIOB33.IOB_Y1.IFF.ZINIT_Q1 origin:035-iob-ilogic 29_55 RIOB33.IOB_Y1.IFF.ZINIT_Q2 origin:035-iob-ilogic 29_51 @@ -83,7 +90,10 @@ RIOB33.IOB_Y1.IN_ONLY origin:030-iob 38_02 38_08 39_09 RIOB33.IOB_Y1.ISERDES.DATA_RATE.SDR origin:035-iob-ilogic 26_19 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.MEMORY_DDR3 origin:035-iob-ilogic 27_10 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.NOT_MEMORY origin:035-iob-ilogic 27_20 RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.OVERSAMPLE origin:035-iob-ilogic 27_12 +RIOB33.IOB_Y1.ISERDES.INTERFACE_TYPE.Z_MEMORY origin:035-iob-ilogic 27_06 +RIOB33.IOB_Y1.ISERDES.IN_USE origin:035-iob-ilogic 26_17 26_25 26_57 29_17 29_44 30_44 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I12 origin:030-iob !38_02 !38_08 !38_10 !39_09 30_41 32_16 33_61 38_00 38_14 38_32 38_62 39_01 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I4 origin:030-iob !38_00 !38_08 !38_10 30_41 32_16 33_61 38_02 38_14 38_32 38_62 39_01 39_09 39_15 39_63 RIOB33.IOB_Y1.LVCMOS12.DRIVE.I8 origin:030-iob !38_00 !38_02 !38_10 !39_01 !39_09 30_41 32_16 33_61 38_08 38_14 38_32 38_62 39_15 39_63
diff --git a/zynq7/tilegrid.json b/zynq7/tilegrid.json index 9eb0c63..450aea3 100644 --- a/zynq7/tilegrid.json +++ b/zynq7/tilegrid.json
@@ -42794,7 +42794,14 @@ "type": "CMT_TOP_L_UPPER_B" }, "CMT_TOP_L_UPPER_T_X119Y44": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00401B00", + "frames": 30, + "offset": 75, + "words": 26 + } + }, "grid_x": 119, "grid_y": 60, "sites": { @@ -42803,7 +42810,14 @@ "type": "CMT_TOP_L_UPPER_T" }, "CMT_TOP_L_UPPER_T_X119Y96": { - "bits": {}, + "bits": { + "CLB_IO_CLK": { + "baseaddr": "0x00001B00", + "frames": 30, + "offset": 75, + "words": 26 + } + }, "grid_x": 119, "grid_y": 8, "sites": {