blob: 62eacdb7944cf21587054deaa418d313be665110 [file] [log] [blame]
{
"pips": {
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"delay": null,
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"res": "0.000"
},
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},
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},
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},
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"res": "0.000"
},
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},
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},
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},
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},
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"delay": null,
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},
"dst_wire": "PSS_LOGIC_OUTS0_3",
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},
"src_wire": "PSS0_LOGIC_OUTS0_3"
},
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"delay": null,
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},
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},
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},
"PSS0.PSS0_LOGIC_OUTS0_5->PSS_LOGIC_OUTS0_5": {
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"delay": null,
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},
"dst_wire": "PSS_LOGIC_OUTS0_5",
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"delay": null,
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},
"src_wire": "PSS0_LOGIC_OUTS0_5"
},
"PSS0.PSS0_LOGIC_OUTS0_6->PSS_LOGIC_OUTS0_6": {
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"delay": null,
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},
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"delay": null,
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"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_6"
},
"PSS0.PSS0_LOGIC_OUTS0_7->PSS_LOGIC_OUTS0_7": {
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"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_7",
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"src_to_dst": {
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"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_7"
},
"PSS0.PSS0_LOGIC_OUTS0_8->PSS_LOGIC_OUTS0_8": {
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"delay": null,
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},
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"src_to_dst": {
"delay": null,
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},
"src_wire": "PSS0_LOGIC_OUTS0_8"
},
"PSS0.PSS0_LOGIC_OUTS0_9->PSS_LOGIC_OUTS0_9": {
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"delay": null,
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"res": "0.000"
},
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"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_9"
},
"PSS0.PSS0_LOGIC_OUTS0_10->PSS_LOGIC_OUTS0_10": {
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"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_10",
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"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_10"
},
"PSS0.PSS0_LOGIC_OUTS0_11->PSS_LOGIC_OUTS0_11": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_11",
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"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_11"
},
"PSS0.PSS0_LOGIC_OUTS0_12->PSS_LOGIC_OUTS0_12": {
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"in_cap": null,
"res": "0.000"
},
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"src_to_dst": {
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},
"src_wire": "PSS0_LOGIC_OUTS0_12"
},
"PSS0.PSS0_LOGIC_OUTS0_13->PSS_LOGIC_OUTS0_13": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_13",
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"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_13"
},
"PSS0.PSS0_LOGIC_OUTS0_14->PSS_LOGIC_OUTS0_14": {
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"dst_to_src": {
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"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_14",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_14"
},
"PSS0.PSS0_LOGIC_OUTS0_15->PSS_LOGIC_OUTS0_15": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_15",
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"is_pseudo": "0",
"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_15"
},
"PSS0.PSS0_LOGIC_OUTS0_16->PSS_LOGIC_OUTS0_16": {
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"dst_to_src": {
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"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_16",
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"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_16"
},
"PSS0.PSS0_LOGIC_OUTS0_17->PSS_LOGIC_OUTS0_17": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS0_17",
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"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_17"
},
"PSS0.PSS0_LOGIC_OUTS0_18->PSS_LOGIC_OUTS0_18": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_18"
},
"PSS0.PSS0_LOGIC_OUTS0_19->PSS_LOGIC_OUTS0_19": {
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"dst_to_src": {
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"in_cap": null,
"res": "0.000"
},
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"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS0_19"
},
"PSS0.PSS0_LOGIC_OUTS1_0->PSS_LOGIC_OUTS1_0": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_0",
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"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_0"
},
"PSS0.PSS0_LOGIC_OUTS1_1->PSS_LOGIC_OUTS1_1": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_1",
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"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_1"
},
"PSS0.PSS0_LOGIC_OUTS1_2->PSS_LOGIC_OUTS1_2": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_2",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_2"
},
"PSS0.PSS0_LOGIC_OUTS1_3->PSS_LOGIC_OUTS1_3": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_3",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_3"
},
"PSS0.PSS0_LOGIC_OUTS1_4->PSS_LOGIC_OUTS1_4": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_4",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_4"
},
"PSS0.PSS0_LOGIC_OUTS1_5->PSS_LOGIC_OUTS1_5": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_5",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_5"
},
"PSS0.PSS0_LOGIC_OUTS1_6->PSS_LOGIC_OUTS1_6": {
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"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_6",
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"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_6"
},
"PSS0.PSS0_LOGIC_OUTS1_7->PSS_LOGIC_OUTS1_7": {
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"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_7",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_7"
},
"PSS0.PSS0_LOGIC_OUTS1_8->PSS_LOGIC_OUTS1_8": {
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"dst_to_src": {
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"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_8",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_8"
},
"PSS0.PSS0_LOGIC_OUTS1_9->PSS_LOGIC_OUTS1_9": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_9",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_9"
},
"PSS0.PSS0_LOGIC_OUTS1_10->PSS_LOGIC_OUTS1_10": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_10",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_10"
},
"PSS0.PSS0_LOGIC_OUTS1_11->PSS_LOGIC_OUTS1_11": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_11",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_11"
},
"PSS0.PSS0_LOGIC_OUTS1_12->PSS_LOGIC_OUTS1_12": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_12",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_12"
},
"PSS0.PSS0_LOGIC_OUTS1_13->PSS_LOGIC_OUTS1_13": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_13"
},
"PSS0.PSS0_LOGIC_OUTS1_14->PSS_LOGIC_OUTS1_14": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_14"
},
"PSS0.PSS0_LOGIC_OUTS1_15->PSS_LOGIC_OUTS1_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_15"
},
"PSS0.PSS0_LOGIC_OUTS1_16->PSS_LOGIC_OUTS1_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_16"
},
"PSS0.PSS0_LOGIC_OUTS1_17->PSS_LOGIC_OUTS1_17": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_17"
},
"PSS0.PSS0_LOGIC_OUTS1_18->PSS_LOGIC_OUTS1_18": {
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"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_18",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_18"
},
"PSS0.PSS0_LOGIC_OUTS1_19->PSS_LOGIC_OUTS1_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS1_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS1_19"
},
"PSS0.PSS0_LOGIC_OUTS2_0->PSS_LOGIC_OUTS2_0": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_0",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_0"
},
"PSS0.PSS0_LOGIC_OUTS2_1->PSS_LOGIC_OUTS2_1": {
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"dst_to_src": {
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"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_1"
},
"PSS0.PSS0_LOGIC_OUTS2_2->PSS_LOGIC_OUTS2_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_2"
},
"PSS0.PSS0_LOGIC_OUTS2_3->PSS_LOGIC_OUTS2_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_3"
},
"PSS0.PSS0_LOGIC_OUTS2_4->PSS_LOGIC_OUTS2_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_4"
},
"PSS0.PSS0_LOGIC_OUTS2_5->PSS_LOGIC_OUTS2_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_5"
},
"PSS0.PSS0_LOGIC_OUTS2_6->PSS_LOGIC_OUTS2_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_6"
},
"PSS0.PSS0_LOGIC_OUTS2_7->PSS_LOGIC_OUTS2_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_7"
},
"PSS0.PSS0_LOGIC_OUTS2_8->PSS_LOGIC_OUTS2_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_8"
},
"PSS0.PSS0_LOGIC_OUTS2_9->PSS_LOGIC_OUTS2_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_9"
},
"PSS0.PSS0_LOGIC_OUTS2_10->PSS_LOGIC_OUTS2_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_10"
},
"PSS0.PSS0_LOGIC_OUTS2_11->PSS_LOGIC_OUTS2_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_11"
},
"PSS0.PSS0_LOGIC_OUTS2_12->PSS_LOGIC_OUTS2_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_12"
},
"PSS0.PSS0_LOGIC_OUTS2_13->PSS_LOGIC_OUTS2_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_13"
},
"PSS0.PSS0_LOGIC_OUTS2_14->PSS_LOGIC_OUTS2_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_14"
},
"PSS0.PSS0_LOGIC_OUTS2_15->PSS_LOGIC_OUTS2_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_15"
},
"PSS0.PSS0_LOGIC_OUTS2_16->PSS_LOGIC_OUTS2_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_16"
},
"PSS0.PSS0_LOGIC_OUTS2_17->PSS_LOGIC_OUTS2_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_17"
},
"PSS0.PSS0_LOGIC_OUTS2_18->PSS_LOGIC_OUTS2_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_18"
},
"PSS0.PSS0_LOGIC_OUTS2_19->PSS_LOGIC_OUTS2_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS2_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS2_19"
},
"PSS0.PSS0_LOGIC_OUTS3_0->PSS_LOGIC_OUTS3_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_0"
},
"PSS0.PSS0_LOGIC_OUTS3_1->PSS_LOGIC_OUTS3_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_1"
},
"PSS0.PSS0_LOGIC_OUTS3_2->PSS_LOGIC_OUTS3_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_2"
},
"PSS0.PSS0_LOGIC_OUTS3_3->PSS_LOGIC_OUTS3_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_3"
},
"PSS0.PSS0_LOGIC_OUTS3_4->PSS_LOGIC_OUTS3_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_4"
},
"PSS0.PSS0_LOGIC_OUTS3_5->PSS_LOGIC_OUTS3_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_5"
},
"PSS0.PSS0_LOGIC_OUTS3_6->PSS_LOGIC_OUTS3_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_6"
},
"PSS0.PSS0_LOGIC_OUTS3_7->PSS_LOGIC_OUTS3_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_7"
},
"PSS0.PSS0_LOGIC_OUTS3_8->PSS_LOGIC_OUTS3_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_8"
},
"PSS0.PSS0_LOGIC_OUTS3_9->PSS_LOGIC_OUTS3_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_9"
},
"PSS0.PSS0_LOGIC_OUTS3_10->PSS_LOGIC_OUTS3_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_10"
},
"PSS0.PSS0_LOGIC_OUTS3_11->PSS_LOGIC_OUTS3_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_11"
},
"PSS0.PSS0_LOGIC_OUTS3_12->PSS_LOGIC_OUTS3_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_12"
},
"PSS0.PSS0_LOGIC_OUTS3_13->PSS_LOGIC_OUTS3_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_13"
},
"PSS0.PSS0_LOGIC_OUTS3_14->PSS_LOGIC_OUTS3_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_14"
},
"PSS0.PSS0_LOGIC_OUTS3_15->PSS_LOGIC_OUTS3_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_15"
},
"PSS0.PSS0_LOGIC_OUTS3_16->PSS_LOGIC_OUTS3_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_16"
},
"PSS0.PSS0_LOGIC_OUTS3_17->PSS_LOGIC_OUTS3_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_17"
},
"PSS0.PSS0_LOGIC_OUTS3_18->PSS_LOGIC_OUTS3_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_18"
},
"PSS0.PSS0_LOGIC_OUTS3_19->PSS_LOGIC_OUTS3_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS3_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS3_19"
},
"PSS0.PSS0_LOGIC_OUTS4_0->PSS_LOGIC_OUTS4_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_0"
},
"PSS0.PSS0_LOGIC_OUTS4_1->PSS_LOGIC_OUTS4_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_1"
},
"PSS0.PSS0_LOGIC_OUTS4_2->PSS_LOGIC_OUTS4_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_2"
},
"PSS0.PSS0_LOGIC_OUTS4_3->PSS_LOGIC_OUTS4_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_3"
},
"PSS0.PSS0_LOGIC_OUTS4_4->PSS_LOGIC_OUTS4_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_4"
},
"PSS0.PSS0_LOGIC_OUTS4_5->PSS_LOGIC_OUTS4_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_5"
},
"PSS0.PSS0_LOGIC_OUTS4_6->PSS_LOGIC_OUTS4_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_6"
},
"PSS0.PSS0_LOGIC_OUTS4_7->PSS_LOGIC_OUTS4_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_7"
},
"PSS0.PSS0_LOGIC_OUTS4_8->PSS_LOGIC_OUTS4_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_8"
},
"PSS0.PSS0_LOGIC_OUTS4_9->PSS_LOGIC_OUTS4_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_9"
},
"PSS0.PSS0_LOGIC_OUTS4_10->PSS_LOGIC_OUTS4_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_10"
},
"PSS0.PSS0_LOGIC_OUTS4_11->PSS_LOGIC_OUTS4_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_11"
},
"PSS0.PSS0_LOGIC_OUTS4_12->PSS_LOGIC_OUTS4_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_12"
},
"PSS0.PSS0_LOGIC_OUTS4_13->PSS_LOGIC_OUTS4_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_13"
},
"PSS0.PSS0_LOGIC_OUTS4_14->PSS_LOGIC_OUTS4_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_14"
},
"PSS0.PSS0_LOGIC_OUTS4_15->PSS_LOGIC_OUTS4_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_15"
},
"PSS0.PSS0_LOGIC_OUTS4_16->PSS_LOGIC_OUTS4_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_16"
},
"PSS0.PSS0_LOGIC_OUTS4_17->PSS_LOGIC_OUTS4_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_17"
},
"PSS0.PSS0_LOGIC_OUTS4_18->PSS_LOGIC_OUTS4_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_18"
},
"PSS0.PSS0_LOGIC_OUTS4_19->PSS_LOGIC_OUTS4_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS4_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS4_19"
},
"PSS0.PSS0_LOGIC_OUTS5_0->PSS_LOGIC_OUTS5_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_0"
},
"PSS0.PSS0_LOGIC_OUTS5_1->PSS_LOGIC_OUTS5_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_1"
},
"PSS0.PSS0_LOGIC_OUTS5_2->PSS_LOGIC_OUTS5_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_2"
},
"PSS0.PSS0_LOGIC_OUTS5_3->PSS_LOGIC_OUTS5_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_3"
},
"PSS0.PSS0_LOGIC_OUTS5_4->PSS_LOGIC_OUTS5_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_4"
},
"PSS0.PSS0_LOGIC_OUTS5_5->PSS_LOGIC_OUTS5_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_5"
},
"PSS0.PSS0_LOGIC_OUTS5_6->PSS_LOGIC_OUTS5_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_6"
},
"PSS0.PSS0_LOGIC_OUTS5_7->PSS_LOGIC_OUTS5_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_7"
},
"PSS0.PSS0_LOGIC_OUTS5_8->PSS_LOGIC_OUTS5_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_8"
},
"PSS0.PSS0_LOGIC_OUTS5_9->PSS_LOGIC_OUTS5_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_9"
},
"PSS0.PSS0_LOGIC_OUTS5_10->PSS_LOGIC_OUTS5_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_10"
},
"PSS0.PSS0_LOGIC_OUTS5_11->PSS_LOGIC_OUTS5_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_11"
},
"PSS0.PSS0_LOGIC_OUTS5_12->PSS_LOGIC_OUTS5_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_12"
},
"PSS0.PSS0_LOGIC_OUTS5_13->PSS_LOGIC_OUTS5_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_13"
},
"PSS0.PSS0_LOGIC_OUTS5_14->PSS_LOGIC_OUTS5_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_14"
},
"PSS0.PSS0_LOGIC_OUTS5_15->PSS_LOGIC_OUTS5_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_15"
},
"PSS0.PSS0_LOGIC_OUTS5_16->PSS_LOGIC_OUTS5_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_16"
},
"PSS0.PSS0_LOGIC_OUTS5_17->PSS_LOGIC_OUTS5_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_17"
},
"PSS0.PSS0_LOGIC_OUTS5_18->PSS_LOGIC_OUTS5_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_18"
},
"PSS0.PSS0_LOGIC_OUTS5_19->PSS_LOGIC_OUTS5_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS5_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS5_19"
},
"PSS0.PSS0_LOGIC_OUTS6_0->PSS_LOGIC_OUTS6_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_0"
},
"PSS0.PSS0_LOGIC_OUTS6_1->PSS_LOGIC_OUTS6_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_1"
},
"PSS0.PSS0_LOGIC_OUTS6_2->PSS_LOGIC_OUTS6_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_2"
},
"PSS0.PSS0_LOGIC_OUTS6_3->PSS_LOGIC_OUTS6_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_3"
},
"PSS0.PSS0_LOGIC_OUTS6_4->PSS_LOGIC_OUTS6_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_4"
},
"PSS0.PSS0_LOGIC_OUTS6_5->PSS_LOGIC_OUTS6_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_5"
},
"PSS0.PSS0_LOGIC_OUTS6_6->PSS_LOGIC_OUTS6_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_6"
},
"PSS0.PSS0_LOGIC_OUTS6_7->PSS_LOGIC_OUTS6_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_7"
},
"PSS0.PSS0_LOGIC_OUTS6_8->PSS_LOGIC_OUTS6_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_8"
},
"PSS0.PSS0_LOGIC_OUTS6_9->PSS_LOGIC_OUTS6_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_9"
},
"PSS0.PSS0_LOGIC_OUTS6_10->PSS_LOGIC_OUTS6_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_10"
},
"PSS0.PSS0_LOGIC_OUTS6_11->PSS_LOGIC_OUTS6_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_11"
},
"PSS0.PSS0_LOGIC_OUTS6_12->PSS_LOGIC_OUTS6_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_12"
},
"PSS0.PSS0_LOGIC_OUTS6_13->PSS_LOGIC_OUTS6_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_13"
},
"PSS0.PSS0_LOGIC_OUTS6_14->PSS_LOGIC_OUTS6_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_14"
},
"PSS0.PSS0_LOGIC_OUTS6_15->PSS_LOGIC_OUTS6_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_15"
},
"PSS0.PSS0_LOGIC_OUTS6_16->PSS_LOGIC_OUTS6_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_16"
},
"PSS0.PSS0_LOGIC_OUTS6_17->PSS_LOGIC_OUTS6_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_17"
},
"PSS0.PSS0_LOGIC_OUTS6_18->PSS_LOGIC_OUTS6_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_18"
},
"PSS0.PSS0_LOGIC_OUTS6_19->PSS_LOGIC_OUTS6_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS6_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS6_19"
},
"PSS0.PSS0_LOGIC_OUTS7_0->PSS_LOGIC_OUTS7_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_0"
},
"PSS0.PSS0_LOGIC_OUTS7_1->PSS_LOGIC_OUTS7_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_1"
},
"PSS0.PSS0_LOGIC_OUTS7_2->PSS_LOGIC_OUTS7_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_2"
},
"PSS0.PSS0_LOGIC_OUTS7_3->PSS_LOGIC_OUTS7_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_3"
},
"PSS0.PSS0_LOGIC_OUTS7_4->PSS_LOGIC_OUTS7_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_4"
},
"PSS0.PSS0_LOGIC_OUTS7_5->PSS_LOGIC_OUTS7_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_5"
},
"PSS0.PSS0_LOGIC_OUTS7_6->PSS_LOGIC_OUTS7_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_6"
},
"PSS0.PSS0_LOGIC_OUTS7_7->PSS_LOGIC_OUTS7_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_7"
},
"PSS0.PSS0_LOGIC_OUTS7_8->PSS_LOGIC_OUTS7_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_8"
},
"PSS0.PSS0_LOGIC_OUTS7_9->PSS_LOGIC_OUTS7_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_9"
},
"PSS0.PSS0_LOGIC_OUTS7_10->PSS_LOGIC_OUTS7_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_10"
},
"PSS0.PSS0_LOGIC_OUTS7_11->PSS_LOGIC_OUTS7_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_11"
},
"PSS0.PSS0_LOGIC_OUTS7_12->PSS_LOGIC_OUTS7_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_12"
},
"PSS0.PSS0_LOGIC_OUTS7_13->PSS_LOGIC_OUTS7_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_13"
},
"PSS0.PSS0_LOGIC_OUTS7_14->PSS_LOGIC_OUTS7_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_14"
},
"PSS0.PSS0_LOGIC_OUTS7_15->PSS_LOGIC_OUTS7_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_15"
},
"PSS0.PSS0_LOGIC_OUTS7_16->PSS_LOGIC_OUTS7_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_16"
},
"PSS0.PSS0_LOGIC_OUTS7_17->PSS_LOGIC_OUTS7_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_17"
},
"PSS0.PSS0_LOGIC_OUTS7_18->PSS_LOGIC_OUTS7_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_18"
},
"PSS0.PSS0_LOGIC_OUTS7_19->PSS_LOGIC_OUTS7_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS7_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS7_19"
},
"PSS0.PSS0_LOGIC_OUTS8_0->PSS_LOGIC_OUTS8_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_0"
},
"PSS0.PSS0_LOGIC_OUTS8_1->PSS_LOGIC_OUTS8_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_1"
},
"PSS0.PSS0_LOGIC_OUTS8_2->PSS_LOGIC_OUTS8_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_2"
},
"PSS0.PSS0_LOGIC_OUTS8_3->PSS_LOGIC_OUTS8_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_3"
},
"PSS0.PSS0_LOGIC_OUTS8_4->PSS_LOGIC_OUTS8_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_4"
},
"PSS0.PSS0_LOGIC_OUTS8_5->PSS_LOGIC_OUTS8_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_5"
},
"PSS0.PSS0_LOGIC_OUTS8_6->PSS_LOGIC_OUTS8_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_6"
},
"PSS0.PSS0_LOGIC_OUTS8_7->PSS_LOGIC_OUTS8_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_7"
},
"PSS0.PSS0_LOGIC_OUTS8_8->PSS_LOGIC_OUTS8_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_8"
},
"PSS0.PSS0_LOGIC_OUTS8_9->PSS_LOGIC_OUTS8_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_9"
},
"PSS0.PSS0_LOGIC_OUTS8_10->PSS_LOGIC_OUTS8_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_10"
},
"PSS0.PSS0_LOGIC_OUTS8_11->PSS_LOGIC_OUTS8_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_11"
},
"PSS0.PSS0_LOGIC_OUTS8_12->PSS_LOGIC_OUTS8_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_12"
},
"PSS0.PSS0_LOGIC_OUTS8_13->PSS_LOGIC_OUTS8_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_13"
},
"PSS0.PSS0_LOGIC_OUTS8_14->PSS_LOGIC_OUTS8_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_14"
},
"PSS0.PSS0_LOGIC_OUTS8_15->PSS_LOGIC_OUTS8_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_15"
},
"PSS0.PSS0_LOGIC_OUTS8_16->PSS_LOGIC_OUTS8_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_16"
},
"PSS0.PSS0_LOGIC_OUTS8_17->PSS_LOGIC_OUTS8_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_17"
},
"PSS0.PSS0_LOGIC_OUTS8_18->PSS_LOGIC_OUTS8_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_18"
},
"PSS0.PSS0_LOGIC_OUTS8_19->PSS_LOGIC_OUTS8_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS8_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS8_19"
},
"PSS0.PSS0_LOGIC_OUTS9_0->PSS_LOGIC_OUTS9_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_0"
},
"PSS0.PSS0_LOGIC_OUTS9_1->PSS_LOGIC_OUTS9_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_1"
},
"PSS0.PSS0_LOGIC_OUTS9_2->PSS_LOGIC_OUTS9_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_2"
},
"PSS0.PSS0_LOGIC_OUTS9_3->PSS_LOGIC_OUTS9_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_3"
},
"PSS0.PSS0_LOGIC_OUTS9_4->PSS_LOGIC_OUTS9_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_4"
},
"PSS0.PSS0_LOGIC_OUTS9_5->PSS_LOGIC_OUTS9_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_5"
},
"PSS0.PSS0_LOGIC_OUTS9_6->PSS_LOGIC_OUTS9_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_6"
},
"PSS0.PSS0_LOGIC_OUTS9_7->PSS_LOGIC_OUTS9_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_7"
},
"PSS0.PSS0_LOGIC_OUTS9_8->PSS_LOGIC_OUTS9_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_8"
},
"PSS0.PSS0_LOGIC_OUTS9_9->PSS_LOGIC_OUTS9_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_9"
},
"PSS0.PSS0_LOGIC_OUTS9_10->PSS_LOGIC_OUTS9_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_10"
},
"PSS0.PSS0_LOGIC_OUTS9_11->PSS_LOGIC_OUTS9_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_11"
},
"PSS0.PSS0_LOGIC_OUTS9_12->PSS_LOGIC_OUTS9_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_12"
},
"PSS0.PSS0_LOGIC_OUTS9_13->PSS_LOGIC_OUTS9_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_13"
},
"PSS0.PSS0_LOGIC_OUTS9_14->PSS_LOGIC_OUTS9_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_14"
},
"PSS0.PSS0_LOGIC_OUTS9_15->PSS_LOGIC_OUTS9_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_15"
},
"PSS0.PSS0_LOGIC_OUTS9_16->PSS_LOGIC_OUTS9_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_16"
},
"PSS0.PSS0_LOGIC_OUTS9_17->PSS_LOGIC_OUTS9_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_17"
},
"PSS0.PSS0_LOGIC_OUTS9_18->PSS_LOGIC_OUTS9_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_18"
},
"PSS0.PSS0_LOGIC_OUTS9_19->PSS_LOGIC_OUTS9_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS9_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS9_19"
},
"PSS0.PSS0_LOGIC_OUTS10_0->PSS_LOGIC_OUTS10_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_0"
},
"PSS0.PSS0_LOGIC_OUTS10_1->PSS_LOGIC_OUTS10_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_1"
},
"PSS0.PSS0_LOGIC_OUTS10_2->PSS_LOGIC_OUTS10_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_2"
},
"PSS0.PSS0_LOGIC_OUTS10_3->PSS_LOGIC_OUTS10_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_3"
},
"PSS0.PSS0_LOGIC_OUTS10_4->PSS_LOGIC_OUTS10_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_4"
},
"PSS0.PSS0_LOGIC_OUTS10_5->PSS_LOGIC_OUTS10_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_5"
},
"PSS0.PSS0_LOGIC_OUTS10_6->PSS_LOGIC_OUTS10_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_6"
},
"PSS0.PSS0_LOGIC_OUTS10_7->PSS_LOGIC_OUTS10_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_7"
},
"PSS0.PSS0_LOGIC_OUTS10_8->PSS_LOGIC_OUTS10_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_8"
},
"PSS0.PSS0_LOGIC_OUTS10_9->PSS_LOGIC_OUTS10_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_9"
},
"PSS0.PSS0_LOGIC_OUTS10_10->PSS_LOGIC_OUTS10_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_10"
},
"PSS0.PSS0_LOGIC_OUTS10_11->PSS_LOGIC_OUTS10_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_11"
},
"PSS0.PSS0_LOGIC_OUTS10_12->PSS_LOGIC_OUTS10_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_12"
},
"PSS0.PSS0_LOGIC_OUTS10_13->PSS_LOGIC_OUTS10_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_13"
},
"PSS0.PSS0_LOGIC_OUTS10_14->PSS_LOGIC_OUTS10_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_14"
},
"PSS0.PSS0_LOGIC_OUTS10_15->PSS_LOGIC_OUTS10_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_15"
},
"PSS0.PSS0_LOGIC_OUTS10_16->PSS_LOGIC_OUTS10_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_16"
},
"PSS0.PSS0_LOGIC_OUTS10_17->PSS_LOGIC_OUTS10_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_17"
},
"PSS0.PSS0_LOGIC_OUTS10_18->PSS_LOGIC_OUTS10_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_18"
},
"PSS0.PSS0_LOGIC_OUTS10_19->PSS_LOGIC_OUTS10_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS10_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS10_19"
},
"PSS0.PSS0_LOGIC_OUTS11_0->PSS_LOGIC_OUTS11_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_0"
},
"PSS0.PSS0_LOGIC_OUTS11_1->PSS_LOGIC_OUTS11_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_1"
},
"PSS0.PSS0_LOGIC_OUTS11_2->PSS_LOGIC_OUTS11_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_2"
},
"PSS0.PSS0_LOGIC_OUTS11_3->PSS_LOGIC_OUTS11_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_3"
},
"PSS0.PSS0_LOGIC_OUTS11_4->PSS_LOGIC_OUTS11_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_4"
},
"PSS0.PSS0_LOGIC_OUTS11_5->PSS_LOGIC_OUTS11_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_5"
},
"PSS0.PSS0_LOGIC_OUTS11_6->PSS_LOGIC_OUTS11_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_6"
},
"PSS0.PSS0_LOGIC_OUTS11_7->PSS_LOGIC_OUTS11_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_7"
},
"PSS0.PSS0_LOGIC_OUTS11_8->PSS_LOGIC_OUTS11_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_8"
},
"PSS0.PSS0_LOGIC_OUTS11_9->PSS_LOGIC_OUTS11_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_9"
},
"PSS0.PSS0_LOGIC_OUTS11_10->PSS_LOGIC_OUTS11_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_10"
},
"PSS0.PSS0_LOGIC_OUTS11_11->PSS_LOGIC_OUTS11_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_11"
},
"PSS0.PSS0_LOGIC_OUTS11_12->PSS_LOGIC_OUTS11_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_12"
},
"PSS0.PSS0_LOGIC_OUTS11_13->PSS_LOGIC_OUTS11_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_13"
},
"PSS0.PSS0_LOGIC_OUTS11_14->PSS_LOGIC_OUTS11_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_14"
},
"PSS0.PSS0_LOGIC_OUTS11_15->PSS_LOGIC_OUTS11_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_15"
},
"PSS0.PSS0_LOGIC_OUTS11_16->PSS_LOGIC_OUTS11_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_16"
},
"PSS0.PSS0_LOGIC_OUTS11_17->PSS_LOGIC_OUTS11_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_17"
},
"PSS0.PSS0_LOGIC_OUTS11_18->PSS_LOGIC_OUTS11_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_18"
},
"PSS0.PSS0_LOGIC_OUTS11_19->PSS_LOGIC_OUTS11_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS11_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS11_19"
},
"PSS0.PSS0_LOGIC_OUTS12_0->PSS_LOGIC_OUTS12_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_0"
},
"PSS0.PSS0_LOGIC_OUTS12_1->PSS_LOGIC_OUTS12_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_1"
},
"PSS0.PSS0_LOGIC_OUTS12_2->PSS_LOGIC_OUTS12_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_2"
},
"PSS0.PSS0_LOGIC_OUTS12_3->PSS_LOGIC_OUTS12_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_3"
},
"PSS0.PSS0_LOGIC_OUTS12_4->PSS_LOGIC_OUTS12_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_4"
},
"PSS0.PSS0_LOGIC_OUTS12_5->PSS_LOGIC_OUTS12_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_5"
},
"PSS0.PSS0_LOGIC_OUTS12_6->PSS_LOGIC_OUTS12_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_6"
},
"PSS0.PSS0_LOGIC_OUTS12_7->PSS_LOGIC_OUTS12_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_7"
},
"PSS0.PSS0_LOGIC_OUTS12_8->PSS_LOGIC_OUTS12_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_8"
},
"PSS0.PSS0_LOGIC_OUTS12_9->PSS_LOGIC_OUTS12_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_9"
},
"PSS0.PSS0_LOGIC_OUTS12_10->PSS_LOGIC_OUTS12_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_10"
},
"PSS0.PSS0_LOGIC_OUTS12_11->PSS_LOGIC_OUTS12_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_11"
},
"PSS0.PSS0_LOGIC_OUTS12_12->PSS_LOGIC_OUTS12_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_12"
},
"PSS0.PSS0_LOGIC_OUTS12_13->PSS_LOGIC_OUTS12_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_13"
},
"PSS0.PSS0_LOGIC_OUTS12_14->PSS_LOGIC_OUTS12_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_14"
},
"PSS0.PSS0_LOGIC_OUTS12_15->PSS_LOGIC_OUTS12_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_15"
},
"PSS0.PSS0_LOGIC_OUTS12_16->PSS_LOGIC_OUTS12_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_16"
},
"PSS0.PSS0_LOGIC_OUTS12_17->PSS_LOGIC_OUTS12_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_17"
},
"PSS0.PSS0_LOGIC_OUTS12_18->PSS_LOGIC_OUTS12_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_18"
},
"PSS0.PSS0_LOGIC_OUTS12_19->PSS_LOGIC_OUTS12_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS12_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS12_19"
},
"PSS0.PSS0_LOGIC_OUTS13_0->PSS_LOGIC_OUTS13_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_0"
},
"PSS0.PSS0_LOGIC_OUTS13_1->PSS_LOGIC_OUTS13_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_1"
},
"PSS0.PSS0_LOGIC_OUTS13_2->PSS_LOGIC_OUTS13_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_2"
},
"PSS0.PSS0_LOGIC_OUTS13_3->PSS_LOGIC_OUTS13_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_3"
},
"PSS0.PSS0_LOGIC_OUTS13_4->PSS_LOGIC_OUTS13_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_4"
},
"PSS0.PSS0_LOGIC_OUTS13_5->PSS_LOGIC_OUTS13_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_5"
},
"PSS0.PSS0_LOGIC_OUTS13_6->PSS_LOGIC_OUTS13_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_6"
},
"PSS0.PSS0_LOGIC_OUTS13_7->PSS_LOGIC_OUTS13_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_7"
},
"PSS0.PSS0_LOGIC_OUTS13_8->PSS_LOGIC_OUTS13_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_8"
},
"PSS0.PSS0_LOGIC_OUTS13_9->PSS_LOGIC_OUTS13_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_9"
},
"PSS0.PSS0_LOGIC_OUTS13_10->PSS_LOGIC_OUTS13_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_10"
},
"PSS0.PSS0_LOGIC_OUTS13_11->PSS_LOGIC_OUTS13_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_11"
},
"PSS0.PSS0_LOGIC_OUTS13_12->PSS_LOGIC_OUTS13_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_12"
},
"PSS0.PSS0_LOGIC_OUTS13_13->PSS_LOGIC_OUTS13_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_13"
},
"PSS0.PSS0_LOGIC_OUTS13_14->PSS_LOGIC_OUTS13_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_14"
},
"PSS0.PSS0_LOGIC_OUTS13_15->PSS_LOGIC_OUTS13_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_15"
},
"PSS0.PSS0_LOGIC_OUTS13_16->PSS_LOGIC_OUTS13_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_16"
},
"PSS0.PSS0_LOGIC_OUTS13_17->PSS_LOGIC_OUTS13_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_17",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_17"
},
"PSS0.PSS0_LOGIC_OUTS13_18->PSS_LOGIC_OUTS13_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_18"
},
"PSS0.PSS0_LOGIC_OUTS13_19->PSS_LOGIC_OUTS13_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS13_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS13_19"
},
"PSS0.PSS0_LOGIC_OUTS14_0->PSS_LOGIC_OUTS14_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_0"
},
"PSS0.PSS0_LOGIC_OUTS14_1->PSS_LOGIC_OUTS14_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_1"
},
"PSS0.PSS0_LOGIC_OUTS14_2->PSS_LOGIC_OUTS14_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_2"
},
"PSS0.PSS0_LOGIC_OUTS14_3->PSS_LOGIC_OUTS14_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_3"
},
"PSS0.PSS0_LOGIC_OUTS14_4->PSS_LOGIC_OUTS14_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_4"
},
"PSS0.PSS0_LOGIC_OUTS14_5->PSS_LOGIC_OUTS14_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_5"
},
"PSS0.PSS0_LOGIC_OUTS14_6->PSS_LOGIC_OUTS14_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_6"
},
"PSS0.PSS0_LOGIC_OUTS14_7->PSS_LOGIC_OUTS14_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_7"
},
"PSS0.PSS0_LOGIC_OUTS14_8->PSS_LOGIC_OUTS14_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_8"
},
"PSS0.PSS0_LOGIC_OUTS14_9->PSS_LOGIC_OUTS14_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_9"
},
"PSS0.PSS0_LOGIC_OUTS14_10->PSS_LOGIC_OUTS14_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_10"
},
"PSS0.PSS0_LOGIC_OUTS14_11->PSS_LOGIC_OUTS14_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_11"
},
"PSS0.PSS0_LOGIC_OUTS14_12->PSS_LOGIC_OUTS14_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_12"
},
"PSS0.PSS0_LOGIC_OUTS14_13->PSS_LOGIC_OUTS14_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_13"
},
"PSS0.PSS0_LOGIC_OUTS14_14->PSS_LOGIC_OUTS14_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_14"
},
"PSS0.PSS0_LOGIC_OUTS14_15->PSS_LOGIC_OUTS14_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_15"
},
"PSS0.PSS0_LOGIC_OUTS14_16->PSS_LOGIC_OUTS14_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_16"
},
"PSS0.PSS0_LOGIC_OUTS14_17->PSS_LOGIC_OUTS14_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_17"
},
"PSS0.PSS0_LOGIC_OUTS14_18->PSS_LOGIC_OUTS14_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_18"
},
"PSS0.PSS0_LOGIC_OUTS14_19->PSS_LOGIC_OUTS14_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS14_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS14_19"
},
"PSS0.PSS0_LOGIC_OUTS15_0->PSS_LOGIC_OUTS15_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_0"
},
"PSS0.PSS0_LOGIC_OUTS15_1->PSS_LOGIC_OUTS15_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_1"
},
"PSS0.PSS0_LOGIC_OUTS15_2->PSS_LOGIC_OUTS15_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_2"
},
"PSS0.PSS0_LOGIC_OUTS15_3->PSS_LOGIC_OUTS15_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_3"
},
"PSS0.PSS0_LOGIC_OUTS15_4->PSS_LOGIC_OUTS15_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_4"
},
"PSS0.PSS0_LOGIC_OUTS15_5->PSS_LOGIC_OUTS15_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_5"
},
"PSS0.PSS0_LOGIC_OUTS15_6->PSS_LOGIC_OUTS15_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_6"
},
"PSS0.PSS0_LOGIC_OUTS15_7->PSS_LOGIC_OUTS15_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_7"
},
"PSS0.PSS0_LOGIC_OUTS15_8->PSS_LOGIC_OUTS15_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_8"
},
"PSS0.PSS0_LOGIC_OUTS15_9->PSS_LOGIC_OUTS15_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_9"
},
"PSS0.PSS0_LOGIC_OUTS15_10->PSS_LOGIC_OUTS15_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_10"
},
"PSS0.PSS0_LOGIC_OUTS15_11->PSS_LOGIC_OUTS15_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_11"
},
"PSS0.PSS0_LOGIC_OUTS15_12->PSS_LOGIC_OUTS15_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_12"
},
"PSS0.PSS0_LOGIC_OUTS15_13->PSS_LOGIC_OUTS15_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_13"
},
"PSS0.PSS0_LOGIC_OUTS15_14->PSS_LOGIC_OUTS15_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_14"
},
"PSS0.PSS0_LOGIC_OUTS15_15->PSS_LOGIC_OUTS15_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_15"
},
"PSS0.PSS0_LOGIC_OUTS15_16->PSS_LOGIC_OUTS15_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_16"
},
"PSS0.PSS0_LOGIC_OUTS15_17->PSS_LOGIC_OUTS15_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_17"
},
"PSS0.PSS0_LOGIC_OUTS15_18->PSS_LOGIC_OUTS15_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_18"
},
"PSS0.PSS0_LOGIC_OUTS15_19->PSS_LOGIC_OUTS15_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS15_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS15_19"
},
"PSS0.PSS0_LOGIC_OUTS16_0->PSS_LOGIC_OUTS16_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_0"
},
"PSS0.PSS0_LOGIC_OUTS16_1->PSS_LOGIC_OUTS16_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_1"
},
"PSS0.PSS0_LOGIC_OUTS16_2->PSS_LOGIC_OUTS16_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_2"
},
"PSS0.PSS0_LOGIC_OUTS16_3->PSS_LOGIC_OUTS16_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_3"
},
"PSS0.PSS0_LOGIC_OUTS16_4->PSS_LOGIC_OUTS16_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_4"
},
"PSS0.PSS0_LOGIC_OUTS16_5->PSS_LOGIC_OUTS16_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_5"
},
"PSS0.PSS0_LOGIC_OUTS16_6->PSS_LOGIC_OUTS16_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_6"
},
"PSS0.PSS0_LOGIC_OUTS16_7->PSS_LOGIC_OUTS16_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_7"
},
"PSS0.PSS0_LOGIC_OUTS16_8->PSS_LOGIC_OUTS16_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_8"
},
"PSS0.PSS0_LOGIC_OUTS16_9->PSS_LOGIC_OUTS16_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_9"
},
"PSS0.PSS0_LOGIC_OUTS16_10->PSS_LOGIC_OUTS16_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_10"
},
"PSS0.PSS0_LOGIC_OUTS16_11->PSS_LOGIC_OUTS16_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_11"
},
"PSS0.PSS0_LOGIC_OUTS16_12->PSS_LOGIC_OUTS16_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_12"
},
"PSS0.PSS0_LOGIC_OUTS16_13->PSS_LOGIC_OUTS16_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_13"
},
"PSS0.PSS0_LOGIC_OUTS16_14->PSS_LOGIC_OUTS16_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_14"
},
"PSS0.PSS0_LOGIC_OUTS16_15->PSS_LOGIC_OUTS16_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_15"
},
"PSS0.PSS0_LOGIC_OUTS16_16->PSS_LOGIC_OUTS16_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_16"
},
"PSS0.PSS0_LOGIC_OUTS16_17->PSS_LOGIC_OUTS16_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_17"
},
"PSS0.PSS0_LOGIC_OUTS16_18->PSS_LOGIC_OUTS16_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_18"
},
"PSS0.PSS0_LOGIC_OUTS16_19->PSS_LOGIC_OUTS16_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS16_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS16_19"
},
"PSS0.PSS0_LOGIC_OUTS17_0->PSS_LOGIC_OUTS17_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_0"
},
"PSS0.PSS0_LOGIC_OUTS17_1->PSS_LOGIC_OUTS17_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_1"
},
"PSS0.PSS0_LOGIC_OUTS17_2->PSS_LOGIC_OUTS17_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_2"
},
"PSS0.PSS0_LOGIC_OUTS17_3->PSS_LOGIC_OUTS17_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_3"
},
"PSS0.PSS0_LOGIC_OUTS17_4->PSS_LOGIC_OUTS17_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_4"
},
"PSS0.PSS0_LOGIC_OUTS17_5->PSS_LOGIC_OUTS17_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_5"
},
"PSS0.PSS0_LOGIC_OUTS17_6->PSS_LOGIC_OUTS17_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_6"
},
"PSS0.PSS0_LOGIC_OUTS17_7->PSS_LOGIC_OUTS17_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_7"
},
"PSS0.PSS0_LOGIC_OUTS17_8->PSS_LOGIC_OUTS17_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_8"
},
"PSS0.PSS0_LOGIC_OUTS17_9->PSS_LOGIC_OUTS17_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_9"
},
"PSS0.PSS0_LOGIC_OUTS17_10->PSS_LOGIC_OUTS17_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_10"
},
"PSS0.PSS0_LOGIC_OUTS17_11->PSS_LOGIC_OUTS17_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_11"
},
"PSS0.PSS0_LOGIC_OUTS17_12->PSS_LOGIC_OUTS17_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_12"
},
"PSS0.PSS0_LOGIC_OUTS17_13->PSS_LOGIC_OUTS17_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_13"
},
"PSS0.PSS0_LOGIC_OUTS17_14->PSS_LOGIC_OUTS17_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_14"
},
"PSS0.PSS0_LOGIC_OUTS17_15->PSS_LOGIC_OUTS17_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_15"
},
"PSS0.PSS0_LOGIC_OUTS17_16->PSS_LOGIC_OUTS17_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_16"
},
"PSS0.PSS0_LOGIC_OUTS17_17->PSS_LOGIC_OUTS17_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_17"
},
"PSS0.PSS0_LOGIC_OUTS17_18->PSS_LOGIC_OUTS17_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_18"
},
"PSS0.PSS0_LOGIC_OUTS17_19->PSS_LOGIC_OUTS17_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS17_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS17_19"
},
"PSS0.PSS0_LOGIC_OUTS18_0->PSS_LOGIC_OUTS18_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_0"
},
"PSS0.PSS0_LOGIC_OUTS18_1->PSS_LOGIC_OUTS18_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_1"
},
"PSS0.PSS0_LOGIC_OUTS18_2->PSS_LOGIC_OUTS18_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_2"
},
"PSS0.PSS0_LOGIC_OUTS18_3->PSS_LOGIC_OUTS18_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_3"
},
"PSS0.PSS0_LOGIC_OUTS18_4->PSS_LOGIC_OUTS18_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_4"
},
"PSS0.PSS0_LOGIC_OUTS18_5->PSS_LOGIC_OUTS18_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_5"
},
"PSS0.PSS0_LOGIC_OUTS18_6->PSS_LOGIC_OUTS18_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_6"
},
"PSS0.PSS0_LOGIC_OUTS18_7->PSS_LOGIC_OUTS18_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_7"
},
"PSS0.PSS0_LOGIC_OUTS18_8->PSS_LOGIC_OUTS18_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_8"
},
"PSS0.PSS0_LOGIC_OUTS18_9->PSS_LOGIC_OUTS18_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_9"
},
"PSS0.PSS0_LOGIC_OUTS18_10->PSS_LOGIC_OUTS18_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_10"
},
"PSS0.PSS0_LOGIC_OUTS18_11->PSS_LOGIC_OUTS18_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_11"
},
"PSS0.PSS0_LOGIC_OUTS18_12->PSS_LOGIC_OUTS18_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_12"
},
"PSS0.PSS0_LOGIC_OUTS18_13->PSS_LOGIC_OUTS18_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_13"
},
"PSS0.PSS0_LOGIC_OUTS18_14->PSS_LOGIC_OUTS18_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_14"
},
"PSS0.PSS0_LOGIC_OUTS18_15->PSS_LOGIC_OUTS18_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_15"
},
"PSS0.PSS0_LOGIC_OUTS18_16->PSS_LOGIC_OUTS18_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_16"
},
"PSS0.PSS0_LOGIC_OUTS18_17->PSS_LOGIC_OUTS18_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_17"
},
"PSS0.PSS0_LOGIC_OUTS18_18->PSS_LOGIC_OUTS18_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_18"
},
"PSS0.PSS0_LOGIC_OUTS18_19->PSS_LOGIC_OUTS18_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS18_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS18_19"
},
"PSS0.PSS0_LOGIC_OUTS19_0->PSS_LOGIC_OUTS19_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_0"
},
"PSS0.PSS0_LOGIC_OUTS19_1->PSS_LOGIC_OUTS19_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_1"
},
"PSS0.PSS0_LOGIC_OUTS19_2->PSS_LOGIC_OUTS19_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_2"
},
"PSS0.PSS0_LOGIC_OUTS19_3->PSS_LOGIC_OUTS19_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_3"
},
"PSS0.PSS0_LOGIC_OUTS19_4->PSS_LOGIC_OUTS19_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_4"
},
"PSS0.PSS0_LOGIC_OUTS19_5->PSS_LOGIC_OUTS19_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_5"
},
"PSS0.PSS0_LOGIC_OUTS19_6->PSS_LOGIC_OUTS19_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_6"
},
"PSS0.PSS0_LOGIC_OUTS19_7->PSS_LOGIC_OUTS19_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_7"
},
"PSS0.PSS0_LOGIC_OUTS19_8->PSS_LOGIC_OUTS19_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_8"
},
"PSS0.PSS0_LOGIC_OUTS19_9->PSS_LOGIC_OUTS19_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_9"
},
"PSS0.PSS0_LOGIC_OUTS19_10->PSS_LOGIC_OUTS19_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_10"
},
"PSS0.PSS0_LOGIC_OUTS19_11->PSS_LOGIC_OUTS19_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_11"
},
"PSS0.PSS0_LOGIC_OUTS19_12->PSS_LOGIC_OUTS19_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_12"
},
"PSS0.PSS0_LOGIC_OUTS19_13->PSS_LOGIC_OUTS19_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_13"
},
"PSS0.PSS0_LOGIC_OUTS19_14->PSS_LOGIC_OUTS19_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_14"
},
"PSS0.PSS0_LOGIC_OUTS19_15->PSS_LOGIC_OUTS19_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_15"
},
"PSS0.PSS0_LOGIC_OUTS19_16->PSS_LOGIC_OUTS19_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_16"
},
"PSS0.PSS0_LOGIC_OUTS19_17->PSS_LOGIC_OUTS19_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_17"
},
"PSS0.PSS0_LOGIC_OUTS19_18->PSS_LOGIC_OUTS19_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_18"
},
"PSS0.PSS0_LOGIC_OUTS19_19->PSS_LOGIC_OUTS19_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS19_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS19_19"
},
"PSS0.PSS0_LOGIC_OUTS20_0->PSS_LOGIC_OUTS20_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_0"
},
"PSS0.PSS0_LOGIC_OUTS20_1->PSS_LOGIC_OUTS20_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_1"
},
"PSS0.PSS0_LOGIC_OUTS20_2->PSS_LOGIC_OUTS20_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_2"
},
"PSS0.PSS0_LOGIC_OUTS20_3->PSS_LOGIC_OUTS20_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_3"
},
"PSS0.PSS0_LOGIC_OUTS20_4->PSS_LOGIC_OUTS20_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_4"
},
"PSS0.PSS0_LOGIC_OUTS20_5->PSS_LOGIC_OUTS20_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_5"
},
"PSS0.PSS0_LOGIC_OUTS20_6->PSS_LOGIC_OUTS20_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_6"
},
"PSS0.PSS0_LOGIC_OUTS20_7->PSS_LOGIC_OUTS20_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_7"
},
"PSS0.PSS0_LOGIC_OUTS20_8->PSS_LOGIC_OUTS20_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_8"
},
"PSS0.PSS0_LOGIC_OUTS20_9->PSS_LOGIC_OUTS20_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_9"
},
"PSS0.PSS0_LOGIC_OUTS20_10->PSS_LOGIC_OUTS20_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_10"
},
"PSS0.PSS0_LOGIC_OUTS20_11->PSS_LOGIC_OUTS20_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_11"
},
"PSS0.PSS0_LOGIC_OUTS20_12->PSS_LOGIC_OUTS20_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_12"
},
"PSS0.PSS0_LOGIC_OUTS20_13->PSS_LOGIC_OUTS20_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_13"
},
"PSS0.PSS0_LOGIC_OUTS20_14->PSS_LOGIC_OUTS20_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_14"
},
"PSS0.PSS0_LOGIC_OUTS20_15->PSS_LOGIC_OUTS20_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_15"
},
"PSS0.PSS0_LOGIC_OUTS20_16->PSS_LOGIC_OUTS20_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_16"
},
"PSS0.PSS0_LOGIC_OUTS20_17->PSS_LOGIC_OUTS20_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_17"
},
"PSS0.PSS0_LOGIC_OUTS20_18->PSS_LOGIC_OUTS20_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_18"
},
"PSS0.PSS0_LOGIC_OUTS20_19->PSS_LOGIC_OUTS20_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS20_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS20_19"
},
"PSS0.PSS0_LOGIC_OUTS21_0->PSS_LOGIC_OUTS21_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_0"
},
"PSS0.PSS0_LOGIC_OUTS21_1->PSS_LOGIC_OUTS21_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_1"
},
"PSS0.PSS0_LOGIC_OUTS21_2->PSS_LOGIC_OUTS21_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_2"
},
"PSS0.PSS0_LOGIC_OUTS21_3->PSS_LOGIC_OUTS21_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_3"
},
"PSS0.PSS0_LOGIC_OUTS21_4->PSS_LOGIC_OUTS21_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_4"
},
"PSS0.PSS0_LOGIC_OUTS21_5->PSS_LOGIC_OUTS21_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_5"
},
"PSS0.PSS0_LOGIC_OUTS21_6->PSS_LOGIC_OUTS21_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_6"
},
"PSS0.PSS0_LOGIC_OUTS21_7->PSS_LOGIC_OUTS21_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_7"
},
"PSS0.PSS0_LOGIC_OUTS21_8->PSS_LOGIC_OUTS21_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_8"
},
"PSS0.PSS0_LOGIC_OUTS21_9->PSS_LOGIC_OUTS21_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_9"
},
"PSS0.PSS0_LOGIC_OUTS21_10->PSS_LOGIC_OUTS21_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_10"
},
"PSS0.PSS0_LOGIC_OUTS21_11->PSS_LOGIC_OUTS21_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_11"
},
"PSS0.PSS0_LOGIC_OUTS21_12->PSS_LOGIC_OUTS21_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_12"
},
"PSS0.PSS0_LOGIC_OUTS21_13->PSS_LOGIC_OUTS21_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_13"
},
"PSS0.PSS0_LOGIC_OUTS21_14->PSS_LOGIC_OUTS21_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_14"
},
"PSS0.PSS0_LOGIC_OUTS21_15->PSS_LOGIC_OUTS21_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_15"
},
"PSS0.PSS0_LOGIC_OUTS21_16->PSS_LOGIC_OUTS21_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_16"
},
"PSS0.PSS0_LOGIC_OUTS21_17->PSS_LOGIC_OUTS21_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_17"
},
"PSS0.PSS0_LOGIC_OUTS21_18->PSS_LOGIC_OUTS21_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_18"
},
"PSS0.PSS0_LOGIC_OUTS21_19->PSS_LOGIC_OUTS21_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS21_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS21_19"
},
"PSS0.PSS0_LOGIC_OUTS22_0->PSS_LOGIC_OUTS22_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_0"
},
"PSS0.PSS0_LOGIC_OUTS22_1->PSS_LOGIC_OUTS22_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_1"
},
"PSS0.PSS0_LOGIC_OUTS22_2->PSS_LOGIC_OUTS22_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_2"
},
"PSS0.PSS0_LOGIC_OUTS22_3->PSS_LOGIC_OUTS22_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_3"
},
"PSS0.PSS0_LOGIC_OUTS22_4->PSS_LOGIC_OUTS22_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_4"
},
"PSS0.PSS0_LOGIC_OUTS22_5->PSS_LOGIC_OUTS22_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_5"
},
"PSS0.PSS0_LOGIC_OUTS22_6->PSS_LOGIC_OUTS22_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_6"
},
"PSS0.PSS0_LOGIC_OUTS22_7->PSS_LOGIC_OUTS22_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_7"
},
"PSS0.PSS0_LOGIC_OUTS22_8->PSS_LOGIC_OUTS22_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_8"
},
"PSS0.PSS0_LOGIC_OUTS22_9->PSS_LOGIC_OUTS22_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_9"
},
"PSS0.PSS0_LOGIC_OUTS22_10->PSS_LOGIC_OUTS22_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_10"
},
"PSS0.PSS0_LOGIC_OUTS22_11->PSS_LOGIC_OUTS22_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_11"
},
"PSS0.PSS0_LOGIC_OUTS22_12->PSS_LOGIC_OUTS22_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_12"
},
"PSS0.PSS0_LOGIC_OUTS22_13->PSS_LOGIC_OUTS22_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_13"
},
"PSS0.PSS0_LOGIC_OUTS22_14->PSS_LOGIC_OUTS22_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_14"
},
"PSS0.PSS0_LOGIC_OUTS22_15->PSS_LOGIC_OUTS22_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_15"
},
"PSS0.PSS0_LOGIC_OUTS22_16->PSS_LOGIC_OUTS22_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_16"
},
"PSS0.PSS0_LOGIC_OUTS22_17->PSS_LOGIC_OUTS22_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_17"
},
"PSS0.PSS0_LOGIC_OUTS22_18->PSS_LOGIC_OUTS22_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_18"
},
"PSS0.PSS0_LOGIC_OUTS22_19->PSS_LOGIC_OUTS22_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS22_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS22_19"
},
"PSS0.PSS0_LOGIC_OUTS23_0->PSS_LOGIC_OUTS23_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_0"
},
"PSS0.PSS0_LOGIC_OUTS23_1->PSS_LOGIC_OUTS23_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_1"
},
"PSS0.PSS0_LOGIC_OUTS23_2->PSS_LOGIC_OUTS23_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_2"
},
"PSS0.PSS0_LOGIC_OUTS23_3->PSS_LOGIC_OUTS23_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_3"
},
"PSS0.PSS0_LOGIC_OUTS23_4->PSS_LOGIC_OUTS23_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_4"
},
"PSS0.PSS0_LOGIC_OUTS23_5->PSS_LOGIC_OUTS23_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_5"
},
"PSS0.PSS0_LOGIC_OUTS23_6->PSS_LOGIC_OUTS23_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_6"
},
"PSS0.PSS0_LOGIC_OUTS23_7->PSS_LOGIC_OUTS23_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_7"
},
"PSS0.PSS0_LOGIC_OUTS23_8->PSS_LOGIC_OUTS23_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_8"
},
"PSS0.PSS0_LOGIC_OUTS23_9->PSS_LOGIC_OUTS23_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_9"
},
"PSS0.PSS0_LOGIC_OUTS23_10->PSS_LOGIC_OUTS23_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_10"
},
"PSS0.PSS0_LOGIC_OUTS23_11->PSS_LOGIC_OUTS23_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_11"
},
"PSS0.PSS0_LOGIC_OUTS23_12->PSS_LOGIC_OUTS23_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_12"
},
"PSS0.PSS0_LOGIC_OUTS23_13->PSS_LOGIC_OUTS23_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_13"
},
"PSS0.PSS0_LOGIC_OUTS23_14->PSS_LOGIC_OUTS23_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_14"
},
"PSS0.PSS0_LOGIC_OUTS23_15->PSS_LOGIC_OUTS23_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_15"
},
"PSS0.PSS0_LOGIC_OUTS23_16->PSS_LOGIC_OUTS23_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_16"
},
"PSS0.PSS0_LOGIC_OUTS23_17->PSS_LOGIC_OUTS23_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_17"
},
"PSS0.PSS0_LOGIC_OUTS23_18->PSS_LOGIC_OUTS23_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_18"
},
"PSS0.PSS0_LOGIC_OUTS23_19->PSS_LOGIC_OUTS23_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS_LOGIC_OUTS23_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS0_LOGIC_OUTS23_19"
},
"PSS0.PSS_CLK_B0_0->PSS0_CLK_B0_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_0"
},
"PSS0.PSS_CLK_B0_1->PSS0_CLK_B0_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_1"
},
"PSS0.PSS_CLK_B0_2->PSS0_CLK_B0_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_2"
},
"PSS0.PSS_CLK_B0_3->PSS0_CLK_B0_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_3"
},
"PSS0.PSS_CLK_B0_4->PSS0_CLK_B0_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_4"
},
"PSS0.PSS_CLK_B0_5->PSS0_CLK_B0_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_5"
},
"PSS0.PSS_CLK_B0_6->PSS0_CLK_B0_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_6"
},
"PSS0.PSS_CLK_B0_7->PSS0_CLK_B0_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_7"
},
"PSS0.PSS_CLK_B0_8->PSS0_CLK_B0_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_8"
},
"PSS0.PSS_CLK_B0_9->PSS0_CLK_B0_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_9"
},
"PSS0.PSS_CLK_B0_10->PSS0_CLK_B0_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_10"
},
"PSS0.PSS_CLK_B0_11->PSS0_CLK_B0_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_11"
},
"PSS0.PSS_CLK_B0_12->PSS0_CLK_B0_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_12"
},
"PSS0.PSS_CLK_B0_13->PSS0_CLK_B0_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_13"
},
"PSS0.PSS_CLK_B0_14->PSS0_CLK_B0_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_14"
},
"PSS0.PSS_CLK_B0_15->PSS0_CLK_B0_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_15"
},
"PSS0.PSS_CLK_B0_16->PSS0_CLK_B0_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_16"
},
"PSS0.PSS_CLK_B0_17->PSS0_CLK_B0_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_17"
},
"PSS0.PSS_CLK_B0_18->PSS0_CLK_B0_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_18"
},
"PSS0.PSS_CLK_B0_19->PSS0_CLK_B0_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B0_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B0_19"
},
"PSS0.PSS_CLK_B1_0->PSS0_CLK_B1_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_0"
},
"PSS0.PSS_CLK_B1_1->PSS0_CLK_B1_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_1"
},
"PSS0.PSS_CLK_B1_2->PSS0_CLK_B1_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_2"
},
"PSS0.PSS_CLK_B1_3->PSS0_CLK_B1_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_3"
},
"PSS0.PSS_CLK_B1_4->PSS0_CLK_B1_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_4"
},
"PSS0.PSS_CLK_B1_5->PSS0_CLK_B1_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_5"
},
"PSS0.PSS_CLK_B1_6->PSS0_CLK_B1_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_6"
},
"PSS0.PSS_CLK_B1_7->PSS0_CLK_B1_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_7"
},
"PSS0.PSS_CLK_B1_8->PSS0_CLK_B1_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_8"
},
"PSS0.PSS_CLK_B1_9->PSS0_CLK_B1_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_9"
},
"PSS0.PSS_CLK_B1_10->PSS0_CLK_B1_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_10"
},
"PSS0.PSS_CLK_B1_11->PSS0_CLK_B1_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_11"
},
"PSS0.PSS_CLK_B1_12->PSS0_CLK_B1_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_12"
},
"PSS0.PSS_CLK_B1_13->PSS0_CLK_B1_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_13"
},
"PSS0.PSS_CLK_B1_14->PSS0_CLK_B1_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_14"
},
"PSS0.PSS_CLK_B1_15->PSS0_CLK_B1_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_15"
},
"PSS0.PSS_CLK_B1_16->PSS0_CLK_B1_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_16"
},
"PSS0.PSS_CLK_B1_17->PSS0_CLK_B1_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_17"
},
"PSS0.PSS_CLK_B1_18->PSS0_CLK_B1_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_18"
},
"PSS0.PSS_CLK_B1_19->PSS0_CLK_B1_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_CLK_B1_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_CLK_B1_19"
},
"PSS0.PSS_IMUX_B0_0->PSS0_IMUX_B0_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_0"
},
"PSS0.PSS_IMUX_B0_1->PSS0_IMUX_B0_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_1"
},
"PSS0.PSS_IMUX_B0_2->PSS0_IMUX_B0_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_2"
},
"PSS0.PSS_IMUX_B0_3->PSS0_IMUX_B0_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_3"
},
"PSS0.PSS_IMUX_B0_4->PSS0_IMUX_B0_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_4"
},
"PSS0.PSS_IMUX_B0_5->PSS0_IMUX_B0_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_5"
},
"PSS0.PSS_IMUX_B0_6->PSS0_IMUX_B0_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_6"
},
"PSS0.PSS_IMUX_B0_7->PSS0_IMUX_B0_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_7"
},
"PSS0.PSS_IMUX_B0_8->PSS0_IMUX_B0_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_8"
},
"PSS0.PSS_IMUX_B0_9->PSS0_IMUX_B0_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_9"
},
"PSS0.PSS_IMUX_B0_10->PSS0_IMUX_B0_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_10"
},
"PSS0.PSS_IMUX_B0_11->PSS0_IMUX_B0_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_11"
},
"PSS0.PSS_IMUX_B0_12->PSS0_IMUX_B0_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_12"
},
"PSS0.PSS_IMUX_B0_13->PSS0_IMUX_B0_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_13"
},
"PSS0.PSS_IMUX_B0_14->PSS0_IMUX_B0_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_14"
},
"PSS0.PSS_IMUX_B0_15->PSS0_IMUX_B0_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_15"
},
"PSS0.PSS_IMUX_B0_16->PSS0_IMUX_B0_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_16"
},
"PSS0.PSS_IMUX_B0_17->PSS0_IMUX_B0_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_17"
},
"PSS0.PSS_IMUX_B0_18->PSS0_IMUX_B0_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_18"
},
"PSS0.PSS_IMUX_B0_19->PSS0_IMUX_B0_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B0_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B0_19"
},
"PSS0.PSS_IMUX_B1_0->PSS0_IMUX_B1_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_0"
},
"PSS0.PSS_IMUX_B1_1->PSS0_IMUX_B1_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_1"
},
"PSS0.PSS_IMUX_B1_2->PSS0_IMUX_B1_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_2"
},
"PSS0.PSS_IMUX_B1_3->PSS0_IMUX_B1_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_3"
},
"PSS0.PSS_IMUX_B1_4->PSS0_IMUX_B1_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_4"
},
"PSS0.PSS_IMUX_B1_5->PSS0_IMUX_B1_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_5"
},
"PSS0.PSS_IMUX_B1_6->PSS0_IMUX_B1_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_6"
},
"PSS0.PSS_IMUX_B1_7->PSS0_IMUX_B1_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_7"
},
"PSS0.PSS_IMUX_B1_8->PSS0_IMUX_B1_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_8"
},
"PSS0.PSS_IMUX_B1_9->PSS0_IMUX_B1_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_9"
},
"PSS0.PSS_IMUX_B1_10->PSS0_IMUX_B1_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_10"
},
"PSS0.PSS_IMUX_B1_11->PSS0_IMUX_B1_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_11"
},
"PSS0.PSS_IMUX_B1_12->PSS0_IMUX_B1_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_12"
},
"PSS0.PSS_IMUX_B1_13->PSS0_IMUX_B1_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_13"
},
"PSS0.PSS_IMUX_B1_14->PSS0_IMUX_B1_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_14"
},
"PSS0.PSS_IMUX_B1_15->PSS0_IMUX_B1_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_15"
},
"PSS0.PSS_IMUX_B1_16->PSS0_IMUX_B1_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_16"
},
"PSS0.PSS_IMUX_B1_17->PSS0_IMUX_B1_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_17"
},
"PSS0.PSS_IMUX_B1_18->PSS0_IMUX_B1_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_18"
},
"PSS0.PSS_IMUX_B1_19->PSS0_IMUX_B1_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B1_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B1_19"
},
"PSS0.PSS_IMUX_B2_0->PSS0_IMUX_B2_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_0"
},
"PSS0.PSS_IMUX_B2_1->PSS0_IMUX_B2_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_1"
},
"PSS0.PSS_IMUX_B2_2->PSS0_IMUX_B2_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_2"
},
"PSS0.PSS_IMUX_B2_3->PSS0_IMUX_B2_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_3"
},
"PSS0.PSS_IMUX_B2_4->PSS0_IMUX_B2_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_4"
},
"PSS0.PSS_IMUX_B2_5->PSS0_IMUX_B2_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_5"
},
"PSS0.PSS_IMUX_B2_6->PSS0_IMUX_B2_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_6"
},
"PSS0.PSS_IMUX_B2_7->PSS0_IMUX_B2_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_7"
},
"PSS0.PSS_IMUX_B2_8->PSS0_IMUX_B2_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_8"
},
"PSS0.PSS_IMUX_B2_9->PSS0_IMUX_B2_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_9"
},
"PSS0.PSS_IMUX_B2_10->PSS0_IMUX_B2_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_10"
},
"PSS0.PSS_IMUX_B2_11->PSS0_IMUX_B2_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_11"
},
"PSS0.PSS_IMUX_B2_12->PSS0_IMUX_B2_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_12"
},
"PSS0.PSS_IMUX_B2_13->PSS0_IMUX_B2_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_13"
},
"PSS0.PSS_IMUX_B2_14->PSS0_IMUX_B2_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_14"
},
"PSS0.PSS_IMUX_B2_15->PSS0_IMUX_B2_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_15"
},
"PSS0.PSS_IMUX_B2_16->PSS0_IMUX_B2_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_16"
},
"PSS0.PSS_IMUX_B2_17->PSS0_IMUX_B2_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_17"
},
"PSS0.PSS_IMUX_B2_18->PSS0_IMUX_B2_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_18"
},
"PSS0.PSS_IMUX_B2_19->PSS0_IMUX_B2_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B2_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B2_19"
},
"PSS0.PSS_IMUX_B3_0->PSS0_IMUX_B3_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_0"
},
"PSS0.PSS_IMUX_B3_1->PSS0_IMUX_B3_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_1"
},
"PSS0.PSS_IMUX_B3_2->PSS0_IMUX_B3_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_2"
},
"PSS0.PSS_IMUX_B3_3->PSS0_IMUX_B3_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_3"
},
"PSS0.PSS_IMUX_B3_4->PSS0_IMUX_B3_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_4"
},
"PSS0.PSS_IMUX_B3_5->PSS0_IMUX_B3_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_5"
},
"PSS0.PSS_IMUX_B3_6->PSS0_IMUX_B3_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_6"
},
"PSS0.PSS_IMUX_B3_7->PSS0_IMUX_B3_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_7"
},
"PSS0.PSS_IMUX_B3_8->PSS0_IMUX_B3_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_8"
},
"PSS0.PSS_IMUX_B3_9->PSS0_IMUX_B3_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_9"
},
"PSS0.PSS_IMUX_B3_10->PSS0_IMUX_B3_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_10"
},
"PSS0.PSS_IMUX_B3_11->PSS0_IMUX_B3_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_11"
},
"PSS0.PSS_IMUX_B3_12->PSS0_IMUX_B3_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_12"
},
"PSS0.PSS_IMUX_B3_13->PSS0_IMUX_B3_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_13"
},
"PSS0.PSS_IMUX_B3_14->PSS0_IMUX_B3_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_14"
},
"PSS0.PSS_IMUX_B3_15->PSS0_IMUX_B3_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_15"
},
"PSS0.PSS_IMUX_B3_16->PSS0_IMUX_B3_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_16"
},
"PSS0.PSS_IMUX_B3_17->PSS0_IMUX_B3_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_17"
},
"PSS0.PSS_IMUX_B3_18->PSS0_IMUX_B3_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_18"
},
"PSS0.PSS_IMUX_B3_19->PSS0_IMUX_B3_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B3_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B3_19"
},
"PSS0.PSS_IMUX_B4_0->PSS0_IMUX_B4_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_0"
},
"PSS0.PSS_IMUX_B4_1->PSS0_IMUX_B4_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_1"
},
"PSS0.PSS_IMUX_B4_2->PSS0_IMUX_B4_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_2"
},
"PSS0.PSS_IMUX_B4_3->PSS0_IMUX_B4_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_3"
},
"PSS0.PSS_IMUX_B4_4->PSS0_IMUX_B4_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_4"
},
"PSS0.PSS_IMUX_B4_5->PSS0_IMUX_B4_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_5"
},
"PSS0.PSS_IMUX_B4_6->PSS0_IMUX_B4_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_6"
},
"PSS0.PSS_IMUX_B4_7->PSS0_IMUX_B4_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_7"
},
"PSS0.PSS_IMUX_B4_8->PSS0_IMUX_B4_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_8"
},
"PSS0.PSS_IMUX_B4_9->PSS0_IMUX_B4_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_9"
},
"PSS0.PSS_IMUX_B4_10->PSS0_IMUX_B4_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_10"
},
"PSS0.PSS_IMUX_B4_11->PSS0_IMUX_B4_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_11"
},
"PSS0.PSS_IMUX_B4_12->PSS0_IMUX_B4_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_12"
},
"PSS0.PSS_IMUX_B4_13->PSS0_IMUX_B4_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_13"
},
"PSS0.PSS_IMUX_B4_14->PSS0_IMUX_B4_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_14"
},
"PSS0.PSS_IMUX_B4_15->PSS0_IMUX_B4_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_15"
},
"PSS0.PSS_IMUX_B4_16->PSS0_IMUX_B4_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_16"
},
"PSS0.PSS_IMUX_B4_17->PSS0_IMUX_B4_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_17"
},
"PSS0.PSS_IMUX_B4_18->PSS0_IMUX_B4_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_18"
},
"PSS0.PSS_IMUX_B4_19->PSS0_IMUX_B4_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B4_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B4_19"
},
"PSS0.PSS_IMUX_B5_0->PSS0_IMUX_B5_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_0"
},
"PSS0.PSS_IMUX_B5_1->PSS0_IMUX_B5_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_1"
},
"PSS0.PSS_IMUX_B5_2->PSS0_IMUX_B5_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_2"
},
"PSS0.PSS_IMUX_B5_3->PSS0_IMUX_B5_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_3"
},
"PSS0.PSS_IMUX_B5_4->PSS0_IMUX_B5_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_4"
},
"PSS0.PSS_IMUX_B5_5->PSS0_IMUX_B5_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_5"
},
"PSS0.PSS_IMUX_B5_6->PSS0_IMUX_B5_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_6"
},
"PSS0.PSS_IMUX_B5_7->PSS0_IMUX_B5_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_7"
},
"PSS0.PSS_IMUX_B5_8->PSS0_IMUX_B5_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_8"
},
"PSS0.PSS_IMUX_B5_9->PSS0_IMUX_B5_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_9"
},
"PSS0.PSS_IMUX_B5_10->PSS0_IMUX_B5_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_10"
},
"PSS0.PSS_IMUX_B5_11->PSS0_IMUX_B5_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_11"
},
"PSS0.PSS_IMUX_B5_12->PSS0_IMUX_B5_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_12"
},
"PSS0.PSS_IMUX_B5_13->PSS0_IMUX_B5_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_13"
},
"PSS0.PSS_IMUX_B5_14->PSS0_IMUX_B5_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_14"
},
"PSS0.PSS_IMUX_B5_15->PSS0_IMUX_B5_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_15"
},
"PSS0.PSS_IMUX_B5_16->PSS0_IMUX_B5_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_16"
},
"PSS0.PSS_IMUX_B5_17->PSS0_IMUX_B5_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_17"
},
"PSS0.PSS_IMUX_B5_18->PSS0_IMUX_B5_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_18"
},
"PSS0.PSS_IMUX_B5_19->PSS0_IMUX_B5_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B5_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B5_19"
},
"PSS0.PSS_IMUX_B6_0->PSS0_IMUX_B6_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_0"
},
"PSS0.PSS_IMUX_B6_1->PSS0_IMUX_B6_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_1"
},
"PSS0.PSS_IMUX_B6_2->PSS0_IMUX_B6_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_2"
},
"PSS0.PSS_IMUX_B6_3->PSS0_IMUX_B6_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_3"
},
"PSS0.PSS_IMUX_B6_4->PSS0_IMUX_B6_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_4"
},
"PSS0.PSS_IMUX_B6_5->PSS0_IMUX_B6_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_5"
},
"PSS0.PSS_IMUX_B6_6->PSS0_IMUX_B6_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_6"
},
"PSS0.PSS_IMUX_B6_7->PSS0_IMUX_B6_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_7"
},
"PSS0.PSS_IMUX_B6_8->PSS0_IMUX_B6_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_8"
},
"PSS0.PSS_IMUX_B6_9->PSS0_IMUX_B6_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_9"
},
"PSS0.PSS_IMUX_B6_10->PSS0_IMUX_B6_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_10"
},
"PSS0.PSS_IMUX_B6_11->PSS0_IMUX_B6_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_11"
},
"PSS0.PSS_IMUX_B6_12->PSS0_IMUX_B6_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_12"
},
"PSS0.PSS_IMUX_B6_13->PSS0_IMUX_B6_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_13"
},
"PSS0.PSS_IMUX_B6_14->PSS0_IMUX_B6_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_14"
},
"PSS0.PSS_IMUX_B6_15->PSS0_IMUX_B6_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_15"
},
"PSS0.PSS_IMUX_B6_16->PSS0_IMUX_B6_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_16"
},
"PSS0.PSS_IMUX_B6_17->PSS0_IMUX_B6_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_17"
},
"PSS0.PSS_IMUX_B6_18->PSS0_IMUX_B6_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_18"
},
"PSS0.PSS_IMUX_B6_19->PSS0_IMUX_B6_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B6_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B6_19"
},
"PSS0.PSS_IMUX_B7_0->PSS0_IMUX_B7_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_0"
},
"PSS0.PSS_IMUX_B7_1->PSS0_IMUX_B7_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_1"
},
"PSS0.PSS_IMUX_B7_2->PSS0_IMUX_B7_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_2"
},
"PSS0.PSS_IMUX_B7_3->PSS0_IMUX_B7_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_3"
},
"PSS0.PSS_IMUX_B7_4->PSS0_IMUX_B7_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_4"
},
"PSS0.PSS_IMUX_B7_5->PSS0_IMUX_B7_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_5"
},
"PSS0.PSS_IMUX_B7_6->PSS0_IMUX_B7_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_6"
},
"PSS0.PSS_IMUX_B7_7->PSS0_IMUX_B7_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_7"
},
"PSS0.PSS_IMUX_B7_8->PSS0_IMUX_B7_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_8"
},
"PSS0.PSS_IMUX_B7_9->PSS0_IMUX_B7_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_9"
},
"PSS0.PSS_IMUX_B7_10->PSS0_IMUX_B7_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_10"
},
"PSS0.PSS_IMUX_B7_11->PSS0_IMUX_B7_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_11"
},
"PSS0.PSS_IMUX_B7_12->PSS0_IMUX_B7_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_12"
},
"PSS0.PSS_IMUX_B7_13->PSS0_IMUX_B7_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_13"
},
"PSS0.PSS_IMUX_B7_14->PSS0_IMUX_B7_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_14"
},
"PSS0.PSS_IMUX_B7_15->PSS0_IMUX_B7_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_15"
},
"PSS0.PSS_IMUX_B7_16->PSS0_IMUX_B7_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_16"
},
"PSS0.PSS_IMUX_B7_17->PSS0_IMUX_B7_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_17"
},
"PSS0.PSS_IMUX_B7_18->PSS0_IMUX_B7_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_18"
},
"PSS0.PSS_IMUX_B7_19->PSS0_IMUX_B7_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B7_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B7_19"
},
"PSS0.PSS_IMUX_B8_0->PSS0_IMUX_B8_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_0"
},
"PSS0.PSS_IMUX_B8_1->PSS0_IMUX_B8_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_1"
},
"PSS0.PSS_IMUX_B8_2->PSS0_IMUX_B8_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_2"
},
"PSS0.PSS_IMUX_B8_3->PSS0_IMUX_B8_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_3"
},
"PSS0.PSS_IMUX_B8_4->PSS0_IMUX_B8_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_4"
},
"PSS0.PSS_IMUX_B8_5->PSS0_IMUX_B8_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_5"
},
"PSS0.PSS_IMUX_B8_6->PSS0_IMUX_B8_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_6"
},
"PSS0.PSS_IMUX_B8_7->PSS0_IMUX_B8_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_7"
},
"PSS0.PSS_IMUX_B8_8->PSS0_IMUX_B8_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_8"
},
"PSS0.PSS_IMUX_B8_9->PSS0_IMUX_B8_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_9"
},
"PSS0.PSS_IMUX_B8_10->PSS0_IMUX_B8_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_10"
},
"PSS0.PSS_IMUX_B8_11->PSS0_IMUX_B8_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_11"
},
"PSS0.PSS_IMUX_B8_12->PSS0_IMUX_B8_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_12"
},
"PSS0.PSS_IMUX_B8_13->PSS0_IMUX_B8_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_13"
},
"PSS0.PSS_IMUX_B8_14->PSS0_IMUX_B8_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_14"
},
"PSS0.PSS_IMUX_B8_15->PSS0_IMUX_B8_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_15"
},
"PSS0.PSS_IMUX_B8_16->PSS0_IMUX_B8_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_16"
},
"PSS0.PSS_IMUX_B8_17->PSS0_IMUX_B8_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_17"
},
"PSS0.PSS_IMUX_B8_18->PSS0_IMUX_B8_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_18"
},
"PSS0.PSS_IMUX_B8_19->PSS0_IMUX_B8_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B8_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B8_19"
},
"PSS0.PSS_IMUX_B9_0->PSS0_IMUX_B9_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_0"
},
"PSS0.PSS_IMUX_B9_1->PSS0_IMUX_B9_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_1"
},
"PSS0.PSS_IMUX_B9_2->PSS0_IMUX_B9_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_2"
},
"PSS0.PSS_IMUX_B9_3->PSS0_IMUX_B9_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_3"
},
"PSS0.PSS_IMUX_B9_4->PSS0_IMUX_B9_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_4"
},
"PSS0.PSS_IMUX_B9_5->PSS0_IMUX_B9_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_5"
},
"PSS0.PSS_IMUX_B9_6->PSS0_IMUX_B9_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_6"
},
"PSS0.PSS_IMUX_B9_7->PSS0_IMUX_B9_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_7"
},
"PSS0.PSS_IMUX_B9_8->PSS0_IMUX_B9_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_8"
},
"PSS0.PSS_IMUX_B9_9->PSS0_IMUX_B9_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_9"
},
"PSS0.PSS_IMUX_B9_10->PSS0_IMUX_B9_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_10"
},
"PSS0.PSS_IMUX_B9_11->PSS0_IMUX_B9_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_11"
},
"PSS0.PSS_IMUX_B9_12->PSS0_IMUX_B9_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_12"
},
"PSS0.PSS_IMUX_B9_13->PSS0_IMUX_B9_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_13"
},
"PSS0.PSS_IMUX_B9_14->PSS0_IMUX_B9_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_14"
},
"PSS0.PSS_IMUX_B9_15->PSS0_IMUX_B9_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_15"
},
"PSS0.PSS_IMUX_B9_16->PSS0_IMUX_B9_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_16"
},
"PSS0.PSS_IMUX_B9_17->PSS0_IMUX_B9_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_17"
},
"PSS0.PSS_IMUX_B9_18->PSS0_IMUX_B9_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_18"
},
"PSS0.PSS_IMUX_B9_19->PSS0_IMUX_B9_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B9_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B9_19"
},
"PSS0.PSS_IMUX_B10_0->PSS0_IMUX_B10_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_0"
},
"PSS0.PSS_IMUX_B10_1->PSS0_IMUX_B10_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_1"
},
"PSS0.PSS_IMUX_B10_2->PSS0_IMUX_B10_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_2"
},
"PSS0.PSS_IMUX_B10_3->PSS0_IMUX_B10_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_3"
},
"PSS0.PSS_IMUX_B10_4->PSS0_IMUX_B10_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_4"
},
"PSS0.PSS_IMUX_B10_5->PSS0_IMUX_B10_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_5"
},
"PSS0.PSS_IMUX_B10_6->PSS0_IMUX_B10_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_6"
},
"PSS0.PSS_IMUX_B10_7->PSS0_IMUX_B10_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_7"
},
"PSS0.PSS_IMUX_B10_8->PSS0_IMUX_B10_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_8"
},
"PSS0.PSS_IMUX_B10_9->PSS0_IMUX_B10_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_9"
},
"PSS0.PSS_IMUX_B10_10->PSS0_IMUX_B10_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_10"
},
"PSS0.PSS_IMUX_B10_11->PSS0_IMUX_B10_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_11"
},
"PSS0.PSS_IMUX_B10_12->PSS0_IMUX_B10_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_12"
},
"PSS0.PSS_IMUX_B10_13->PSS0_IMUX_B10_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_13"
},
"PSS0.PSS_IMUX_B10_14->PSS0_IMUX_B10_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_14"
},
"PSS0.PSS_IMUX_B10_15->PSS0_IMUX_B10_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_15"
},
"PSS0.PSS_IMUX_B10_16->PSS0_IMUX_B10_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_16"
},
"PSS0.PSS_IMUX_B10_17->PSS0_IMUX_B10_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_17"
},
"PSS0.PSS_IMUX_B10_18->PSS0_IMUX_B10_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_18"
},
"PSS0.PSS_IMUX_B10_19->PSS0_IMUX_B10_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B10_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B10_19"
},
"PSS0.PSS_IMUX_B11_0->PSS0_IMUX_B11_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_0"
},
"PSS0.PSS_IMUX_B11_1->PSS0_IMUX_B11_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_1"
},
"PSS0.PSS_IMUX_B11_2->PSS0_IMUX_B11_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_2"
},
"PSS0.PSS_IMUX_B11_3->PSS0_IMUX_B11_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_3"
},
"PSS0.PSS_IMUX_B11_4->PSS0_IMUX_B11_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_4"
},
"PSS0.PSS_IMUX_B11_5->PSS0_IMUX_B11_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_5"
},
"PSS0.PSS_IMUX_B11_6->PSS0_IMUX_B11_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_6"
},
"PSS0.PSS_IMUX_B11_7->PSS0_IMUX_B11_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_7"
},
"PSS0.PSS_IMUX_B11_8->PSS0_IMUX_B11_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_8"
},
"PSS0.PSS_IMUX_B11_9->PSS0_IMUX_B11_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_9"
},
"PSS0.PSS_IMUX_B11_10->PSS0_IMUX_B11_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_10"
},
"PSS0.PSS_IMUX_B11_11->PSS0_IMUX_B11_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_11"
},
"PSS0.PSS_IMUX_B11_12->PSS0_IMUX_B11_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_12"
},
"PSS0.PSS_IMUX_B11_13->PSS0_IMUX_B11_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_13"
},
"PSS0.PSS_IMUX_B11_14->PSS0_IMUX_B11_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_14"
},
"PSS0.PSS_IMUX_B11_15->PSS0_IMUX_B11_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_15"
},
"PSS0.PSS_IMUX_B11_16->PSS0_IMUX_B11_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_16"
},
"PSS0.PSS_IMUX_B11_17->PSS0_IMUX_B11_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_17"
},
"PSS0.PSS_IMUX_B11_18->PSS0_IMUX_B11_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_18"
},
"PSS0.PSS_IMUX_B11_19->PSS0_IMUX_B11_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B11_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B11_19"
},
"PSS0.PSS_IMUX_B12_0->PSS0_IMUX_B12_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_0"
},
"PSS0.PSS_IMUX_B12_1->PSS0_IMUX_B12_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_1"
},
"PSS0.PSS_IMUX_B12_2->PSS0_IMUX_B12_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_2"
},
"PSS0.PSS_IMUX_B12_3->PSS0_IMUX_B12_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_3"
},
"PSS0.PSS_IMUX_B12_4->PSS0_IMUX_B12_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_4"
},
"PSS0.PSS_IMUX_B12_5->PSS0_IMUX_B12_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_5"
},
"PSS0.PSS_IMUX_B12_6->PSS0_IMUX_B12_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_6"
},
"PSS0.PSS_IMUX_B12_7->PSS0_IMUX_B12_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_7"
},
"PSS0.PSS_IMUX_B12_8->PSS0_IMUX_B12_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_8"
},
"PSS0.PSS_IMUX_B12_9->PSS0_IMUX_B12_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_9"
},
"PSS0.PSS_IMUX_B12_10->PSS0_IMUX_B12_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_10"
},
"PSS0.PSS_IMUX_B12_11->PSS0_IMUX_B12_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_11"
},
"PSS0.PSS_IMUX_B12_12->PSS0_IMUX_B12_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_12"
},
"PSS0.PSS_IMUX_B12_13->PSS0_IMUX_B12_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_13"
},
"PSS0.PSS_IMUX_B12_14->PSS0_IMUX_B12_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_14"
},
"PSS0.PSS_IMUX_B12_15->PSS0_IMUX_B12_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_15"
},
"PSS0.PSS_IMUX_B12_16->PSS0_IMUX_B12_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_16"
},
"PSS0.PSS_IMUX_B12_17->PSS0_IMUX_B12_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_17"
},
"PSS0.PSS_IMUX_B12_18->PSS0_IMUX_B12_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_18"
},
"PSS0.PSS_IMUX_B12_19->PSS0_IMUX_B12_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B12_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B12_19"
},
"PSS0.PSS_IMUX_B13_0->PSS0_IMUX_B13_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_0"
},
"PSS0.PSS_IMUX_B13_1->PSS0_IMUX_B13_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_1"
},
"PSS0.PSS_IMUX_B13_2->PSS0_IMUX_B13_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_2"
},
"PSS0.PSS_IMUX_B13_3->PSS0_IMUX_B13_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_3"
},
"PSS0.PSS_IMUX_B13_4->PSS0_IMUX_B13_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_4"
},
"PSS0.PSS_IMUX_B13_5->PSS0_IMUX_B13_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_5"
},
"PSS0.PSS_IMUX_B13_6->PSS0_IMUX_B13_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_6"
},
"PSS0.PSS_IMUX_B13_7->PSS0_IMUX_B13_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_7"
},
"PSS0.PSS_IMUX_B13_8->PSS0_IMUX_B13_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_8"
},
"PSS0.PSS_IMUX_B13_9->PSS0_IMUX_B13_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_9"
},
"PSS0.PSS_IMUX_B13_10->PSS0_IMUX_B13_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_10"
},
"PSS0.PSS_IMUX_B13_11->PSS0_IMUX_B13_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_11"
},
"PSS0.PSS_IMUX_B13_12->PSS0_IMUX_B13_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_12"
},
"PSS0.PSS_IMUX_B13_13->PSS0_IMUX_B13_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_13"
},
"PSS0.PSS_IMUX_B13_14->PSS0_IMUX_B13_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_14"
},
"PSS0.PSS_IMUX_B13_15->PSS0_IMUX_B13_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_15"
},
"PSS0.PSS_IMUX_B13_16->PSS0_IMUX_B13_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_16"
},
"PSS0.PSS_IMUX_B13_17->PSS0_IMUX_B13_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_17"
},
"PSS0.PSS_IMUX_B13_18->PSS0_IMUX_B13_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_18"
},
"PSS0.PSS_IMUX_B13_19->PSS0_IMUX_B13_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B13_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B13_19"
},
"PSS0.PSS_IMUX_B14_0->PSS0_IMUX_B14_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_0"
},
"PSS0.PSS_IMUX_B14_1->PSS0_IMUX_B14_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_1"
},
"PSS0.PSS_IMUX_B14_2->PSS0_IMUX_B14_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_2"
},
"PSS0.PSS_IMUX_B14_3->PSS0_IMUX_B14_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_3"
},
"PSS0.PSS_IMUX_B14_4->PSS0_IMUX_B14_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_4"
},
"PSS0.PSS_IMUX_B14_5->PSS0_IMUX_B14_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_5"
},
"PSS0.PSS_IMUX_B14_6->PSS0_IMUX_B14_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_6"
},
"PSS0.PSS_IMUX_B14_7->PSS0_IMUX_B14_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_7"
},
"PSS0.PSS_IMUX_B14_8->PSS0_IMUX_B14_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_8"
},
"PSS0.PSS_IMUX_B14_9->PSS0_IMUX_B14_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_9"
},
"PSS0.PSS_IMUX_B14_10->PSS0_IMUX_B14_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_10"
},
"PSS0.PSS_IMUX_B14_11->PSS0_IMUX_B14_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_11"
},
"PSS0.PSS_IMUX_B14_12->PSS0_IMUX_B14_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_12"
},
"PSS0.PSS_IMUX_B14_13->PSS0_IMUX_B14_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_13"
},
"PSS0.PSS_IMUX_B14_14->PSS0_IMUX_B14_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_14"
},
"PSS0.PSS_IMUX_B14_15->PSS0_IMUX_B14_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_15"
},
"PSS0.PSS_IMUX_B14_16->PSS0_IMUX_B14_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_16"
},
"PSS0.PSS_IMUX_B14_17->PSS0_IMUX_B14_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_17"
},
"PSS0.PSS_IMUX_B14_18->PSS0_IMUX_B14_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_18"
},
"PSS0.PSS_IMUX_B14_19->PSS0_IMUX_B14_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B14_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B14_19"
},
"PSS0.PSS_IMUX_B15_0->PSS0_IMUX_B15_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_0"
},
"PSS0.PSS_IMUX_B15_1->PSS0_IMUX_B15_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_1"
},
"PSS0.PSS_IMUX_B15_2->PSS0_IMUX_B15_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_2"
},
"PSS0.PSS_IMUX_B15_3->PSS0_IMUX_B15_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_3"
},
"PSS0.PSS_IMUX_B15_4->PSS0_IMUX_B15_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_4"
},
"PSS0.PSS_IMUX_B15_5->PSS0_IMUX_B15_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_5"
},
"PSS0.PSS_IMUX_B15_6->PSS0_IMUX_B15_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_6"
},
"PSS0.PSS_IMUX_B15_7->PSS0_IMUX_B15_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_7"
},
"PSS0.PSS_IMUX_B15_8->PSS0_IMUX_B15_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_8"
},
"PSS0.PSS_IMUX_B15_9->PSS0_IMUX_B15_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_9"
},
"PSS0.PSS_IMUX_B15_10->PSS0_IMUX_B15_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_10"
},
"PSS0.PSS_IMUX_B15_11->PSS0_IMUX_B15_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_11"
},
"PSS0.PSS_IMUX_B15_12->PSS0_IMUX_B15_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_12"
},
"PSS0.PSS_IMUX_B15_13->PSS0_IMUX_B15_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_13"
},
"PSS0.PSS_IMUX_B15_14->PSS0_IMUX_B15_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_14"
},
"PSS0.PSS_IMUX_B15_15->PSS0_IMUX_B15_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_15"
},
"PSS0.PSS_IMUX_B15_16->PSS0_IMUX_B15_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_16"
},
"PSS0.PSS_IMUX_B15_17->PSS0_IMUX_B15_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_17"
},
"PSS0.PSS_IMUX_B15_18->PSS0_IMUX_B15_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_18"
},
"PSS0.PSS_IMUX_B15_19->PSS0_IMUX_B15_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B15_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B15_19"
},
"PSS0.PSS_IMUX_B16_0->PSS0_IMUX_B16_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_0"
},
"PSS0.PSS_IMUX_B16_1->PSS0_IMUX_B16_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_1"
},
"PSS0.PSS_IMUX_B16_2->PSS0_IMUX_B16_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_2"
},
"PSS0.PSS_IMUX_B16_3->PSS0_IMUX_B16_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_3"
},
"PSS0.PSS_IMUX_B16_4->PSS0_IMUX_B16_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_4"
},
"PSS0.PSS_IMUX_B16_5->PSS0_IMUX_B16_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_5"
},
"PSS0.PSS_IMUX_B16_6->PSS0_IMUX_B16_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_6"
},
"PSS0.PSS_IMUX_B16_7->PSS0_IMUX_B16_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_7"
},
"PSS0.PSS_IMUX_B16_8->PSS0_IMUX_B16_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_8"
},
"PSS0.PSS_IMUX_B16_9->PSS0_IMUX_B16_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_9"
},
"PSS0.PSS_IMUX_B16_10->PSS0_IMUX_B16_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_10"
},
"PSS0.PSS_IMUX_B16_11->PSS0_IMUX_B16_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_11"
},
"PSS0.PSS_IMUX_B16_12->PSS0_IMUX_B16_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_12"
},
"PSS0.PSS_IMUX_B16_13->PSS0_IMUX_B16_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_13"
},
"PSS0.PSS_IMUX_B16_14->PSS0_IMUX_B16_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_14"
},
"PSS0.PSS_IMUX_B16_15->PSS0_IMUX_B16_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_15"
},
"PSS0.PSS_IMUX_B16_16->PSS0_IMUX_B16_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_16"
},
"PSS0.PSS_IMUX_B16_17->PSS0_IMUX_B16_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_17"
},
"PSS0.PSS_IMUX_B16_18->PSS0_IMUX_B16_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_18"
},
"PSS0.PSS_IMUX_B16_19->PSS0_IMUX_B16_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B16_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B16_19"
},
"PSS0.PSS_IMUX_B17_0->PSS0_IMUX_B17_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_0"
},
"PSS0.PSS_IMUX_B17_1->PSS0_IMUX_B17_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_1"
},
"PSS0.PSS_IMUX_B17_2->PSS0_IMUX_B17_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_2"
},
"PSS0.PSS_IMUX_B17_3->PSS0_IMUX_B17_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_3"
},
"PSS0.PSS_IMUX_B17_4->PSS0_IMUX_B17_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_4"
},
"PSS0.PSS_IMUX_B17_5->PSS0_IMUX_B17_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_5"
},
"PSS0.PSS_IMUX_B17_6->PSS0_IMUX_B17_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_6"
},
"PSS0.PSS_IMUX_B17_7->PSS0_IMUX_B17_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_7"
},
"PSS0.PSS_IMUX_B17_8->PSS0_IMUX_B17_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_8"
},
"PSS0.PSS_IMUX_B17_9->PSS0_IMUX_B17_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_9"
},
"PSS0.PSS_IMUX_B17_10->PSS0_IMUX_B17_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_10"
},
"PSS0.PSS_IMUX_B17_11->PSS0_IMUX_B17_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_11"
},
"PSS0.PSS_IMUX_B17_12->PSS0_IMUX_B17_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_12"
},
"PSS0.PSS_IMUX_B17_13->PSS0_IMUX_B17_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_13"
},
"PSS0.PSS_IMUX_B17_14->PSS0_IMUX_B17_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_14"
},
"PSS0.PSS_IMUX_B17_15->PSS0_IMUX_B17_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_15"
},
"PSS0.PSS_IMUX_B17_16->PSS0_IMUX_B17_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_16"
},
"PSS0.PSS_IMUX_B17_17->PSS0_IMUX_B17_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_17"
},
"PSS0.PSS_IMUX_B17_18->PSS0_IMUX_B17_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_18"
},
"PSS0.PSS_IMUX_B17_19->PSS0_IMUX_B17_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B17_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B17_19"
},
"PSS0.PSS_IMUX_B18_0->PSS0_IMUX_B18_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_0"
},
"PSS0.PSS_IMUX_B18_1->PSS0_IMUX_B18_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_1"
},
"PSS0.PSS_IMUX_B18_2->PSS0_IMUX_B18_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_2"
},
"PSS0.PSS_IMUX_B18_3->PSS0_IMUX_B18_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_3"
},
"PSS0.PSS_IMUX_B18_4->PSS0_IMUX_B18_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_4"
},
"PSS0.PSS_IMUX_B18_5->PSS0_IMUX_B18_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_5"
},
"PSS0.PSS_IMUX_B18_6->PSS0_IMUX_B18_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_6"
},
"PSS0.PSS_IMUX_B18_7->PSS0_IMUX_B18_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_7"
},
"PSS0.PSS_IMUX_B18_8->PSS0_IMUX_B18_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_8"
},
"PSS0.PSS_IMUX_B18_9->PSS0_IMUX_B18_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_9"
},
"PSS0.PSS_IMUX_B18_10->PSS0_IMUX_B18_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_10"
},
"PSS0.PSS_IMUX_B18_11->PSS0_IMUX_B18_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_11"
},
"PSS0.PSS_IMUX_B18_12->PSS0_IMUX_B18_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_12"
},
"PSS0.PSS_IMUX_B18_13->PSS0_IMUX_B18_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_13"
},
"PSS0.PSS_IMUX_B18_14->PSS0_IMUX_B18_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_14"
},
"PSS0.PSS_IMUX_B18_15->PSS0_IMUX_B18_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_15"
},
"PSS0.PSS_IMUX_B18_16->PSS0_IMUX_B18_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_16"
},
"PSS0.PSS_IMUX_B18_17->PSS0_IMUX_B18_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_17"
},
"PSS0.PSS_IMUX_B18_18->PSS0_IMUX_B18_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_18"
},
"PSS0.PSS_IMUX_B18_19->PSS0_IMUX_B18_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B18_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B18_19"
},
"PSS0.PSS_IMUX_B19_0->PSS0_IMUX_B19_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_0"
},
"PSS0.PSS_IMUX_B19_1->PSS0_IMUX_B19_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_1"
},
"PSS0.PSS_IMUX_B19_2->PSS0_IMUX_B19_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_2"
},
"PSS0.PSS_IMUX_B19_3->PSS0_IMUX_B19_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_3"
},
"PSS0.PSS_IMUX_B19_4->PSS0_IMUX_B19_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_4"
},
"PSS0.PSS_IMUX_B19_5->PSS0_IMUX_B19_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_5"
},
"PSS0.PSS_IMUX_B19_6->PSS0_IMUX_B19_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_6"
},
"PSS0.PSS_IMUX_B19_7->PSS0_IMUX_B19_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_7"
},
"PSS0.PSS_IMUX_B19_8->PSS0_IMUX_B19_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_8"
},
"PSS0.PSS_IMUX_B19_9->PSS0_IMUX_B19_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_9"
},
"PSS0.PSS_IMUX_B19_10->PSS0_IMUX_B19_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_10"
},
"PSS0.PSS_IMUX_B19_11->PSS0_IMUX_B19_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_11"
},
"PSS0.PSS_IMUX_B19_12->PSS0_IMUX_B19_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_12"
},
"PSS0.PSS_IMUX_B19_13->PSS0_IMUX_B19_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_13"
},
"PSS0.PSS_IMUX_B19_14->PSS0_IMUX_B19_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_14"
},
"PSS0.PSS_IMUX_B19_15->PSS0_IMUX_B19_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_15"
},
"PSS0.PSS_IMUX_B19_16->PSS0_IMUX_B19_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_16"
},
"PSS0.PSS_IMUX_B19_17->PSS0_IMUX_B19_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_17"
},
"PSS0.PSS_IMUX_B19_18->PSS0_IMUX_B19_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_18"
},
"PSS0.PSS_IMUX_B19_19->PSS0_IMUX_B19_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B19_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B19_19"
},
"PSS0.PSS_IMUX_B20_0->PSS0_IMUX_B20_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_0"
},
"PSS0.PSS_IMUX_B20_1->PSS0_IMUX_B20_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_1"
},
"PSS0.PSS_IMUX_B20_2->PSS0_IMUX_B20_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_2"
},
"PSS0.PSS_IMUX_B20_3->PSS0_IMUX_B20_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_3"
},
"PSS0.PSS_IMUX_B20_4->PSS0_IMUX_B20_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_4"
},
"PSS0.PSS_IMUX_B20_5->PSS0_IMUX_B20_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_5"
},
"PSS0.PSS_IMUX_B20_6->PSS0_IMUX_B20_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_6"
},
"PSS0.PSS_IMUX_B20_7->PSS0_IMUX_B20_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_7"
},
"PSS0.PSS_IMUX_B20_8->PSS0_IMUX_B20_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_8"
},
"PSS0.PSS_IMUX_B20_9->PSS0_IMUX_B20_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_9"
},
"PSS0.PSS_IMUX_B20_10->PSS0_IMUX_B20_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_10"
},
"PSS0.PSS_IMUX_B20_11->PSS0_IMUX_B20_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_11"
},
"PSS0.PSS_IMUX_B20_12->PSS0_IMUX_B20_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_12"
},
"PSS0.PSS_IMUX_B20_13->PSS0_IMUX_B20_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_13"
},
"PSS0.PSS_IMUX_B20_14->PSS0_IMUX_B20_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_14"
},
"PSS0.PSS_IMUX_B20_15->PSS0_IMUX_B20_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_15"
},
"PSS0.PSS_IMUX_B20_16->PSS0_IMUX_B20_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_16"
},
"PSS0.PSS_IMUX_B20_17->PSS0_IMUX_B20_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_17"
},
"PSS0.PSS_IMUX_B20_18->PSS0_IMUX_B20_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_18"
},
"PSS0.PSS_IMUX_B20_19->PSS0_IMUX_B20_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B20_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B20_19"
},
"PSS0.PSS_IMUX_B21_0->PSS0_IMUX_B21_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_0"
},
"PSS0.PSS_IMUX_B21_1->PSS0_IMUX_B21_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_1"
},
"PSS0.PSS_IMUX_B21_2->PSS0_IMUX_B21_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_2"
},
"PSS0.PSS_IMUX_B21_3->PSS0_IMUX_B21_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_3"
},
"PSS0.PSS_IMUX_B21_4->PSS0_IMUX_B21_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_4"
},
"PSS0.PSS_IMUX_B21_5->PSS0_IMUX_B21_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_5"
},
"PSS0.PSS_IMUX_B21_6->PSS0_IMUX_B21_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_6"
},
"PSS0.PSS_IMUX_B21_7->PSS0_IMUX_B21_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_7"
},
"PSS0.PSS_IMUX_B21_8->PSS0_IMUX_B21_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_8"
},
"PSS0.PSS_IMUX_B21_9->PSS0_IMUX_B21_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_9"
},
"PSS0.PSS_IMUX_B21_10->PSS0_IMUX_B21_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_10"
},
"PSS0.PSS_IMUX_B21_11->PSS0_IMUX_B21_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_11"
},
"PSS0.PSS_IMUX_B21_12->PSS0_IMUX_B21_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_12"
},
"PSS0.PSS_IMUX_B21_13->PSS0_IMUX_B21_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_13"
},
"PSS0.PSS_IMUX_B21_14->PSS0_IMUX_B21_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_14"
},
"PSS0.PSS_IMUX_B21_15->PSS0_IMUX_B21_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_15"
},
"PSS0.PSS_IMUX_B21_16->PSS0_IMUX_B21_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_16"
},
"PSS0.PSS_IMUX_B21_17->PSS0_IMUX_B21_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_17"
},
"PSS0.PSS_IMUX_B21_18->PSS0_IMUX_B21_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_18"
},
"PSS0.PSS_IMUX_B21_19->PSS0_IMUX_B21_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B21_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B21_19"
},
"PSS0.PSS_IMUX_B22_0->PSS0_IMUX_B22_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_0"
},
"PSS0.PSS_IMUX_B22_1->PSS0_IMUX_B22_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_1"
},
"PSS0.PSS_IMUX_B22_2->PSS0_IMUX_B22_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_2"
},
"PSS0.PSS_IMUX_B22_3->PSS0_IMUX_B22_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_3"
},
"PSS0.PSS_IMUX_B22_4->PSS0_IMUX_B22_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_4"
},
"PSS0.PSS_IMUX_B22_5->PSS0_IMUX_B22_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_5"
},
"PSS0.PSS_IMUX_B22_6->PSS0_IMUX_B22_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_6"
},
"PSS0.PSS_IMUX_B22_7->PSS0_IMUX_B22_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_7"
},
"PSS0.PSS_IMUX_B22_8->PSS0_IMUX_B22_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_8"
},
"PSS0.PSS_IMUX_B22_9->PSS0_IMUX_B22_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_9"
},
"PSS0.PSS_IMUX_B22_10->PSS0_IMUX_B22_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_10"
},
"PSS0.PSS_IMUX_B22_11->PSS0_IMUX_B22_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_11"
},
"PSS0.PSS_IMUX_B22_12->PSS0_IMUX_B22_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_12"
},
"PSS0.PSS_IMUX_B22_13->PSS0_IMUX_B22_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_13"
},
"PSS0.PSS_IMUX_B22_14->PSS0_IMUX_B22_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_14"
},
"PSS0.PSS_IMUX_B22_15->PSS0_IMUX_B22_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_15"
},
"PSS0.PSS_IMUX_B22_16->PSS0_IMUX_B22_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_16"
},
"PSS0.PSS_IMUX_B22_17->PSS0_IMUX_B22_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_17"
},
"PSS0.PSS_IMUX_B22_18->PSS0_IMUX_B22_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_18"
},
"PSS0.PSS_IMUX_B22_19->PSS0_IMUX_B22_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B22_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B22_19"
},
"PSS0.PSS_IMUX_B23_0->PSS0_IMUX_B23_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_0"
},
"PSS0.PSS_IMUX_B23_1->PSS0_IMUX_B23_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_1"
},
"PSS0.PSS_IMUX_B23_2->PSS0_IMUX_B23_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_2"
},
"PSS0.PSS_IMUX_B23_3->PSS0_IMUX_B23_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_3"
},
"PSS0.PSS_IMUX_B23_4->PSS0_IMUX_B23_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_4"
},
"PSS0.PSS_IMUX_B23_5->PSS0_IMUX_B23_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_5"
},
"PSS0.PSS_IMUX_B23_6->PSS0_IMUX_B23_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_6"
},
"PSS0.PSS_IMUX_B23_7->PSS0_IMUX_B23_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_7"
},
"PSS0.PSS_IMUX_B23_8->PSS0_IMUX_B23_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_8"
},
"PSS0.PSS_IMUX_B23_9->PSS0_IMUX_B23_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_9"
},
"PSS0.PSS_IMUX_B23_10->PSS0_IMUX_B23_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_10"
},
"PSS0.PSS_IMUX_B23_11->PSS0_IMUX_B23_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_11"
},
"PSS0.PSS_IMUX_B23_12->PSS0_IMUX_B23_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_12"
},
"PSS0.PSS_IMUX_B23_13->PSS0_IMUX_B23_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_13"
},
"PSS0.PSS_IMUX_B23_14->PSS0_IMUX_B23_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_14"
},
"PSS0.PSS_IMUX_B23_15->PSS0_IMUX_B23_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_15"
},
"PSS0.PSS_IMUX_B23_16->PSS0_IMUX_B23_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_16"
},
"PSS0.PSS_IMUX_B23_17->PSS0_IMUX_B23_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_17"
},
"PSS0.PSS_IMUX_B23_18->PSS0_IMUX_B23_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_18"
},
"PSS0.PSS_IMUX_B23_19->PSS0_IMUX_B23_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B23_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B23_19"
},
"PSS0.PSS_IMUX_B24_0->PSS0_IMUX_B24_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_0"
},
"PSS0.PSS_IMUX_B24_1->PSS0_IMUX_B24_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_1"
},
"PSS0.PSS_IMUX_B24_2->PSS0_IMUX_B24_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_2"
},
"PSS0.PSS_IMUX_B24_3->PSS0_IMUX_B24_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_3"
},
"PSS0.PSS_IMUX_B24_4->PSS0_IMUX_B24_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_4"
},
"PSS0.PSS_IMUX_B24_5->PSS0_IMUX_B24_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_5"
},
"PSS0.PSS_IMUX_B24_6->PSS0_IMUX_B24_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_6"
},
"PSS0.PSS_IMUX_B24_7->PSS0_IMUX_B24_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_7"
},
"PSS0.PSS_IMUX_B24_8->PSS0_IMUX_B24_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_8"
},
"PSS0.PSS_IMUX_B24_9->PSS0_IMUX_B24_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_9"
},
"PSS0.PSS_IMUX_B24_10->PSS0_IMUX_B24_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_10"
},
"PSS0.PSS_IMUX_B24_11->PSS0_IMUX_B24_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_11"
},
"PSS0.PSS_IMUX_B24_12->PSS0_IMUX_B24_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_12"
},
"PSS0.PSS_IMUX_B24_13->PSS0_IMUX_B24_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_13"
},
"PSS0.PSS_IMUX_B24_14->PSS0_IMUX_B24_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_14"
},
"PSS0.PSS_IMUX_B24_15->PSS0_IMUX_B24_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_15"
},
"PSS0.PSS_IMUX_B24_16->PSS0_IMUX_B24_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_16"
},
"PSS0.PSS_IMUX_B24_17->PSS0_IMUX_B24_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_17"
},
"PSS0.PSS_IMUX_B24_18->PSS0_IMUX_B24_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_18"
},
"PSS0.PSS_IMUX_B24_19->PSS0_IMUX_B24_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B24_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B24_19"
},
"PSS0.PSS_IMUX_B25_0->PSS0_IMUX_B25_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_0"
},
"PSS0.PSS_IMUX_B25_1->PSS0_IMUX_B25_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_1"
},
"PSS0.PSS_IMUX_B25_2->PSS0_IMUX_B25_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_2"
},
"PSS0.PSS_IMUX_B25_3->PSS0_IMUX_B25_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_3"
},
"PSS0.PSS_IMUX_B25_4->PSS0_IMUX_B25_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_4"
},
"PSS0.PSS_IMUX_B25_5->PSS0_IMUX_B25_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_5"
},
"PSS0.PSS_IMUX_B25_6->PSS0_IMUX_B25_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_6"
},
"PSS0.PSS_IMUX_B25_7->PSS0_IMUX_B25_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_7"
},
"PSS0.PSS_IMUX_B25_8->PSS0_IMUX_B25_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_8"
},
"PSS0.PSS_IMUX_B25_9->PSS0_IMUX_B25_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_9"
},
"PSS0.PSS_IMUX_B25_10->PSS0_IMUX_B25_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_10"
},
"PSS0.PSS_IMUX_B25_11->PSS0_IMUX_B25_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_11"
},
"PSS0.PSS_IMUX_B25_12->PSS0_IMUX_B25_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_12"
},
"PSS0.PSS_IMUX_B25_13->PSS0_IMUX_B25_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_13"
},
"PSS0.PSS_IMUX_B25_14->PSS0_IMUX_B25_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_14"
},
"PSS0.PSS_IMUX_B25_15->PSS0_IMUX_B25_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_15"
},
"PSS0.PSS_IMUX_B25_16->PSS0_IMUX_B25_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_16"
},
"PSS0.PSS_IMUX_B25_17->PSS0_IMUX_B25_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_17"
},
"PSS0.PSS_IMUX_B25_18->PSS0_IMUX_B25_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_18"
},
"PSS0.PSS_IMUX_B25_19->PSS0_IMUX_B25_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B25_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B25_19"
},
"PSS0.PSS_IMUX_B26_0->PSS0_IMUX_B26_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_0"
},
"PSS0.PSS_IMUX_B26_1->PSS0_IMUX_B26_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_1"
},
"PSS0.PSS_IMUX_B26_2->PSS0_IMUX_B26_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_2"
},
"PSS0.PSS_IMUX_B26_3->PSS0_IMUX_B26_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_3"
},
"PSS0.PSS_IMUX_B26_4->PSS0_IMUX_B26_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_4"
},
"PSS0.PSS_IMUX_B26_5->PSS0_IMUX_B26_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_5"
},
"PSS0.PSS_IMUX_B26_6->PSS0_IMUX_B26_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_6"
},
"PSS0.PSS_IMUX_B26_7->PSS0_IMUX_B26_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_7"
},
"PSS0.PSS_IMUX_B26_8->PSS0_IMUX_B26_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_8"
},
"PSS0.PSS_IMUX_B26_9->PSS0_IMUX_B26_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_9"
},
"PSS0.PSS_IMUX_B26_10->PSS0_IMUX_B26_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_10"
},
"PSS0.PSS_IMUX_B26_11->PSS0_IMUX_B26_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_11"
},
"PSS0.PSS_IMUX_B26_12->PSS0_IMUX_B26_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_12"
},
"PSS0.PSS_IMUX_B26_13->PSS0_IMUX_B26_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_13"
},
"PSS0.PSS_IMUX_B26_14->PSS0_IMUX_B26_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_14"
},
"PSS0.PSS_IMUX_B26_15->PSS0_IMUX_B26_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_15"
},
"PSS0.PSS_IMUX_B26_16->PSS0_IMUX_B26_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_16"
},
"PSS0.PSS_IMUX_B26_17->PSS0_IMUX_B26_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_17"
},
"PSS0.PSS_IMUX_B26_18->PSS0_IMUX_B26_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_18"
},
"PSS0.PSS_IMUX_B26_19->PSS0_IMUX_B26_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B26_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B26_19"
},
"PSS0.PSS_IMUX_B27_0->PSS0_IMUX_B27_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_0"
},
"PSS0.PSS_IMUX_B27_1->PSS0_IMUX_B27_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_1"
},
"PSS0.PSS_IMUX_B27_2->PSS0_IMUX_B27_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_2"
},
"PSS0.PSS_IMUX_B27_3->PSS0_IMUX_B27_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_3"
},
"PSS0.PSS_IMUX_B27_4->PSS0_IMUX_B27_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_4"
},
"PSS0.PSS_IMUX_B27_5->PSS0_IMUX_B27_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_5"
},
"PSS0.PSS_IMUX_B27_6->PSS0_IMUX_B27_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_6"
},
"PSS0.PSS_IMUX_B27_7->PSS0_IMUX_B27_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_7"
},
"PSS0.PSS_IMUX_B27_8->PSS0_IMUX_B27_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_8"
},
"PSS0.PSS_IMUX_B27_9->PSS0_IMUX_B27_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_9"
},
"PSS0.PSS_IMUX_B27_10->PSS0_IMUX_B27_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_10"
},
"PSS0.PSS_IMUX_B27_11->PSS0_IMUX_B27_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_11"
},
"PSS0.PSS_IMUX_B27_12->PSS0_IMUX_B27_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_12"
},
"PSS0.PSS_IMUX_B27_13->PSS0_IMUX_B27_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_13"
},
"PSS0.PSS_IMUX_B27_14->PSS0_IMUX_B27_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_14"
},
"PSS0.PSS_IMUX_B27_15->PSS0_IMUX_B27_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_15"
},
"PSS0.PSS_IMUX_B27_16->PSS0_IMUX_B27_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_16"
},
"PSS0.PSS_IMUX_B27_17->PSS0_IMUX_B27_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_17"
},
"PSS0.PSS_IMUX_B27_18->PSS0_IMUX_B27_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_18"
},
"PSS0.PSS_IMUX_B27_19->PSS0_IMUX_B27_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B27_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B27_19"
},
"PSS0.PSS_IMUX_B28_0->PSS0_IMUX_B28_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_0"
},
"PSS0.PSS_IMUX_B28_1->PSS0_IMUX_B28_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_1"
},
"PSS0.PSS_IMUX_B28_2->PSS0_IMUX_B28_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_2"
},
"PSS0.PSS_IMUX_B28_3->PSS0_IMUX_B28_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_3"
},
"PSS0.PSS_IMUX_B28_4->PSS0_IMUX_B28_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_4"
},
"PSS0.PSS_IMUX_B28_5->PSS0_IMUX_B28_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_5"
},
"PSS0.PSS_IMUX_B28_6->PSS0_IMUX_B28_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_6"
},
"PSS0.PSS_IMUX_B28_7->PSS0_IMUX_B28_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_7"
},
"PSS0.PSS_IMUX_B28_8->PSS0_IMUX_B28_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_8"
},
"PSS0.PSS_IMUX_B28_9->PSS0_IMUX_B28_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_9"
},
"PSS0.PSS_IMUX_B28_10->PSS0_IMUX_B28_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_10"
},
"PSS0.PSS_IMUX_B28_11->PSS0_IMUX_B28_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_11"
},
"PSS0.PSS_IMUX_B28_12->PSS0_IMUX_B28_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_12"
},
"PSS0.PSS_IMUX_B28_13->PSS0_IMUX_B28_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_13"
},
"PSS0.PSS_IMUX_B28_14->PSS0_IMUX_B28_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_14"
},
"PSS0.PSS_IMUX_B28_15->PSS0_IMUX_B28_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_15"
},
"PSS0.PSS_IMUX_B28_16->PSS0_IMUX_B28_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_16"
},
"PSS0.PSS_IMUX_B28_17->PSS0_IMUX_B28_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_17"
},
"PSS0.PSS_IMUX_B28_18->PSS0_IMUX_B28_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_18"
},
"PSS0.PSS_IMUX_B28_19->PSS0_IMUX_B28_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B28_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B28_19"
},
"PSS0.PSS_IMUX_B29_0->PSS0_IMUX_B29_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_0"
},
"PSS0.PSS_IMUX_B29_1->PSS0_IMUX_B29_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_1"
},
"PSS0.PSS_IMUX_B29_2->PSS0_IMUX_B29_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_2"
},
"PSS0.PSS_IMUX_B29_3->PSS0_IMUX_B29_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_3"
},
"PSS0.PSS_IMUX_B29_4->PSS0_IMUX_B29_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_4"
},
"PSS0.PSS_IMUX_B29_5->PSS0_IMUX_B29_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_5"
},
"PSS0.PSS_IMUX_B29_6->PSS0_IMUX_B29_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_6"
},
"PSS0.PSS_IMUX_B29_7->PSS0_IMUX_B29_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_7"
},
"PSS0.PSS_IMUX_B29_8->PSS0_IMUX_B29_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_8"
},
"PSS0.PSS_IMUX_B29_9->PSS0_IMUX_B29_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_9"
},
"PSS0.PSS_IMUX_B29_10->PSS0_IMUX_B29_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_10"
},
"PSS0.PSS_IMUX_B29_11->PSS0_IMUX_B29_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_11"
},
"PSS0.PSS_IMUX_B29_12->PSS0_IMUX_B29_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_12"
},
"PSS0.PSS_IMUX_B29_13->PSS0_IMUX_B29_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_13"
},
"PSS0.PSS_IMUX_B29_14->PSS0_IMUX_B29_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_14"
},
"PSS0.PSS_IMUX_B29_15->PSS0_IMUX_B29_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_15"
},
"PSS0.PSS_IMUX_B29_16->PSS0_IMUX_B29_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_16"
},
"PSS0.PSS_IMUX_B29_17->PSS0_IMUX_B29_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_17"
},
"PSS0.PSS_IMUX_B29_18->PSS0_IMUX_B29_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_18"
},
"PSS0.PSS_IMUX_B29_19->PSS0_IMUX_B29_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B29_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B29_19"
},
"PSS0.PSS_IMUX_B30_0->PSS0_IMUX_B30_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_0"
},
"PSS0.PSS_IMUX_B30_1->PSS0_IMUX_B30_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_1"
},
"PSS0.PSS_IMUX_B30_2->PSS0_IMUX_B30_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_2"
},
"PSS0.PSS_IMUX_B30_3->PSS0_IMUX_B30_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_3"
},
"PSS0.PSS_IMUX_B30_4->PSS0_IMUX_B30_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_4"
},
"PSS0.PSS_IMUX_B30_5->PSS0_IMUX_B30_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_5"
},
"PSS0.PSS_IMUX_B30_6->PSS0_IMUX_B30_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_6"
},
"PSS0.PSS_IMUX_B30_7->PSS0_IMUX_B30_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_7"
},
"PSS0.PSS_IMUX_B30_8->PSS0_IMUX_B30_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_8"
},
"PSS0.PSS_IMUX_B30_9->PSS0_IMUX_B30_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_9"
},
"PSS0.PSS_IMUX_B30_10->PSS0_IMUX_B30_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_10"
},
"PSS0.PSS_IMUX_B30_11->PSS0_IMUX_B30_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_11"
},
"PSS0.PSS_IMUX_B30_12->PSS0_IMUX_B30_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_12"
},
"PSS0.PSS_IMUX_B30_13->PSS0_IMUX_B30_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_13"
},
"PSS0.PSS_IMUX_B30_14->PSS0_IMUX_B30_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_14"
},
"PSS0.PSS_IMUX_B30_15->PSS0_IMUX_B30_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_15"
},
"PSS0.PSS_IMUX_B30_16->PSS0_IMUX_B30_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_16"
},
"PSS0.PSS_IMUX_B30_17->PSS0_IMUX_B30_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_17"
},
"PSS0.PSS_IMUX_B30_18->PSS0_IMUX_B30_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_18"
},
"PSS0.PSS_IMUX_B30_19->PSS0_IMUX_B30_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B30_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B30_19"
},
"PSS0.PSS_IMUX_B31_0->PSS0_IMUX_B31_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_0"
},
"PSS0.PSS_IMUX_B31_1->PSS0_IMUX_B31_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_1"
},
"PSS0.PSS_IMUX_B31_2->PSS0_IMUX_B31_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_2"
},
"PSS0.PSS_IMUX_B31_3->PSS0_IMUX_B31_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_3"
},
"PSS0.PSS_IMUX_B31_4->PSS0_IMUX_B31_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_4"
},
"PSS0.PSS_IMUX_B31_5->PSS0_IMUX_B31_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_5"
},
"PSS0.PSS_IMUX_B31_6->PSS0_IMUX_B31_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_6"
},
"PSS0.PSS_IMUX_B31_7->PSS0_IMUX_B31_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_7"
},
"PSS0.PSS_IMUX_B31_8->PSS0_IMUX_B31_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_8"
},
"PSS0.PSS_IMUX_B31_9->PSS0_IMUX_B31_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_9"
},
"PSS0.PSS_IMUX_B31_10->PSS0_IMUX_B31_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_10"
},
"PSS0.PSS_IMUX_B31_11->PSS0_IMUX_B31_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_11"
},
"PSS0.PSS_IMUX_B31_12->PSS0_IMUX_B31_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_12"
},
"PSS0.PSS_IMUX_B31_13->PSS0_IMUX_B31_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_13"
},
"PSS0.PSS_IMUX_B31_14->PSS0_IMUX_B31_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_14"
},
"PSS0.PSS_IMUX_B31_15->PSS0_IMUX_B31_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_15"
},
"PSS0.PSS_IMUX_B31_16->PSS0_IMUX_B31_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_16"
},
"PSS0.PSS_IMUX_B31_17->PSS0_IMUX_B31_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_17"
},
"PSS0.PSS_IMUX_B31_18->PSS0_IMUX_B31_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_18"
},
"PSS0.PSS_IMUX_B31_19->PSS0_IMUX_B31_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B31_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B31_19"
},
"PSS0.PSS_IMUX_B32_0->PSS0_IMUX_B32_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_0"
},
"PSS0.PSS_IMUX_B32_1->PSS0_IMUX_B32_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_1"
},
"PSS0.PSS_IMUX_B32_2->PSS0_IMUX_B32_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_2"
},
"PSS0.PSS_IMUX_B32_3->PSS0_IMUX_B32_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_3"
},
"PSS0.PSS_IMUX_B32_4->PSS0_IMUX_B32_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_4"
},
"PSS0.PSS_IMUX_B32_5->PSS0_IMUX_B32_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_5"
},
"PSS0.PSS_IMUX_B32_6->PSS0_IMUX_B32_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_6"
},
"PSS0.PSS_IMUX_B32_7->PSS0_IMUX_B32_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_7"
},
"PSS0.PSS_IMUX_B32_8->PSS0_IMUX_B32_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_8"
},
"PSS0.PSS_IMUX_B32_9->PSS0_IMUX_B32_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_9"
},
"PSS0.PSS_IMUX_B32_10->PSS0_IMUX_B32_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_10"
},
"PSS0.PSS_IMUX_B32_11->PSS0_IMUX_B32_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_11"
},
"PSS0.PSS_IMUX_B32_12->PSS0_IMUX_B32_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_12"
},
"PSS0.PSS_IMUX_B32_13->PSS0_IMUX_B32_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_13"
},
"PSS0.PSS_IMUX_B32_14->PSS0_IMUX_B32_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_14"
},
"PSS0.PSS_IMUX_B32_15->PSS0_IMUX_B32_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_15"
},
"PSS0.PSS_IMUX_B32_16->PSS0_IMUX_B32_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_16"
},
"PSS0.PSS_IMUX_B32_17->PSS0_IMUX_B32_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_17"
},
"PSS0.PSS_IMUX_B32_18->PSS0_IMUX_B32_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_18"
},
"PSS0.PSS_IMUX_B32_19->PSS0_IMUX_B32_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B32_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B32_19"
},
"PSS0.PSS_IMUX_B33_0->PSS0_IMUX_B33_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_0"
},
"PSS0.PSS_IMUX_B33_1->PSS0_IMUX_B33_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_1"
},
"PSS0.PSS_IMUX_B33_2->PSS0_IMUX_B33_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_2"
},
"PSS0.PSS_IMUX_B33_3->PSS0_IMUX_B33_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_3"
},
"PSS0.PSS_IMUX_B33_4->PSS0_IMUX_B33_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_4"
},
"PSS0.PSS_IMUX_B33_5->PSS0_IMUX_B33_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_5"
},
"PSS0.PSS_IMUX_B33_6->PSS0_IMUX_B33_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_6"
},
"PSS0.PSS_IMUX_B33_7->PSS0_IMUX_B33_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_7"
},
"PSS0.PSS_IMUX_B33_8->PSS0_IMUX_B33_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_8"
},
"PSS0.PSS_IMUX_B33_9->PSS0_IMUX_B33_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_9"
},
"PSS0.PSS_IMUX_B33_10->PSS0_IMUX_B33_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_10"
},
"PSS0.PSS_IMUX_B33_11->PSS0_IMUX_B33_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_11"
},
"PSS0.PSS_IMUX_B33_12->PSS0_IMUX_B33_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_12"
},
"PSS0.PSS_IMUX_B33_13->PSS0_IMUX_B33_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_13"
},
"PSS0.PSS_IMUX_B33_14->PSS0_IMUX_B33_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_14"
},
"PSS0.PSS_IMUX_B33_15->PSS0_IMUX_B33_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_15"
},
"PSS0.PSS_IMUX_B33_16->PSS0_IMUX_B33_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_16"
},
"PSS0.PSS_IMUX_B33_17->PSS0_IMUX_B33_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_17"
},
"PSS0.PSS_IMUX_B33_18->PSS0_IMUX_B33_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_18"
},
"PSS0.PSS_IMUX_B33_19->PSS0_IMUX_B33_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B33_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B33_19"
},
"PSS0.PSS_IMUX_B34_0->PSS0_IMUX_B34_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_0"
},
"PSS0.PSS_IMUX_B34_1->PSS0_IMUX_B34_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_1"
},
"PSS0.PSS_IMUX_B34_2->PSS0_IMUX_B34_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_2"
},
"PSS0.PSS_IMUX_B34_3->PSS0_IMUX_B34_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_3"
},
"PSS0.PSS_IMUX_B34_4->PSS0_IMUX_B34_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_4"
},
"PSS0.PSS_IMUX_B34_5->PSS0_IMUX_B34_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_5"
},
"PSS0.PSS_IMUX_B34_6->PSS0_IMUX_B34_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_6"
},
"PSS0.PSS_IMUX_B34_7->PSS0_IMUX_B34_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_7"
},
"PSS0.PSS_IMUX_B34_8->PSS0_IMUX_B34_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_8"
},
"PSS0.PSS_IMUX_B34_9->PSS0_IMUX_B34_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_9"
},
"PSS0.PSS_IMUX_B34_10->PSS0_IMUX_B34_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_10"
},
"PSS0.PSS_IMUX_B34_11->PSS0_IMUX_B34_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_11"
},
"PSS0.PSS_IMUX_B34_12->PSS0_IMUX_B34_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_12"
},
"PSS0.PSS_IMUX_B34_13->PSS0_IMUX_B34_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_13"
},
"PSS0.PSS_IMUX_B34_14->PSS0_IMUX_B34_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_14"
},
"PSS0.PSS_IMUX_B34_15->PSS0_IMUX_B34_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_15"
},
"PSS0.PSS_IMUX_B34_16->PSS0_IMUX_B34_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_16"
},
"PSS0.PSS_IMUX_B34_17->PSS0_IMUX_B34_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_17"
},
"PSS0.PSS_IMUX_B34_18->PSS0_IMUX_B34_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_18"
},
"PSS0.PSS_IMUX_B34_19->PSS0_IMUX_B34_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B34_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B34_19"
},
"PSS0.PSS_IMUX_B35_0->PSS0_IMUX_B35_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_0"
},
"PSS0.PSS_IMUX_B35_1->PSS0_IMUX_B35_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_1"
},
"PSS0.PSS_IMUX_B35_2->PSS0_IMUX_B35_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_2"
},
"PSS0.PSS_IMUX_B35_3->PSS0_IMUX_B35_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_3"
},
"PSS0.PSS_IMUX_B35_4->PSS0_IMUX_B35_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_4"
},
"PSS0.PSS_IMUX_B35_5->PSS0_IMUX_B35_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_5"
},
"PSS0.PSS_IMUX_B35_6->PSS0_IMUX_B35_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_6"
},
"PSS0.PSS_IMUX_B35_7->PSS0_IMUX_B35_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_7"
},
"PSS0.PSS_IMUX_B35_8->PSS0_IMUX_B35_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_8"
},
"PSS0.PSS_IMUX_B35_9->PSS0_IMUX_B35_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_9"
},
"PSS0.PSS_IMUX_B35_10->PSS0_IMUX_B35_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_10"
},
"PSS0.PSS_IMUX_B35_11->PSS0_IMUX_B35_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_11"
},
"PSS0.PSS_IMUX_B35_12->PSS0_IMUX_B35_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_12"
},
"PSS0.PSS_IMUX_B35_13->PSS0_IMUX_B35_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_13"
},
"PSS0.PSS_IMUX_B35_14->PSS0_IMUX_B35_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_14"
},
"PSS0.PSS_IMUX_B35_15->PSS0_IMUX_B35_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_15"
},
"PSS0.PSS_IMUX_B35_16->PSS0_IMUX_B35_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_16"
},
"PSS0.PSS_IMUX_B35_17->PSS0_IMUX_B35_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_17"
},
"PSS0.PSS_IMUX_B35_18->PSS0_IMUX_B35_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_18"
},
"PSS0.PSS_IMUX_B35_19->PSS0_IMUX_B35_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B35_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B35_19"
},
"PSS0.PSS_IMUX_B36_0->PSS0_IMUX_B36_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_0"
},
"PSS0.PSS_IMUX_B36_1->PSS0_IMUX_B36_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_1"
},
"PSS0.PSS_IMUX_B36_2->PSS0_IMUX_B36_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_2"
},
"PSS0.PSS_IMUX_B36_3->PSS0_IMUX_B36_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_3"
},
"PSS0.PSS_IMUX_B36_4->PSS0_IMUX_B36_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_4"
},
"PSS0.PSS_IMUX_B36_5->PSS0_IMUX_B36_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_5"
},
"PSS0.PSS_IMUX_B36_6->PSS0_IMUX_B36_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_6"
},
"PSS0.PSS_IMUX_B36_7->PSS0_IMUX_B36_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_7"
},
"PSS0.PSS_IMUX_B36_8->PSS0_IMUX_B36_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_8"
},
"PSS0.PSS_IMUX_B36_9->PSS0_IMUX_B36_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_9"
},
"PSS0.PSS_IMUX_B36_10->PSS0_IMUX_B36_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_10"
},
"PSS0.PSS_IMUX_B36_11->PSS0_IMUX_B36_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_11"
},
"PSS0.PSS_IMUX_B36_12->PSS0_IMUX_B36_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_12"
},
"PSS0.PSS_IMUX_B36_13->PSS0_IMUX_B36_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_13"
},
"PSS0.PSS_IMUX_B36_14->PSS0_IMUX_B36_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_14"
},
"PSS0.PSS_IMUX_B36_15->PSS0_IMUX_B36_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_15"
},
"PSS0.PSS_IMUX_B36_16->PSS0_IMUX_B36_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_16"
},
"PSS0.PSS_IMUX_B36_17->PSS0_IMUX_B36_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_17"
},
"PSS0.PSS_IMUX_B36_18->PSS0_IMUX_B36_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_18"
},
"PSS0.PSS_IMUX_B36_19->PSS0_IMUX_B36_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B36_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B36_19"
},
"PSS0.PSS_IMUX_B37_0->PSS0_IMUX_B37_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_0"
},
"PSS0.PSS_IMUX_B37_1->PSS0_IMUX_B37_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_1"
},
"PSS0.PSS_IMUX_B37_2->PSS0_IMUX_B37_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_2"
},
"PSS0.PSS_IMUX_B37_3->PSS0_IMUX_B37_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_3"
},
"PSS0.PSS_IMUX_B37_4->PSS0_IMUX_B37_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_4"
},
"PSS0.PSS_IMUX_B37_5->PSS0_IMUX_B37_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_5"
},
"PSS0.PSS_IMUX_B37_6->PSS0_IMUX_B37_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_6"
},
"PSS0.PSS_IMUX_B37_7->PSS0_IMUX_B37_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_7"
},
"PSS0.PSS_IMUX_B37_8->PSS0_IMUX_B37_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_8"
},
"PSS0.PSS_IMUX_B37_9->PSS0_IMUX_B37_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_9"
},
"PSS0.PSS_IMUX_B37_10->PSS0_IMUX_B37_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_10"
},
"PSS0.PSS_IMUX_B37_11->PSS0_IMUX_B37_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_11"
},
"PSS0.PSS_IMUX_B37_12->PSS0_IMUX_B37_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_12"
},
"PSS0.PSS_IMUX_B37_13->PSS0_IMUX_B37_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_13"
},
"PSS0.PSS_IMUX_B37_14->PSS0_IMUX_B37_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_14"
},
"PSS0.PSS_IMUX_B37_15->PSS0_IMUX_B37_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_15"
},
"PSS0.PSS_IMUX_B37_16->PSS0_IMUX_B37_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_16"
},
"PSS0.PSS_IMUX_B37_17->PSS0_IMUX_B37_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_17"
},
"PSS0.PSS_IMUX_B37_18->PSS0_IMUX_B37_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_18"
},
"PSS0.PSS_IMUX_B37_19->PSS0_IMUX_B37_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B37_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B37_19"
},
"PSS0.PSS_IMUX_B38_0->PSS0_IMUX_B38_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_0"
},
"PSS0.PSS_IMUX_B38_1->PSS0_IMUX_B38_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_1"
},
"PSS0.PSS_IMUX_B38_2->PSS0_IMUX_B38_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_2"
},
"PSS0.PSS_IMUX_B38_3->PSS0_IMUX_B38_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_3"
},
"PSS0.PSS_IMUX_B38_4->PSS0_IMUX_B38_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_4"
},
"PSS0.PSS_IMUX_B38_5->PSS0_IMUX_B38_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_5"
},
"PSS0.PSS_IMUX_B38_6->PSS0_IMUX_B38_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_6"
},
"PSS0.PSS_IMUX_B38_7->PSS0_IMUX_B38_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_7"
},
"PSS0.PSS_IMUX_B38_8->PSS0_IMUX_B38_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_8"
},
"PSS0.PSS_IMUX_B38_9->PSS0_IMUX_B38_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_9"
},
"PSS0.PSS_IMUX_B38_10->PSS0_IMUX_B38_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_10"
},
"PSS0.PSS_IMUX_B38_11->PSS0_IMUX_B38_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_11"
},
"PSS0.PSS_IMUX_B38_12->PSS0_IMUX_B38_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_12"
},
"PSS0.PSS_IMUX_B38_13->PSS0_IMUX_B38_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_13"
},
"PSS0.PSS_IMUX_B38_14->PSS0_IMUX_B38_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_14"
},
"PSS0.PSS_IMUX_B38_15->PSS0_IMUX_B38_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_15"
},
"PSS0.PSS_IMUX_B38_16->PSS0_IMUX_B38_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_16"
},
"PSS0.PSS_IMUX_B38_17->PSS0_IMUX_B38_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_17"
},
"PSS0.PSS_IMUX_B38_18->PSS0_IMUX_B38_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_18"
},
"PSS0.PSS_IMUX_B38_19->PSS0_IMUX_B38_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B38_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B38_19"
},
"PSS0.PSS_IMUX_B39_0->PSS0_IMUX_B39_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_0"
},
"PSS0.PSS_IMUX_B39_1->PSS0_IMUX_B39_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_1"
},
"PSS0.PSS_IMUX_B39_2->PSS0_IMUX_B39_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_2"
},
"PSS0.PSS_IMUX_B39_3->PSS0_IMUX_B39_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_3"
},
"PSS0.PSS_IMUX_B39_4->PSS0_IMUX_B39_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_4"
},
"PSS0.PSS_IMUX_B39_5->PSS0_IMUX_B39_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_5"
},
"PSS0.PSS_IMUX_B39_6->PSS0_IMUX_B39_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_6"
},
"PSS0.PSS_IMUX_B39_7->PSS0_IMUX_B39_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_7"
},
"PSS0.PSS_IMUX_B39_8->PSS0_IMUX_B39_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_8"
},
"PSS0.PSS_IMUX_B39_9->PSS0_IMUX_B39_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_9"
},
"PSS0.PSS_IMUX_B39_10->PSS0_IMUX_B39_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_10"
},
"PSS0.PSS_IMUX_B39_11->PSS0_IMUX_B39_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_11"
},
"PSS0.PSS_IMUX_B39_12->PSS0_IMUX_B39_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_12"
},
"PSS0.PSS_IMUX_B39_13->PSS0_IMUX_B39_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_13"
},
"PSS0.PSS_IMUX_B39_14->PSS0_IMUX_B39_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_14"
},
"PSS0.PSS_IMUX_B39_15->PSS0_IMUX_B39_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_15"
},
"PSS0.PSS_IMUX_B39_16->PSS0_IMUX_B39_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_16"
},
"PSS0.PSS_IMUX_B39_17->PSS0_IMUX_B39_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_17"
},
"PSS0.PSS_IMUX_B39_18->PSS0_IMUX_B39_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_18"
},
"PSS0.PSS_IMUX_B39_19->PSS0_IMUX_B39_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B39_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B39_19"
},
"PSS0.PSS_IMUX_B40_0->PSS0_IMUX_B40_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_0"
},
"PSS0.PSS_IMUX_B40_1->PSS0_IMUX_B40_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_1"
},
"PSS0.PSS_IMUX_B40_2->PSS0_IMUX_B40_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_2"
},
"PSS0.PSS_IMUX_B40_3->PSS0_IMUX_B40_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_3"
},
"PSS0.PSS_IMUX_B40_4->PSS0_IMUX_B40_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_4"
},
"PSS0.PSS_IMUX_B40_5->PSS0_IMUX_B40_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_5"
},
"PSS0.PSS_IMUX_B40_6->PSS0_IMUX_B40_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_6"
},
"PSS0.PSS_IMUX_B40_7->PSS0_IMUX_B40_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_7"
},
"PSS0.PSS_IMUX_B40_8->PSS0_IMUX_B40_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_8"
},
"PSS0.PSS_IMUX_B40_9->PSS0_IMUX_B40_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_9"
},
"PSS0.PSS_IMUX_B40_10->PSS0_IMUX_B40_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_10"
},
"PSS0.PSS_IMUX_B40_11->PSS0_IMUX_B40_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_11"
},
"PSS0.PSS_IMUX_B40_12->PSS0_IMUX_B40_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_12"
},
"PSS0.PSS_IMUX_B40_13->PSS0_IMUX_B40_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_13"
},
"PSS0.PSS_IMUX_B40_14->PSS0_IMUX_B40_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_14"
},
"PSS0.PSS_IMUX_B40_15->PSS0_IMUX_B40_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_15"
},
"PSS0.PSS_IMUX_B40_16->PSS0_IMUX_B40_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_16"
},
"PSS0.PSS_IMUX_B40_17->PSS0_IMUX_B40_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_17"
},
"PSS0.PSS_IMUX_B40_18->PSS0_IMUX_B40_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_18"
},
"PSS0.PSS_IMUX_B40_19->PSS0_IMUX_B40_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B40_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B40_19"
},
"PSS0.PSS_IMUX_B41_0->PSS0_IMUX_B41_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_0"
},
"PSS0.PSS_IMUX_B41_1->PSS0_IMUX_B41_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_1"
},
"PSS0.PSS_IMUX_B41_2->PSS0_IMUX_B41_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_2"
},
"PSS0.PSS_IMUX_B41_3->PSS0_IMUX_B41_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_3"
},
"PSS0.PSS_IMUX_B41_4->PSS0_IMUX_B41_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_4"
},
"PSS0.PSS_IMUX_B41_5->PSS0_IMUX_B41_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_5"
},
"PSS0.PSS_IMUX_B41_6->PSS0_IMUX_B41_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_6"
},
"PSS0.PSS_IMUX_B41_7->PSS0_IMUX_B41_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_7"
},
"PSS0.PSS_IMUX_B41_8->PSS0_IMUX_B41_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_8"
},
"PSS0.PSS_IMUX_B41_9->PSS0_IMUX_B41_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_9"
},
"PSS0.PSS_IMUX_B41_10->PSS0_IMUX_B41_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_10"
},
"PSS0.PSS_IMUX_B41_11->PSS0_IMUX_B41_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_11"
},
"PSS0.PSS_IMUX_B41_12->PSS0_IMUX_B41_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_12"
},
"PSS0.PSS_IMUX_B41_13->PSS0_IMUX_B41_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_13"
},
"PSS0.PSS_IMUX_B41_14->PSS0_IMUX_B41_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_14"
},
"PSS0.PSS_IMUX_B41_15->PSS0_IMUX_B41_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_15"
},
"PSS0.PSS_IMUX_B41_16->PSS0_IMUX_B41_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_16"
},
"PSS0.PSS_IMUX_B41_17->PSS0_IMUX_B41_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_17"
},
"PSS0.PSS_IMUX_B41_18->PSS0_IMUX_B41_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_18"
},
"PSS0.PSS_IMUX_B41_19->PSS0_IMUX_B41_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B41_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B41_19"
},
"PSS0.PSS_IMUX_B42_0->PSS0_IMUX_B42_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_0"
},
"PSS0.PSS_IMUX_B42_1->PSS0_IMUX_B42_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_1"
},
"PSS0.PSS_IMUX_B42_2->PSS0_IMUX_B42_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_2"
},
"PSS0.PSS_IMUX_B42_3->PSS0_IMUX_B42_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_3"
},
"PSS0.PSS_IMUX_B42_4->PSS0_IMUX_B42_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_4"
},
"PSS0.PSS_IMUX_B42_5->PSS0_IMUX_B42_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_5"
},
"PSS0.PSS_IMUX_B42_6->PSS0_IMUX_B42_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_6"
},
"PSS0.PSS_IMUX_B42_7->PSS0_IMUX_B42_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_7"
},
"PSS0.PSS_IMUX_B42_8->PSS0_IMUX_B42_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_8"
},
"PSS0.PSS_IMUX_B42_9->PSS0_IMUX_B42_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_9"
},
"PSS0.PSS_IMUX_B42_10->PSS0_IMUX_B42_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_10"
},
"PSS0.PSS_IMUX_B42_11->PSS0_IMUX_B42_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_11"
},
"PSS0.PSS_IMUX_B42_12->PSS0_IMUX_B42_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_12"
},
"PSS0.PSS_IMUX_B42_13->PSS0_IMUX_B42_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_13"
},
"PSS0.PSS_IMUX_B42_14->PSS0_IMUX_B42_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_14"
},
"PSS0.PSS_IMUX_B42_15->PSS0_IMUX_B42_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_15"
},
"PSS0.PSS_IMUX_B42_16->PSS0_IMUX_B42_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_16"
},
"PSS0.PSS_IMUX_B42_17->PSS0_IMUX_B42_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_17"
},
"PSS0.PSS_IMUX_B42_18->PSS0_IMUX_B42_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_18"
},
"PSS0.PSS_IMUX_B42_19->PSS0_IMUX_B42_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B42_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B42_19"
},
"PSS0.PSS_IMUX_B43_0->PSS0_IMUX_B43_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_0"
},
"PSS0.PSS_IMUX_B43_1->PSS0_IMUX_B43_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_1"
},
"PSS0.PSS_IMUX_B43_2->PSS0_IMUX_B43_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_2"
},
"PSS0.PSS_IMUX_B43_3->PSS0_IMUX_B43_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_3"
},
"PSS0.PSS_IMUX_B43_4->PSS0_IMUX_B43_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_4"
},
"PSS0.PSS_IMUX_B43_5->PSS0_IMUX_B43_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_5"
},
"PSS0.PSS_IMUX_B43_6->PSS0_IMUX_B43_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_6"
},
"PSS0.PSS_IMUX_B43_7->PSS0_IMUX_B43_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_7"
},
"PSS0.PSS_IMUX_B43_8->PSS0_IMUX_B43_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_8"
},
"PSS0.PSS_IMUX_B43_9->PSS0_IMUX_B43_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_9"
},
"PSS0.PSS_IMUX_B43_10->PSS0_IMUX_B43_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_10"
},
"PSS0.PSS_IMUX_B43_11->PSS0_IMUX_B43_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_11"
},
"PSS0.PSS_IMUX_B43_12->PSS0_IMUX_B43_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_12"
},
"PSS0.PSS_IMUX_B43_13->PSS0_IMUX_B43_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_13"
},
"PSS0.PSS_IMUX_B43_14->PSS0_IMUX_B43_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_14"
},
"PSS0.PSS_IMUX_B43_15->PSS0_IMUX_B43_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_15"
},
"PSS0.PSS_IMUX_B43_16->PSS0_IMUX_B43_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_16"
},
"PSS0.PSS_IMUX_B43_17->PSS0_IMUX_B43_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_17"
},
"PSS0.PSS_IMUX_B43_18->PSS0_IMUX_B43_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_18"
},
"PSS0.PSS_IMUX_B43_19->PSS0_IMUX_B43_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B43_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B43_19"
},
"PSS0.PSS_IMUX_B44_0->PSS0_IMUX_B44_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_0"
},
"PSS0.PSS_IMUX_B44_1->PSS0_IMUX_B44_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_1"
},
"PSS0.PSS_IMUX_B44_2->PSS0_IMUX_B44_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_2"
},
"PSS0.PSS_IMUX_B44_3->PSS0_IMUX_B44_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_3"
},
"PSS0.PSS_IMUX_B44_4->PSS0_IMUX_B44_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_4"
},
"PSS0.PSS_IMUX_B44_5->PSS0_IMUX_B44_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_5"
},
"PSS0.PSS_IMUX_B44_6->PSS0_IMUX_B44_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_6"
},
"PSS0.PSS_IMUX_B44_7->PSS0_IMUX_B44_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_7"
},
"PSS0.PSS_IMUX_B44_8->PSS0_IMUX_B44_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_8"
},
"PSS0.PSS_IMUX_B44_9->PSS0_IMUX_B44_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_9"
},
"PSS0.PSS_IMUX_B44_10->PSS0_IMUX_B44_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_10"
},
"PSS0.PSS_IMUX_B44_11->PSS0_IMUX_B44_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_11"
},
"PSS0.PSS_IMUX_B44_12->PSS0_IMUX_B44_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_12"
},
"PSS0.PSS_IMUX_B44_13->PSS0_IMUX_B44_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_13"
},
"PSS0.PSS_IMUX_B44_14->PSS0_IMUX_B44_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_14"
},
"PSS0.PSS_IMUX_B44_15->PSS0_IMUX_B44_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_15"
},
"PSS0.PSS_IMUX_B44_16->PSS0_IMUX_B44_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_16"
},
"PSS0.PSS_IMUX_B44_17->PSS0_IMUX_B44_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_17"
},
"PSS0.PSS_IMUX_B44_18->PSS0_IMUX_B44_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_18"
},
"PSS0.PSS_IMUX_B44_19->PSS0_IMUX_B44_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B44_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B44_19"
},
"PSS0.PSS_IMUX_B45_0->PSS0_IMUX_B45_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_0"
},
"PSS0.PSS_IMUX_B45_1->PSS0_IMUX_B45_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_1"
},
"PSS0.PSS_IMUX_B45_2->PSS0_IMUX_B45_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_2"
},
"PSS0.PSS_IMUX_B45_3->PSS0_IMUX_B45_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_3"
},
"PSS0.PSS_IMUX_B45_4->PSS0_IMUX_B45_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_4"
},
"PSS0.PSS_IMUX_B45_5->PSS0_IMUX_B45_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_5"
},
"PSS0.PSS_IMUX_B45_6->PSS0_IMUX_B45_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_6"
},
"PSS0.PSS_IMUX_B45_7->PSS0_IMUX_B45_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_7"
},
"PSS0.PSS_IMUX_B45_8->PSS0_IMUX_B45_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_8"
},
"PSS0.PSS_IMUX_B45_9->PSS0_IMUX_B45_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_9"
},
"PSS0.PSS_IMUX_B45_10->PSS0_IMUX_B45_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_10"
},
"PSS0.PSS_IMUX_B45_11->PSS0_IMUX_B45_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_11"
},
"PSS0.PSS_IMUX_B45_12->PSS0_IMUX_B45_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_12"
},
"PSS0.PSS_IMUX_B45_13->PSS0_IMUX_B45_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_13"
},
"PSS0.PSS_IMUX_B45_14->PSS0_IMUX_B45_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_14"
},
"PSS0.PSS_IMUX_B45_15->PSS0_IMUX_B45_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_15"
},
"PSS0.PSS_IMUX_B45_16->PSS0_IMUX_B45_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_16"
},
"PSS0.PSS_IMUX_B45_17->PSS0_IMUX_B45_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_17"
},
"PSS0.PSS_IMUX_B45_18->PSS0_IMUX_B45_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_18"
},
"PSS0.PSS_IMUX_B45_19->PSS0_IMUX_B45_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B45_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B45_19"
},
"PSS0.PSS_IMUX_B46_0->PSS0_IMUX_B46_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_0"
},
"PSS0.PSS_IMUX_B46_1->PSS0_IMUX_B46_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_1"
},
"PSS0.PSS_IMUX_B46_2->PSS0_IMUX_B46_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_2"
},
"PSS0.PSS_IMUX_B46_3->PSS0_IMUX_B46_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_3"
},
"PSS0.PSS_IMUX_B46_4->PSS0_IMUX_B46_4": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_4"
},
"PSS0.PSS_IMUX_B46_5->PSS0_IMUX_B46_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_5"
},
"PSS0.PSS_IMUX_B46_6->PSS0_IMUX_B46_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_6"
},
"PSS0.PSS_IMUX_B46_7->PSS0_IMUX_B46_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_7"
},
"PSS0.PSS_IMUX_B46_8->PSS0_IMUX_B46_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_8"
},
"PSS0.PSS_IMUX_B46_9->PSS0_IMUX_B46_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_9"
},
"PSS0.PSS_IMUX_B46_10->PSS0_IMUX_B46_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_10"
},
"PSS0.PSS_IMUX_B46_11->PSS0_IMUX_B46_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_11"
},
"PSS0.PSS_IMUX_B46_12->PSS0_IMUX_B46_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_12"
},
"PSS0.PSS_IMUX_B46_13->PSS0_IMUX_B46_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_13"
},
"PSS0.PSS_IMUX_B46_14->PSS0_IMUX_B46_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_14"
},
"PSS0.PSS_IMUX_B46_15->PSS0_IMUX_B46_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_15"
},
"PSS0.PSS_IMUX_B46_16->PSS0_IMUX_B46_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_16"
},
"PSS0.PSS_IMUX_B46_17->PSS0_IMUX_B46_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_17",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_17"
},
"PSS0.PSS_IMUX_B46_18->PSS0_IMUX_B46_18": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_18",
"is_directional": "1",
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"is_pseudo": "0",
"src_to_dst": {
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"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_18"
},
"PSS0.PSS_IMUX_B46_19->PSS0_IMUX_B46_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B46_19",
"is_directional": "1",
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"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B46_19"
},
"PSS0.PSS_IMUX_B47_0->PSS0_IMUX_B47_0": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_0",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_0"
},
"PSS0.PSS_IMUX_B47_1->PSS0_IMUX_B47_1": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_1",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_1"
},
"PSS0.PSS_IMUX_B47_2->PSS0_IMUX_B47_2": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_2",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_2"
},
"PSS0.PSS_IMUX_B47_3->PSS0_IMUX_B47_3": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_3",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_3"
},
"PSS0.PSS_IMUX_B47_4->PSS0_IMUX_B47_4": {
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"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_4",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_4"
},
"PSS0.PSS_IMUX_B47_5->PSS0_IMUX_B47_5": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_5",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_5"
},
"PSS0.PSS_IMUX_B47_6->PSS0_IMUX_B47_6": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_6",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_6"
},
"PSS0.PSS_IMUX_B47_7->PSS0_IMUX_B47_7": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_7",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_7"
},
"PSS0.PSS_IMUX_B47_8->PSS0_IMUX_B47_8": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_8",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_8"
},
"PSS0.PSS_IMUX_B47_9->PSS0_IMUX_B47_9": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_9",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_9"
},
"PSS0.PSS_IMUX_B47_10->PSS0_IMUX_B47_10": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_10",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_10"
},
"PSS0.PSS_IMUX_B47_11->PSS0_IMUX_B47_11": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_11",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_11"
},
"PSS0.PSS_IMUX_B47_12->PSS0_IMUX_B47_12": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_12",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_12"
},
"PSS0.PSS_IMUX_B47_13->PSS0_IMUX_B47_13": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_13",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_13"
},
"PSS0.PSS_IMUX_B47_14->PSS0_IMUX_B47_14": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_14",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_14"
},
"PSS0.PSS_IMUX_B47_15->PSS0_IMUX_B47_15": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_15",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_15"
},
"PSS0.PSS_IMUX_B47_16->PSS0_IMUX_B47_16": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_16",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_16"
},
"PSS0.PSS_IMUX_B47_17->PSS0_IMUX_B47_17": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_17",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_17"
},
"PSS0.PSS_IMUX_B47_18->PSS0_IMUX_B47_18": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_18",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_18"
},
"PSS0.PSS_IMUX_B47_19->PSS0_IMUX_B47_19": {
"can_invert": "0",
"dst_to_src": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"dst_wire": "PSS0_IMUX_B47_19",
"is_directional": "1",
"is_pass_transistor": 1,
"is_pseudo": "0",
"src_to_dst": {
"delay": null,
"in_cap": null,
"res": "0.000"
},
"src_wire": "PSS_IMUX_B47_19"
}
},
"sites": [],
"tile_type": "PSS0",
"wires": {
"PSS0_CLK_B0_0": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_1": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_2": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_3": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_4": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_5": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_6": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_7": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_8": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_9": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_10": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_11": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_12": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_13": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_14": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_15": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_16": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_17": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_18": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B0_19": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_0": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_1": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_2": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_3": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_4": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_5": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_6": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_7": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_8": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_9": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_10": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_11": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_12": {
"cap": "10.823",
"res": "0.000"
},
"PSS0_CLK_B1_13": {
"cap": "10.823",
"res": "0.000"
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