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foss-fpga-tools/prjxray-db/ccead5dd107210a9c543edae5c129d350a0e2dd4^!/.
commit
ccead5dd107210a9c543edae5c129d350a0e2dd4
[log]
author
Tim 'mithro' Ansell <me@mith.ro>
Sun Sep 30 14:19:02 2018 +0000
committer
SymbiYosys Travis Bot <nobody@nowhere.com>
Sun Sep 30 14:19:02 2018 +0000
tree
4f1fce752e55cee6bcce09c4aec5797f1c8b1aeb
parent
3c2e768cebe020fdf12f8cfe6c0fa0aa49a3a3bd [diff]
Travis build #274 of v0.0-116-gfcb76b4

From https://github.com/SymbiFlow/prjxray-db/tree/fcb76b4ac952140a907fca67dc1103a29dfbc2d2

diff --git a/artix7/seg_clbll_l.html b/artix7/seg_clbll_l.html
index ebd6a17..987c772 100644
--- a/artix7/seg_clbll_l.html
+++ b/artix7/seg_clbll_l.html

@@ -24098,118 +24098,6 @@
 <tr bgcolor="#dddddd"><!-- 1-----1-- --><td>INT_L.WW4BEG3.NE6END3</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 1----1--- --><td>INT_L.WW4BEG3.NN6END3</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 </table>
-<h3>Tile INT_L Pseudo PIPs</h3>
-<table cellspacing=0>
-<tr><th width="500" align="left">PIP</th><th>Type</th></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT0.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.FAN_ALT1.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT2.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.FAN_ALT3.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT4.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.FAN_ALT5.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT6.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.FAN_ALT7.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT0.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.BYP_ALT1.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT2.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.BYP_ALT3.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT4.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.BYP_ALT5.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT6.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.BYP_ALT7.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L0.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L1.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L2.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L3.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L4.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L5.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L6.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L7.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L8.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L9.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L10.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L11.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L12.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L13.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L14.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L15.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L16.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L17.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L18.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L19.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L20.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L21.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L22.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L23.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L24.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L25.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L26.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L27.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L28.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L29.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L30.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L31.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L32.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L33.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L34.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L35.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L36.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L37.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L38.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L39.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L40.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L41.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L42.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L43.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L44.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L45.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.IMUX_L46.VCC_WIRE</td><td>default</td></tr>
-<tr><td>INT_L.IMUX_L47.VCC_WIRE</td><td>default</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE0.BYP_ALT0</td><td>always</td></tr>
-<tr><td>INT_L.BYP_BOUNCE1.BYP_ALT1</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE2.BYP_ALT2</td><td>always</td></tr>
-<tr><td>INT_L.BYP_BOUNCE3.BYP_ALT3</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE4.BYP_ALT4</td><td>always</td></tr>
-<tr><td>INT_L.BYP_BOUNCE5.BYP_ALT5</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE6.BYP_ALT6</td><td>always</td></tr>
-<tr><td>INT_L.BYP_BOUNCE7.BYP_ALT7</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_L0.BYP_ALT0</td><td>always</td></tr>
-<tr><td>INT_L.BYP_L1.BYP_ALT1</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_L2.BYP_ALT2</td><td>always</td></tr>
-<tr><td>INT_L.BYP_L3.BYP_ALT3</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_L4.BYP_ALT4</td><td>always</td></tr>
-<tr><td>INT_L.BYP_L5.BYP_ALT5</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.BYP_L6.BYP_ALT6</td><td>always</td></tr>
-<tr><td>INT_L.BYP_L7.BYP_ALT7</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE0.FAN_ALT0</td><td>always</td></tr>
-<tr><td>INT_L.FAN_BOUNCE1.FAN_ALT1</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE2.FAN_ALT2</td><td>always</td></tr>
-<tr><td>INT_L.FAN_BOUNCE3.FAN_ALT3</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE4.FAN_ALT4</td><td>always</td></tr>
-<tr><td>INT_L.FAN_BOUNCE5.FAN_ALT5</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE6.FAN_ALT6</td><td>always</td></tr>
-<tr><td>INT_L.FAN_BOUNCE7.FAN_ALT7</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_L0.FAN_ALT0</td><td>always</td></tr>
-<tr><td>INT_L.FAN_L1.FAN_ALT1</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_L2.FAN_ALT2</td><td>always</td></tr>
-<tr><td>INT_L.FAN_L3.FAN_ALT3</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_L4.FAN_ALT4</td><td>always</td></tr>
-<tr><td>INT_L.FAN_L5.FAN_ALT5</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.FAN_L6.FAN_ALT6</td><td>always</td></tr>
-<tr><td>INT_L.FAN_L7.FAN_ALT7</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B10_WEST.GCLK_L_B10</td><td>always</td></tr>
-<tr><td>INT_L.GCLK_L_B10_EAST.GCLK_L_B10</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B11_WEST.GCLK_L_B11</td><td>always</td></tr>
-<tr><td>INT_L.GCLK_L_B11_EAST.GCLK_L_B11</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B6_WEST.GCLK_L_B6</td><td>always</td></tr>
-<tr><td>INT_L.GCLK_L_B6_EAST.GCLK_L_B6</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B7_WEST.GCLK_L_B7</td><td>always</td></tr>
-<tr><td>INT_L.GCLK_L_B7_EAST.GCLK_L_B7</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B8_WEST.GCLK_L_B8</td><td>always</td></tr>
-<tr><td>INT_L.GCLK_L_B8_EAST.GCLK_L_B8</td><td>always</td></tr>
-<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B9_WEST.GCLK_L_B9</td><td>always</td></tr>
-<tr><td>INT_L.GCLK_L_B9_EAST.GCLK_L_B9</td><td>always</td></tr>
-</table>
 <h3>Tile CLBLL_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
@@ -24360,5 +24248,117 @@
 <tr bgcolor="#dddddd"><td>CLBLL_L.CLBLL_LOGIC_OUTS19.CLBLL_L_DMUX</td><td>always</td></tr>
 <tr><td>CLBLL_L.CLBLL_LOGIC_OUTS3.CLBLL_L_DQ</td><td>always</td></tr>
 </table>
+<h3>Tile INT_L Pseudo PIPs</h3>
+<table cellspacing=0>
+<tr><th width="500" align="left">PIP</th><th>Type</th></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT0.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.FAN_ALT1.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT2.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.FAN_ALT3.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT4.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.FAN_ALT5.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_ALT6.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.FAN_ALT7.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT0.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.BYP_ALT1.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT2.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.BYP_ALT3.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT4.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.BYP_ALT5.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_ALT6.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.BYP_ALT7.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L0.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L1.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L2.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L3.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L4.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L5.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L6.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L7.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L8.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L9.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L10.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L11.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L12.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L13.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L14.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L15.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L16.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L17.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L18.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L19.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L20.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L21.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L22.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L23.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L24.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L25.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L26.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L27.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L28.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L29.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L30.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L31.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L32.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L33.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L34.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L35.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L36.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L37.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L38.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L39.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L40.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L41.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L42.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L43.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L44.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L45.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.IMUX_L46.VCC_WIRE</td><td>default</td></tr>
+<tr><td>INT_L.IMUX_L47.VCC_WIRE</td><td>default</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE0.BYP_ALT0</td><td>always</td></tr>
+<tr><td>INT_L.BYP_BOUNCE1.BYP_ALT1</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE2.BYP_ALT2</td><td>always</td></tr>
+<tr><td>INT_L.BYP_BOUNCE3.BYP_ALT3</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE4.BYP_ALT4</td><td>always</td></tr>
+<tr><td>INT_L.BYP_BOUNCE5.BYP_ALT5</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_BOUNCE6.BYP_ALT6</td><td>always</td></tr>
+<tr><td>INT_L.BYP_BOUNCE7.BYP_ALT7</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_L0.BYP_ALT0</td><td>always</td></tr>
+<tr><td>INT_L.BYP_L1.BYP_ALT1</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_L2.BYP_ALT2</td><td>always</td></tr>
+<tr><td>INT_L.BYP_L3.BYP_ALT3</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_L4.BYP_ALT4</td><td>always</td></tr>
+<tr><td>INT_L.BYP_L5.BYP_ALT5</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.BYP_L6.BYP_ALT6</td><td>always</td></tr>
+<tr><td>INT_L.BYP_L7.BYP_ALT7</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE0.FAN_ALT0</td><td>always</td></tr>
+<tr><td>INT_L.FAN_BOUNCE1.FAN_ALT1</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE2.FAN_ALT2</td><td>always</td></tr>
+<tr><td>INT_L.FAN_BOUNCE3.FAN_ALT3</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE4.FAN_ALT4</td><td>always</td></tr>
+<tr><td>INT_L.FAN_BOUNCE5.FAN_ALT5</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_BOUNCE6.FAN_ALT6</td><td>always</td></tr>
+<tr><td>INT_L.FAN_BOUNCE7.FAN_ALT7</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_L0.FAN_ALT0</td><td>always</td></tr>
+<tr><td>INT_L.FAN_L1.FAN_ALT1</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_L2.FAN_ALT2</td><td>always</td></tr>
+<tr><td>INT_L.FAN_L3.FAN_ALT3</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_L4.FAN_ALT4</td><td>always</td></tr>
+<tr><td>INT_L.FAN_L5.FAN_ALT5</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.FAN_L6.FAN_ALT6</td><td>always</td></tr>
+<tr><td>INT_L.FAN_L7.FAN_ALT7</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B10_WEST.GCLK_L_B10</td><td>always</td></tr>
+<tr><td>INT_L.GCLK_L_B10_EAST.GCLK_L_B10</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B11_WEST.GCLK_L_B11</td><td>always</td></tr>
+<tr><td>INT_L.GCLK_L_B11_EAST.GCLK_L_B11</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B6_WEST.GCLK_L_B6</td><td>always</td></tr>
+<tr><td>INT_L.GCLK_L_B6_EAST.GCLK_L_B6</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B7_WEST.GCLK_L_B7</td><td>always</td></tr>
+<tr><td>INT_L.GCLK_L_B7_EAST.GCLK_L_B7</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B8_WEST.GCLK_L_B8</td><td>always</td></tr>
+<tr><td>INT_L.GCLK_L_B8_EAST.GCLK_L_B8</td><td>always</td></tr>
+<tr bgcolor="#dddddd"><td>INT_L.GCLK_L_B9_WEST.GCLK_L_B9</td><td>always</td></tr>
+<tr><td>INT_L.GCLK_L_B9_EAST.GCLK_L_B9</td><td>always</td></tr>
+</table>
 </div>
 </body></html>

diff --git a/kintex7/seg_bram1_l.html b/kintex7/seg_bram1_l.html
index 8dd098d..f0fc704 100644
--- a/kintex7/seg_bram1_l.html
+++ b/kintex7/seg_bram1_l.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
+<h3>Tile INT_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_L Pseudo PIPs</h3>
+<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_bram2_l.html b/kintex7/seg_bram2_l.html
index 4d422ca..ae7239e 100644
--- a/kintex7/seg_bram2_l.html
+++ b/kintex7/seg_bram2_l.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
+<h3>Tile INT_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_L Pseudo PIPs</h3>
+<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_bram3_l.html b/kintex7/seg_bram3_l.html
index e248200..b9dbf90 100644
--- a/kintex7/seg_bram3_l.html
+++ b/kintex7/seg_bram3_l.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
+<h3>Tile INT_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_L Pseudo PIPs</h3>
+<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_bram4_l.html b/kintex7/seg_bram4_l.html
index 9ff5f66..769bb02 100644
--- a/kintex7/seg_bram4_l.html
+++ b/kintex7/seg_bram4_l.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_L.WW4BEG3.LOGIC_OUTS_L21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
+<h3>Tile INT_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_L Pseudo PIPs</h3>
+<h3>Tile BRAM_INT_INTERFACE_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_clbll_l.html b/kintex7/seg_clbll_l.html
index 9c5a2cb..7af4a9e 100644
--- a/kintex7/seg_clbll_l.html
+++ b/kintex7/seg_clbll_l.html

@@ -22868,11 +22868,11 @@
 <tr bgcolor="#dddddd"><!-- 1-----1-- --><td>INT_L.WW4BEG3.NE6END3</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 1----1--- --><td>INT_L.WW4BEG3.NN6END3</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 </table>
-<h3>Tile CLBLL_L Pseudo PIPs</h3>
+<h3>Tile INT_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_L Pseudo PIPs</h3>
+<h3>Tile CLBLL_L Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_clblm_r.html b/kintex7/seg_clblm_r.html
index 6e52043..dae8e14 100644
--- a/kintex7/seg_clblm_r.html
+++ b/kintex7/seg_clblm_r.html

@@ -22868,11 +22868,11 @@
 <tr bgcolor="#dddddd"><!-- 1-----1-- --><td>INT_R.WW4BEG3.NE6END3</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 1----1--- --><td>INT_R.WW4BEG3.NN6END3</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 </table>
-<h3>Tile CLBLM_R Pseudo PIPs</h3>
+<h3>Tile INT_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_R Pseudo PIPs</h3>
+<h3>Tile CLBLM_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_dsp0_r.html b/kintex7/seg_dsp0_r.html
index b1c86b2..98d4f78 100644
--- a/kintex7/seg_dsp0_r.html
+++ b/kintex7/seg_dsp0_r.html

@@ -20530,7 +20530,7 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_R.WW4BEG3.LOGIC_OUTS15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_R.WW4BEG3.LOGIC_OUTS21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile DSP_R Pseudo PIPs</h3>
+<h3>Tile INT_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
@@ -20538,7 +20538,7 @@
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_R Pseudo PIPs</h3>
+<h3>Tile DSP_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_dsp1_r.html b/kintex7/seg_dsp1_r.html
index fe4211b..eee07ab 100644
--- a/kintex7/seg_dsp1_r.html
+++ b/kintex7/seg_dsp1_r.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_R.WW4BEG3.LOGIC_OUTS15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_R.WW4BEG3.LOGIC_OUTS21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
+<h3>Tile INT_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_R Pseudo PIPs</h3>
+<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_dsp2_r.html b/kintex7/seg_dsp2_r.html
index f97970c..72aaa8e 100644
--- a/kintex7/seg_dsp2_r.html
+++ b/kintex7/seg_dsp2_r.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_R.WW4BEG3.LOGIC_OUTS15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_R.WW4BEG3.LOGIC_OUTS21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
+<h3>Tile INT_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_R Pseudo PIPs</h3>
+<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_dsp3_r.html b/kintex7/seg_dsp3_r.html
index ee6be61..ad55e4d 100644
--- a/kintex7/seg_dsp3_r.html
+++ b/kintex7/seg_dsp3_r.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_R.WW4BEG3.LOGIC_OUTS15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_R.WW4BEG3.LOGIC_OUTS21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
+<h3>Tile INT_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_R Pseudo PIPs</h3>
+<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>

diff --git a/kintex7/seg_dsp4_r.html b/kintex7/seg_dsp4_r.html
index 66a9ea8..265fa69 100644
--- a/kintex7/seg_dsp4_r.html
+++ b/kintex7/seg_dsp4_r.html

@@ -20530,11 +20530,11 @@
 <tr bgcolor="#dddddd"><!-- 1------1- --><td>INT_R.WW4BEG3.LOGIC_OUTS15</td><td align="center">-</td><td align="center">1</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td></tr>
 <tr><!-- 11------- --><td>INT_R.WW4BEG3.LOGIC_OUTS21</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">-</td><td align="center">1</td><td align="center">1</td></tr>
 </table>
-<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
+<h3>Tile INT_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>
-<h3>Tile INT_R Pseudo PIPs</h3>
+<h3>Tile INT_INTERFACE_R Pseudo PIPs</h3>
 <table cellspacing=0>
 <tr><th width="500" align="left">PIP</th><th>Type</th></tr>
 </table>