| { |
| "pips": { |
| "LIOI3.IOI_BYP3_0->IOI_IMUX_RC0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IMUX_RC0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP3_0" |
| }, |
| "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR0_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CLR0_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP3_0" |
| }, |
| "LIOI3.IOI_BYP3_0->IOI_RCLK_DIV_CLR3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CLR3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP3_0" |
| }, |
| "LIOI3.IOI_BYP3_1->IOI_IMUX_RC3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IMUX_RC3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP3_1" |
| }, |
| "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CE0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP3_1" |
| }, |
| "LIOI3.IOI_BYP3_1->IOI_RCLK_DIV_CE3_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CE3_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP3_1" |
| }, |
| "LIOI3.IOI_BYP4_0->IOI_IMUX_RC1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IMUX_RC1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP4_0" |
| }, |
| "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR1_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CLR1_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP4_0" |
| }, |
| "LIOI3.IOI_BYP4_0->IOI_RCLK_DIV_CLR2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CLR2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP4_0" |
| }, |
| "LIOI3.IOI_BYP4_1->IOI_IMUX_RC2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IMUX_RC2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP4_1" |
| }, |
| "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CE1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP4_1" |
| }, |
| "LIOI3.IOI_BYP4_1->IOI_RCLK_DIV_CE2_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_RCLK_DIV_CE2_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP4_1" |
| }, |
| "LIOI3.IOI_BYP6_0->IOI_IDELAY1_CINVCTRL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_CINVCTRL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP6_0" |
| }, |
| "LIOI3.IOI_BYP6_1->IOI_IDELAY0_CINVCTRL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_CINVCTRL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP6_1" |
| }, |
| "LIOI3.IOI_BYP7_0->LIOI3_IDELAY1_IFDLY2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI3_IDELAY1_IFDLY2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP7_0" |
| }, |
| "LIOI3.IOI_BYP7_1->LIOI3_IDELAY0_IFDLY2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI3_IDELAY0_IFDLY2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_BYP7_1" |
| }, |
| "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CLK0_0" |
| }, |
| "LIOI3.IOI_CLK0_0->IOI_ILOGIC1_CLKDIVP": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKDIVP", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CLK0_0" |
| }, |
| "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CLK0_1" |
| }, |
| "LIOI3.IOI_CLK0_1->IOI_ILOGIC0_CLKDIVP": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKDIVP", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CLK0_1" |
| }, |
| "LIOI3.IOI_CLK1_0->IOI_IDELAY1_C": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_C", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CLK1_0" |
| }, |
| "LIOI3.IOI_CLK1_1->IOI_IDELAY0_C": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_C", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CLK1_1" |
| }, |
| "LIOI3.IOI_CTRL0_0->IOI_OLOGIC1_SR": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_SR", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CTRL0_0" |
| }, |
| "LIOI3.IOI_CTRL0_1->IOI_OLOGIC0_SR": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_SR", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CTRL0_1" |
| }, |
| "LIOI3.IOI_CTRL1_0->IOI_ILOGIC1_SR": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_SR", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CTRL1_0" |
| }, |
| "LIOI3.IOI_CTRL1_1->IOI_ILOGIC0_SR": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_SR", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_CTRL1_1" |
| }, |
| "LIOI3.IOI_FAN4_0->LIOI3_IDELAY1_IFDLY0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI3_IDELAY1_IFDLY0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_FAN4_0" |
| }, |
| "LIOI3.IOI_FAN4_1->LIOI3_IDELAY0_IFDLY0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI3_IDELAY0_IFDLY0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_FAN4_1" |
| }, |
| "LIOI3.IOI_FAN5_0->LIOI3_IDELAY1_IFDLY1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI3_IDELAY1_IFDLY1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_FAN5_0" |
| }, |
| "LIOI3.IOI_FAN5_1->LIOI3_IDELAY0_IFDLY1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI3_IDELAY0_IFDLY1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_FAN5_1" |
| }, |
| "LIOI3.IOI_IDELAY0_CNTVALUEOUT0->IOI_LOGIC_OUTS20_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS20_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY0_CNTVALUEOUT0" |
| }, |
| "LIOI3.IOI_IDELAY0_CNTVALUEOUT1->IOI_LOGIC_OUTS1_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS1_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY0_CNTVALUEOUT1" |
| }, |
| "LIOI3.IOI_IDELAY0_CNTVALUEOUT2->IOI_LOGIC_OUTS19_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS19_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY0_CNTVALUEOUT2" |
| }, |
| "LIOI3.IOI_IDELAY0_CNTVALUEOUT3->IOI_LOGIC_OUTS15_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS15_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY0_CNTVALUEOUT3" |
| }, |
| "LIOI3.IOI_IDELAY0_CNTVALUEOUT4->IOI_LOGIC_OUTS11_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS11_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY0_CNTVALUEOUT4" |
| }, |
| "LIOI3.IOI_IDELAY1_CNTVALUEOUT0->IOI_LOGIC_OUTS20_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS20_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY1_CNTVALUEOUT0" |
| }, |
| "LIOI3.IOI_IDELAY1_CNTVALUEOUT1->IOI_LOGIC_OUTS1_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS1_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY1_CNTVALUEOUT1" |
| }, |
| "LIOI3.IOI_IDELAY1_CNTVALUEOUT2->IOI_LOGIC_OUTS19_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS19_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY1_CNTVALUEOUT2" |
| }, |
| "LIOI3.IOI_IDELAY1_CNTVALUEOUT3->IOI_LOGIC_OUTS15_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS15_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY1_CNTVALUEOUT3" |
| }, |
| "LIOI3.IOI_IDELAY1_CNTVALUEOUT4->IOI_LOGIC_OUTS11_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS11_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAY1_CNTVALUEOUT4" |
| }, |
| "LIOI3.IOI_IDELAYCTRL_DNPULSEOUT->IOI_LOGIC_OUTS13_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS13_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAYCTRL_DNPULSEOUT" |
| }, |
| "LIOI3.IOI_IDELAYCTRL_OUTN1->IOI_LOGIC_OUTS13_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS13_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAYCTRL_OUTN1" |
| }, |
| "LIOI3.IOI_IDELAYCTRL_OUTN65->IOI_LOGIC_OUTS16_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS16_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAYCTRL_OUTN65" |
| }, |
| "LIOI3.IOI_IDELAYCTRL_RDY->IOI_LOGIC_OUTS22_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS22_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAYCTRL_RDY" |
| }, |
| "LIOI3.IOI_IDELAYCTRL_UPPULSEOUT->IOI_LOGIC_OUTS16_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS16_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IDELAYCTRL_UPPULSEOUT" |
| }, |
| "LIOI3.IOI_ILOGIC0_O->>IOI_LOGIC_OUTS18_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.004", |
| "0.015", |
| "0.027", |
| "0.030" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS18_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.004", |
| "0.015", |
| "0.027", |
| "0.030" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_ILOGIC0_O" |
| }, |
| "LIOI3.IOI_ILOGIC0_O->LIOI_I2GCLK_TOP0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_I2GCLK_TOP0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_O" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q1->IOI_LOGIC_OUTS0_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS0_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q1" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q2->IOI_LOGIC_OUTS23_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS23_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q2" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q3->IOI_LOGIC_OUTS9_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS9_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q3" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q4->IOI_LOGIC_OUTS10_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS10_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q4" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q5->IOI_LOGIC_OUTS14_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS14_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q5" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q6->IOI_LOGIC_OUTS3_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS3_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q6" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q7->IOI_LOGIC_OUTS7_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS7_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q7" |
| }, |
| "LIOI3.IOI_ILOGIC0_Q8->IOI_LOGIC_OUTS8_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS8_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC0_Q8" |
| }, |
| "LIOI3.IOI_ILOGIC1_O->>IOI_LOGIC_OUTS18_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.004", |
| "0.015", |
| "0.027", |
| "0.030" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS18_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.004", |
| "0.015", |
| "0.027", |
| "0.030" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_ILOGIC1_O" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q1->IOI_LOGIC_OUTS0_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS0_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q1" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q2->IOI_LOGIC_OUTS23_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS23_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q2" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q3->IOI_LOGIC_OUTS9_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS9_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q3" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q4->IOI_LOGIC_OUTS10_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS10_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q4" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q5->IOI_LOGIC_OUTS14_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS14_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q5" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q6->IOI_LOGIC_OUTS3_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS3_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q6" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q7->IOI_LOGIC_OUTS7_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS7_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q7" |
| }, |
| "LIOI3.IOI_ILOGIC1_Q8->IOI_LOGIC_OUTS8_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS8_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_ILOGIC1_Q8" |
| }, |
| "LIOI3.IOI_IMUX0_0->IOI_ILOGIC1_BITSLIP": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_BITSLIP", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX0_0" |
| }, |
| "LIOI3.IOI_IMUX0_1->IOI_ILOGIC0_BITSLIP": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_BITSLIP", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX0_1" |
| }, |
| "LIOI3.IOI_IMUX10_0->IOI_ILOGIC1_DYNCLKDIVPSEL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_DYNCLKDIVPSEL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX10_0" |
| }, |
| "LIOI3.IOI_IMUX10_1->IOI_ILOGIC0_DYNCLKDIVPSEL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_DYNCLKDIVPSEL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX10_1" |
| }, |
| "LIOI3.IOI_IMUX12_0->IOI_IDELAY1_REGRST": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_REGRST", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX12_0" |
| }, |
| "LIOI3.IOI_IMUX12_1->IOI_IDELAY0_REGRST": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_REGRST", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX12_1" |
| }, |
| "LIOI3.IOI_IMUX13_0->IOI_OLOGIC1_T3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_T3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX13_0" |
| }, |
| "LIOI3.IOI_IMUX13_1->IOI_OLOGIC0_T3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_T3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX13_1" |
| }, |
| "LIOI3.IOI_IMUX14_0->IOI_ILOGIC1_CE2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CE2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX14_0" |
| }, |
| "LIOI3.IOI_IMUX14_1->IOI_ILOGIC0_CE2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CE2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX14_1" |
| }, |
| "LIOI3.IOI_IMUX15_0->IOI_OLOGIC1_T1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_T1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX15_0" |
| }, |
| "LIOI3.IOI_IMUX15_1->IOI_OLOGIC0_T1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_T1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX15_1" |
| }, |
| "LIOI3.IOI_IMUX1_0->IOI_OLOGIC1_TCE": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_TCE", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX1_0" |
| }, |
| "LIOI3.IOI_IMUX1_1->IOI_OLOGIC0_TCE": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_TCE", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX1_1" |
| }, |
| "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX20_0" |
| }, |
| "LIOI3.IOI_IMUX20_0->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX20_0" |
| }, |
| "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX20_1" |
| }, |
| "LIOI3.IOI_IMUX20_1->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX20_1" |
| }, |
| "LIOI3.IOI_IMUX21_0->IOI_OLOGIC1_T4": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_T4", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX21_0" |
| }, |
| "LIOI3.IOI_IMUX21_1->IOI_OLOGIC0_T4": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_T4", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX21_1" |
| }, |
| "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX22_0" |
| }, |
| "LIOI3.IOI_IMUX22_0->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX22_0" |
| }, |
| "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX22_1" |
| }, |
| "LIOI3.IOI_IMUX22_1->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX22_1" |
| }, |
| "LIOI3.IOI_IMUX24_0->IOI_IDELAYCTRL_RST": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAYCTRL_RST", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX24_0" |
| }, |
| "LIOI3.IOI_IMUX25_0->IOI_IDELAY1_DATAIN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_DATAIN", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX25_0" |
| }, |
| "LIOI3.IOI_IMUX25_1->IOI_IDELAY0_DATAIN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_DATAIN", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX25_1" |
| }, |
| "LIOI3.IOI_IMUX26_0->IOI_IDELAY1_INC": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_INC", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX26_0" |
| }, |
| "LIOI3.IOI_IMUX26_1->IOI_IDELAY0_INC": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_INC", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX26_1" |
| }, |
| "LIOI3.IOI_IMUX29_0->IOI_OLOGIC1_OCE": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_OCE", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX29_0" |
| }, |
| "LIOI3.IOI_IMUX29_1->IOI_OLOGIC0_OCE": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_OCE", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX29_1" |
| }, |
| "LIOI3.IOI_IMUX30_0->IOI_IDELAY1_LD": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_LD", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX30_0" |
| }, |
| "LIOI3.IOI_IMUX30_1->IOI_IDELAY0_LD": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_LD", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX30_1" |
| }, |
| "LIOI3.IOI_IMUX31_0->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX31_0" |
| }, |
| "LIOI3.IOI_IMUX31_0->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX31_0" |
| }, |
| "LIOI3.IOI_IMUX31_1->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX31_1" |
| }, |
| "LIOI3.IOI_IMUX31_1->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX31_1" |
| }, |
| "LIOI3.IOI_IMUX32_0->IOI_IDELAY1_CE": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_CE", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX32_0" |
| }, |
| "LIOI3.IOI_IMUX32_1->IOI_IDELAY0_CE": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_CE", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX32_1" |
| }, |
| "LIOI3.IOI_IMUX33_0->IOI_IDELAY1_LDPIPEEN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_LDPIPEEN", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX33_0" |
| }, |
| "LIOI3.IOI_IMUX33_1->IOI_IDELAY0_LDPIPEEN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_LDPIPEEN", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX33_1" |
| }, |
| "LIOI3.IOI_IMUX34_0->IOI_OLOGIC1_D1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX34_0" |
| }, |
| "LIOI3.IOI_IMUX34_1->IOI_OLOGIC0_D1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX34_1" |
| }, |
| "LIOI3.IOI_IMUX35_0->IOI_IDELAY1_CNTVALUEIN2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_CNTVALUEIN2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX35_0" |
| }, |
| "LIOI3.IOI_IMUX35_1->IOI_IDELAY0_CNTVALUEIN2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_CNTVALUEIN2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX35_1" |
| }, |
| "LIOI3.IOI_IMUX36_0->IOI_IDELAY1_CNTVALUEIN1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_CNTVALUEIN1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX36_0" |
| }, |
| "LIOI3.IOI_IMUX36_1->IOI_IDELAY0_CNTVALUEIN1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_CNTVALUEIN1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX36_1" |
| }, |
| "LIOI3.IOI_IMUX37_0->IOI_ILOGIC1_DYNCLKSEL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_DYNCLKSEL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX37_0" |
| }, |
| "LIOI3.IOI_IMUX37_1->IOI_ILOGIC0_DYNCLKSEL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_DYNCLKSEL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX37_1" |
| }, |
| "LIOI3.IOI_IMUX38_0->IOI_IDELAY1_CNTVALUEIN3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_CNTVALUEIN3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX38_0" |
| }, |
| "LIOI3.IOI_IMUX38_1->IOI_IDELAY0_CNTVALUEIN3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_CNTVALUEIN3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX38_1" |
| }, |
| "LIOI3.IOI_IMUX39_0->IOI_IDELAY1_CNTVALUEIN4": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_CNTVALUEIN4", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX39_0" |
| }, |
| "LIOI3.IOI_IMUX39_1->IOI_IDELAY0_CNTVALUEIN4": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_CNTVALUEIN4", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX39_1" |
| }, |
| "LIOI3.IOI_IMUX40_0->IOI_OLOGIC1_D2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX40_0" |
| }, |
| "LIOI3.IOI_IMUX40_1->IOI_OLOGIC0_D2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX40_1" |
| }, |
| "LIOI3.IOI_IMUX41_0->IOI_IDELAY1_CNTVALUEIN0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY1_CNTVALUEIN0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX41_0" |
| }, |
| "LIOI3.IOI_IMUX41_1->IOI_IDELAY0_CNTVALUEIN0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_IDELAY0_CNTVALUEIN0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX41_1" |
| }, |
| "LIOI3.IOI_IMUX42_0->IOI_OLOGIC1_D4": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D4", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX42_0" |
| }, |
| "LIOI3.IOI_IMUX42_1->IOI_OLOGIC0_D4": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D4", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX42_1" |
| }, |
| "LIOI3.IOI_IMUX43_0->IOI_OLOGIC1_D5": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D5", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX43_0" |
| }, |
| "LIOI3.IOI_IMUX43_1->IOI_OLOGIC0_D5": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D5", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX43_1" |
| }, |
| "LIOI3.IOI_IMUX44_0->IOI_OLOGIC1_D3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX44_0" |
| }, |
| "LIOI3.IOI_IMUX44_1->IOI_OLOGIC0_D3": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D3", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX44_1" |
| }, |
| "LIOI3.IOI_IMUX45_0->IOI_OLOGIC1_D6": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D6", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX45_0" |
| }, |
| "LIOI3.IOI_IMUX45_1->IOI_OLOGIC0_D6": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D6", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX45_1" |
| }, |
| "LIOI3.IOI_IMUX46_0->IOI_OLOGIC1_D7": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D7", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX46_0" |
| }, |
| "LIOI3.IOI_IMUX46_1->IOI_OLOGIC0_D7": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D7", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX46_1" |
| }, |
| "LIOI3.IOI_IMUX47_0->IOI_OLOGIC1_D8": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_D8", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX47_0" |
| }, |
| "LIOI3.IOI_IMUX47_1->IOI_OLOGIC0_D8": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_D8", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX47_1" |
| }, |
| "LIOI3.IOI_IMUX4_0->IOI_ILOGIC1_DYNCLKDIVSEL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_DYNCLKDIVSEL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX4_0" |
| }, |
| "LIOI3.IOI_IMUX4_1->IOI_ILOGIC0_DYNCLKDIVSEL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_DYNCLKDIVSEL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX4_1" |
| }, |
| "LIOI3.IOI_IMUX5_0->IOI_ILOGIC1_CE1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CE1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX5_0" |
| }, |
| "LIOI3.IOI_IMUX5_1->IOI_ILOGIC0_CE1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CE1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX5_1" |
| }, |
| "LIOI3.IOI_IMUX6_0->LIOI_DCI_T_TERM1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_DCI_T_TERM1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX6_0" |
| }, |
| "LIOI3.IOI_IMUX6_1->LIOI_DCI_T_TERM0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_DCI_T_TERM0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX6_1" |
| }, |
| "LIOI3.IOI_IMUX7_0->IOI_OLOGIC1_T2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_T2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX7_0" |
| }, |
| "LIOI3.IOI_IMUX7_1->IOI_OLOGIC0_T2": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_T2", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX7_1" |
| }, |
| "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX8_0" |
| }, |
| "LIOI3.IOI_IMUX8_0->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX8_0" |
| }, |
| "LIOI3.IOI_IMUX8_0->IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX8_0" |
| }, |
| "LIOI3.IOI_IMUX8_0->LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX8_0" |
| }, |
| "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX8_1" |
| }, |
| "LIOI3.IOI_IMUX8_1->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.123", |
| "0.142", |
| "0.386", |
| "0.393" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IMUX8_1" |
| }, |
| "LIOI3.IOI_IMUX8_1->IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX8_1" |
| }, |
| "LIOI3.IOI_IMUX8_1->LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX8_1" |
| }, |
| "LIOI3.IOI_IMUX9_0->LIOI_IBUF_DISABLE1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_IBUF_DISABLE1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX9_0" |
| }, |
| "LIOI3.IOI_IMUX9_1->LIOI_IBUF_DISABLE0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_IBUF_DISABLE0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_IMUX9_1" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK0->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK0" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK1->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK1" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK2->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK2" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_IOCLK3->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_IOCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK0->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK0" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK1->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK1" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK2->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK2" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK3->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK3" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK4->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK4" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_LEAF_GCLK5->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_LEAF_GCLK5" |
| }, |
| "LIOI3.IOI_OCLKM_0->IOI_ILOGIC0_OCLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_OCLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLKM_0" |
| }, |
| "LIOI3.IOI_OCLKM_0->IOI_OLOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLKM_0" |
| }, |
| "LIOI3.IOI_OCLKM_1->IOI_ILOGIC1_OCLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_OCLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLKM_1" |
| }, |
| "LIOI3.IOI_OCLKM_1->IOI_OLOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLKM_1" |
| }, |
| "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_OCLK", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_0" |
| }, |
| "LIOI3.IOI_OCLK_0->IOI_ILOGIC0_OCLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC0_OCLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_0" |
| }, |
| "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_0" |
| }, |
| "LIOI3.IOI_OCLK_0->IOI_OLOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_0" |
| }, |
| "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_OCLK", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_1" |
| }, |
| "LIOI3.IOI_OCLK_1->IOI_ILOGIC1_OCLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_ILOGIC1_OCLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_1" |
| }, |
| "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_1" |
| }, |
| "LIOI3.IOI_OCLK_1->IOI_OLOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OCLK_1" |
| }, |
| "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_OFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC0_D1" |
| }, |
| "LIOI3.IOI_OLOGIC0_D1->>LIOI_OLOGIC0_OQ": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_OQ", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC0_D1" |
| }, |
| "LIOI3.IOI_OLOGIC0_IOCLKGLITCH->IOI_LOGIC_OUTS5_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS5_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OLOGIC0_IOCLKGLITCH" |
| }, |
| "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_TFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC0_T1" |
| }, |
| "LIOI3.IOI_OLOGIC0_T1->>LIOI_OLOGIC0_TQ": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_TQ", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC0_T1" |
| }, |
| "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_OFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC1_D1" |
| }, |
| "LIOI3.IOI_OLOGIC1_D1->>LIOI_OLOGIC1_OQ": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_OQ", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.100", |
| "0.331", |
| "0.999", |
| "1.156" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC1_D1" |
| }, |
| "LIOI3.IOI_OLOGIC1_IOCLKGLITCH->IOI_LOGIC_OUTS5_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS5_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "IOI_OLOGIC1_IOCLKGLITCH" |
| }, |
| "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_TFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC1_T1" |
| }, |
| "LIOI3.IOI_OLOGIC1_T1->>LIOI_OLOGIC1_TQ": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_TQ", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.350", |
| "0.403", |
| "0.958", |
| "1.102" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_OLOGIC1_T1" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_ICLK" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_ICLK->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_ICLK" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_ICLKDIV->>IOI_ILOGIC1_CLKDIVP": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKDIVP", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_ICLKDIV" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_ICLKDIV_0->>IOI_ILOGIC0_CLKDIVP": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKDIVP", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_ICLKDIV_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_ICLK_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_ICLK_0->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_ICLK_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK1X_90_0->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK1X_90_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLKDIV->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLKDIV" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLKDIV_0->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLKDIV_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK_0" |
| }, |
| "LIOI3.IOI_PHASER_TO_IO_OCLK_0->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.029", |
| "0.032", |
| "0.085", |
| "0.092" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_PHASER_TO_IO_OCLK_0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO0->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO0" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO1->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO1" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO2->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO2" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC0_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLK": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLK", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_ILOGIC1_CLKB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_CLKB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLKM_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLKM_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OCLK_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OCLK_1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC0_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIV": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIV", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>IOI_OLOGIC1_CLKDIVFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_CLKDIVFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC0_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_RCLK_FORIO3->>LIOI_OLOGIC1_CLKDIVF": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_CLKDIVF", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.079", |
| "0.083" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_RCLK_FORIO3" |
| }, |
| "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC0_TBYTEIN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC0_TBYTEIN", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_TBYTEIN" |
| }, |
| "LIOI3.IOI_TBYTEIN->>IOI_OLOGIC1_TBYTEIN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_OLOGIC1_TBYTEIN", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "IOI_TBYTEIN" |
| }, |
| "LIOI3.LIOI_I0->LIOI_IDELAY0_IDATAIN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_IDELAY0_IDATAIN", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_I0" |
| }, |
| "LIOI3.LIOI_I0->LIOI_ILOGIC0_D": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC0_D", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_I0" |
| }, |
| "LIOI3.LIOI_I1->LIOI_IDELAY1_IDATAIN": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_IDELAY1_IDATAIN", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_I1" |
| }, |
| "LIOI3.LIOI_I1->LIOI_ILOGIC1_D": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC1_D", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_I1" |
| }, |
| "LIOI3.LIOI_IBUF0->LIOI_I0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_I0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_IBUF0" |
| }, |
| "LIOI3.LIOI_IBUF1->LIOI_I1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_I1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_IBUF1" |
| }, |
| "LIOI3.LIOI_IDELAY0_DATAOUT->LIOI_ILOGIC0_DDLY": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC0_DDLY", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_IDELAY0_DATAOUT" |
| }, |
| "LIOI3.LIOI_IDELAY0_IDATAIN->>LIOI_IDELAY0_DATAOUT": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.243", |
| "0.305", |
| "0.755", |
| "0.815" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_IDELAY0_DATAOUT", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.243", |
| "0.305", |
| "0.755", |
| "0.815" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_IDELAY0_IDATAIN" |
| }, |
| "LIOI3.LIOI_IDELAY1_DATAOUT->LIOI_ILOGIC1_DDLY": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC1_DDLY", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_IDELAY1_DATAOUT" |
| }, |
| "LIOI3.LIOI_IDELAY1_IDATAIN->>LIOI_IDELAY1_DATAOUT": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.243", |
| "0.305", |
| "0.755", |
| "0.815" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_IDELAY1_DATAOUT", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.243", |
| "0.305", |
| "0.755", |
| "0.815" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_IDELAY1_IDATAIN" |
| }, |
| "LIOI3.LIOI_ILOGIC0_D->>IOI_ILOGIC0_O": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.047", |
| "0.054", |
| "0.112", |
| "0.129" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_O", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.047", |
| "0.054", |
| "0.112", |
| "0.129" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_ILOGIC0_D" |
| }, |
| "LIOI3.LIOI_ILOGIC0_DDLY->>IOI_ILOGIC0_O": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.047", |
| "0.055", |
| "0.120", |
| "0.138" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC0_O", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.047", |
| "0.055", |
| "0.120", |
| "0.138" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_ILOGIC0_DDLY" |
| }, |
| "LIOI3.LIOI_ILOGIC1_D->>IOI_ILOGIC1_O": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.047", |
| "0.054", |
| "0.112", |
| "0.129" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_O", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.047", |
| "0.054", |
| "0.112", |
| "0.129" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_ILOGIC1_D" |
| }, |
| "LIOI3.LIOI_ILOGIC1_DDLY->>IOI_ILOGIC1_O": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.047", |
| "0.055", |
| "0.120", |
| "0.138" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "IOI_ILOGIC1_O", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.047", |
| "0.055", |
| "0.120", |
| "0.138" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_ILOGIC1_DDLY" |
| }, |
| "LIOI3.LIOI_ISOUT10->LIOI_ISIN11": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ISIN11", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_ISOUT10" |
| }, |
| "LIOI3.LIOI_ISOUT20->LIOI_ISIN21": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ISIN21", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_ISOUT20" |
| }, |
| "LIOI3.LIOI_OLOGIC0_OFB->LIOI_ILOGIC0_OFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC0_OFB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC0_OFB" |
| }, |
| "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_O0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_O0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC0_OQ" |
| }, |
| "LIOI3.LIOI_OLOGIC0_OQ->>LIOI_OLOGIC0_OFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_OFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC0_OQ" |
| }, |
| "LIOI3.LIOI_OLOGIC0_TFB->LIOI_OLOGIC0_TFB_LOCAL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_TFB_LOCAL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC0_TFB" |
| }, |
| "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->IOI_LOGIC_OUTS2_1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS2_1", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" |
| }, |
| "LIOI3.LIOI_OLOGIC0_TFB_LOCAL->LIOI_ILOGIC0_TFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC0_TFB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC0_TFB_LOCAL" |
| }, |
| "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_OLOGIC0_TFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC0_TFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC0_TQ" |
| }, |
| "LIOI3.LIOI_OLOGIC0_TQ->>LIOI_T0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_T0", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC0_TQ" |
| }, |
| "LIOI3.LIOI_OLOGIC1_OFB->LIOI_ILOGIC1_OFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC1_OFB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC1_OFB" |
| }, |
| "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_O1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_O1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC1_OQ" |
| }, |
| "LIOI3.LIOI_OLOGIC1_OQ->>LIOI_OLOGIC1_OFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_OFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC1_OQ" |
| }, |
| "LIOI3.LIOI_OLOGIC1_TFB->LIOI_OLOGIC1_TFB_LOCAL": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_TFB_LOCAL", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC1_TFB" |
| }, |
| "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->IOI_LOGIC_OUTS2_0": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "IOI_LOGIC_OUTS2_0", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" |
| }, |
| "LIOI3.LIOI_OLOGIC1_TFB_LOCAL->LIOI_ILOGIC1_TFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_ILOGIC1_TFB", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OLOGIC1_TFB_LOCAL" |
| }, |
| "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_OLOGIC1_TFB": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_OLOGIC1_TFB", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "1", |
| "src_to_dst": { |
| "delay": [ |
| "0.055", |
| "0.063", |
| "0.165", |
| "0.190" |
| ], |
| "in_cap": null, |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC1_TQ" |
| }, |
| "LIOI3.LIOI_OLOGIC1_TQ->>LIOI_T1": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "dst_wire": "LIOI_T1", |
| "is_directional": "1", |
| "is_pass_transistor": 0, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "in_cap": "0.000", |
| "res": "0.0" |
| }, |
| "src_wire": "LIOI_OLOGIC1_TQ" |
| }, |
| "LIOI3.LIOI_OSOUT11->LIOI_OSIN10": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_OSIN10", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OSOUT11" |
| }, |
| "LIOI3.LIOI_OSOUT21->LIOI_OSIN20": { |
| "can_invert": "0", |
| "dst_to_src": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "dst_wire": "LIOI_OSIN20", |
| "is_directional": "1", |
| "is_pass_transistor": 1, |
| "is_pseudo": "0", |
| "src_to_dst": { |
| "delay": null, |
| "in_cap": null, |
| "res": "0.000" |
| }, |
| "src_wire": "LIOI_OSOUT21" |
| } |
| }, |
| "sites": [ |
| { |
| "name": "X0Y0", |
| "prefix": "OLOGIC", |
| "site_pins": { |
| "CLK": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_CLK" |
| }, |
| "CLKB": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_CLKB" |
| }, |
| "CLKDIV": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_CLKDIV" |
| }, |
| "CLKDIVB": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_CLKDIVB" |
| }, |
| "CLKDIVF": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "LIOI_OLOGIC1_CLKDIVF" |
| }, |
| "CLKDIVFB": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_CLKDIVFB" |
| }, |
| "D1": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D1" |
| }, |
| "D2": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D2" |
| }, |
| "D3": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D3" |
| }, |
| "D4": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D4" |
| }, |
| "D5": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D5" |
| }, |
| "D6": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D6" |
| }, |
| "D7": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D7" |
| }, |
| "D8": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_D8" |
| }, |
| "IOCLKGLITCH": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "687.5", |
| "wire": "IOI_OLOGIC1_IOCLKGLITCH" |
| }, |
| "OCE": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_OCE" |
| }, |
| "OFB": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "687.5", |
| "wire": "LIOI_OLOGIC1_OFB" |
| }, |
| "OQ": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "687.5", |
| "wire": "LIOI_OLOGIC1_OQ" |
| }, |
| "REV": null, |
| "SHIFTIN1": null, |
| "SHIFTIN2": null, |
| "SHIFTOUT1": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "0.0", |
| "wire": "LIOI_OSOUT11" |
| }, |
| "SHIFTOUT2": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "0.0", |
| "wire": "LIOI_OSOUT21" |
| }, |
| "SR": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_SR" |
| }, |
| "T1": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_T1" |
| }, |
| "T2": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_T2" |
| }, |
| "T3": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_T3" |
| }, |
| "T4": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_T4" |
| }, |
| "TBYTEIN": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_TBYTEIN" |
| }, |
| "TBYTEOUT": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "687.5", |
| "wire": "IOI_OLOGIC1_TBYTEOUT" |
| }, |
| "TCE": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_OLOGIC1_TCE" |
| }, |
| "TFB": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "687.5", |
| "wire": "LIOI_OLOGIC1_TFB" |
| }, |
| "TQ": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "687.5", |
| "wire": "LIOI_OLOGIC1_TQ" |
| } |
| }, |
| "type": "OLOGICE3", |
| "x_coord": 0, |
| "y_coord": 0 |
| }, |
| { |
| "name": "X0Y0", |
| "prefix": "ILOGIC", |
| "site_pins": { |
| "BITSLIP": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_BITSLIP" |
| }, |
| "CE1": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_CE1" |
| }, |
| "CE2": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_CE2" |
| }, |
| "CLK": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_CLK" |
| }, |
| "CLKB": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_CLKB" |
| }, |
| "CLKDIV": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_CLKDIV" |
| }, |
| "CLKDIVP": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_CLKDIVP" |
| }, |
| "D": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "LIOI_ILOGIC1_D" |
| }, |
| "DDLY": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "LIOI_ILOGIC1_DDLY" |
| }, |
| "DYNCLKDIVPSEL": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_DYNCLKDIVPSEL" |
| }, |
| "DYNCLKDIVSEL": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_DYNCLKDIVSEL" |
| }, |
| "DYNCLKSEL": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_DYNCLKSEL" |
| }, |
| "O": { |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "res": "0.0", |
| "wire": "IOI_ILOGIC1_O" |
| }, |
| "OCLK": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_OCLK" |
| }, |
| "OCLKB": { |
| "cap": "0.000", |
| "delay": [ |
| "0.000", |
| "0.000", |
| "0.000", |
| "0.000" |
| ], |
| "wire": "IOI_ILOGIC1_OCLKB" |
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| "IOI_IMUX31_1": null, |
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| "IOI_IMUX33_0": null, |
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| "IOI_IMUX34_0": null, |
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| "IOI_IMUX40_0": null, |
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| "IOI_IMUX42_0": null, |
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| "IOI_IMUX43_0": null, |
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| "IOI_IMUX44_0": null, |
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| "IOI_MONITOR_P": null, |
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| "IOI_NW4END3_0": null, |
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| "IOI_ODELAY0_CNTVALUEIN2": null, |
| "IOI_ODELAY0_CNTVALUEIN3": null, |
| "IOI_ODELAY0_CNTVALUEIN4": null, |
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| "IOI_ODELAY0_CNTVALUEOUT3": null, |
| "IOI_ODELAY0_CNTVALUEOUT4": null, |
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| "IOI_ODELAY0_REGRST": null, |
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| "IOI_ODELAY1_CNTVALUEIN0": null, |
| "IOI_ODELAY1_CNTVALUEIN1": null, |
| "IOI_ODELAY1_CNTVALUEIN2": null, |
| "IOI_ODELAY1_CNTVALUEIN3": null, |
| "IOI_ODELAY1_CNTVALUEIN4": null, |
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| "IOI_ODELAY1_CNTVALUEOUT1": null, |
| "IOI_ODELAY1_CNTVALUEOUT2": null, |
| "IOI_ODELAY1_CNTVALUEOUT3": null, |
| "IOI_ODELAY1_CNTVALUEOUT4": null, |
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| "IOI_OLOGIC0_CLK": null, |
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| "IOI_OLOGIC0_D3": null, |
| "IOI_OLOGIC0_D4": null, |
| "IOI_OLOGIC0_D5": null, |
| "IOI_OLOGIC0_D6": null, |
| "IOI_OLOGIC0_D7": null, |
| "IOI_OLOGIC0_D8": null, |
| "IOI_OLOGIC0_IOCLKGLITCH": null, |
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| "IOI_OLOGIC0_REV": null, |
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| "IOI_OLOGIC0_T1": null, |
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| "IOI_OLOGIC0_T3": null, |
| "IOI_OLOGIC0_T4": null, |
| "IOI_OLOGIC0_TBYTEIN": null, |
| "IOI_OLOGIC0_TBYTEOUT": null, |
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| "IOI_PHASER_TO_IO_ICLK_0": null, |
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| "IOI_RCLK_FORIO1": null, |
| "IOI_RCLK_FORIO2": null, |
| "IOI_RCLK_FORIO3": null, |
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| "IOI_SE4C2_1": null, |
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| "IOI_SW4END1_1": null, |
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| "IOI_SW4END2_1": null, |
| "IOI_SW4END3_0": null, |
| "IOI_SW4END3_1": null, |
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| "IOI_WL1END0_1": null, |
| "IOI_WL1END1_0": null, |
| "IOI_WL1END1_1": null, |
| "IOI_WL1END2_0": null, |
| "IOI_WL1END2_1": null, |
| "IOI_WL1END3_0": null, |
| "IOI_WL1END3_1": null, |
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| "IOI_WR1END0_1": null, |
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| "IOI_WR1END1_1": null, |
| "IOI_WR1END2_0": null, |
| "IOI_WR1END2_1": null, |
| "IOI_WR1END3_0": null, |
| "IOI_WR1END3_1": null, |
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| "IOI_WW2A1_0": null, |
| "IOI_WW2A1_1": null, |
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| "IOI_WW2A3_0": null, |
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| "IOI_WW2END0_0": null, |
| "IOI_WW2END0_1": null, |
| "IOI_WW2END1_0": null, |
| "IOI_WW2END1_1": null, |
| "IOI_WW2END2_0": null, |
| "IOI_WW2END2_1": null, |
| "IOI_WW2END3_0": null, |
| "IOI_WW2END3_1": null, |
| "IOI_WW4A0_0": null, |
| "IOI_WW4A0_1": null, |
| "IOI_WW4A1_0": null, |
| "IOI_WW4A1_1": null, |
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| "IOI_WW4A2_1": null, |
| "IOI_WW4A3_0": null, |
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| "IOI_WW4B1_1": null, |
| "IOI_WW4B2_0": null, |
| "IOI_WW4B2_1": null, |
| "IOI_WW4B3_0": null, |
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| "IOI_WW4C1_1": null, |
| "IOI_WW4C2_0": null, |
| "IOI_WW4C2_1": null, |
| "IOI_WW4C3_0": null, |
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| "IOI_WW4END0_0": null, |
| "IOI_WW4END0_1": null, |
| "IOI_WW4END1_0": null, |
| "IOI_WW4END1_1": null, |
| "IOI_WW4END2_0": null, |
| "IOI_WW4END2_1": null, |
| "IOI_WW4END3_0": null, |
| "IOI_WW4END3_1": null, |
| "LIOI3_IDELAY0_IFDLY0": null, |
| "LIOI3_IDELAY0_IFDLY1": null, |
| "LIOI3_IDELAY0_IFDLY2": null, |
| "LIOI3_IDELAY1_IFDLY0": null, |
| "LIOI3_IDELAY1_IFDLY1": null, |
| "LIOI3_IDELAY1_IFDLY2": null, |
| "LIOI_DCI_T_TERM0": null, |
| "LIOI_DCI_T_TERM1": null, |
| "LIOI_DIFF_TERM_INT_EN": null, |
| "LIOI_I0": null, |
| "LIOI_I1": null, |
| "LIOI_I2GCLK_BOT1": null, |
| "LIOI_I2GCLK_TOP0": null, |
| "LIOI_I2GCLK_TOP1": null, |
| "LIOI_IBUF0": null, |
| "LIOI_IBUF1": null, |
| "LIOI_IBUF_DISABLE0": null, |
| "LIOI_IBUF_DISABLE1": null, |
| "LIOI_IDELAY0_DATAOUT": null, |
| "LIOI_IDELAY0_IDATAIN": null, |
| "LIOI_IDELAY1_DATAOUT": null, |
| "LIOI_IDELAY1_IDATAIN": null, |
| "LIOI_ILOGIC0_D": null, |
| "LIOI_ILOGIC0_DDLY": null, |
| "LIOI_ILOGIC0_OFB": null, |
| "LIOI_ILOGIC0_TFB": null, |
| "LIOI_ILOGIC1_D": null, |
| "LIOI_ILOGIC1_DDLY": null, |
| "LIOI_ILOGIC1_OFB": null, |
| "LIOI_ILOGIC1_TFB": null, |
| "LIOI_ISIN10": null, |
| "LIOI_ISIN11": null, |
| "LIOI_ISIN20": null, |
| "LIOI_ISIN21": null, |
| "LIOI_ISOUT10": null, |
| "LIOI_ISOUT11": null, |
| "LIOI_ISOUT20": null, |
| "LIOI_ISOUT21": null, |
| "LIOI_KEEPER_INT_EN_0": null, |
| "LIOI_KEEPER_INT_EN_1": null, |
| "LIOI_O0": null, |
| "LIOI_O1": null, |
| "LIOI_ODELAY0_DATAOUT": null, |
| "LIOI_ODELAY0_ODATAIN": null, |
| "LIOI_ODELAY0_OFDLY0": null, |
| "LIOI_ODELAY0_OFDLY1": null, |
| "LIOI_ODELAY0_OFDLY2": null, |
| "LIOI_ODELAY1_DATAOUT": null, |
| "LIOI_ODELAY1_ODATAIN": null, |
| "LIOI_ODELAY1_OFDLY0": null, |
| "LIOI_ODELAY1_OFDLY1": null, |
| "LIOI_ODELAY1_OFDLY2": null, |
| "LIOI_OLOGIC0_CLKDIVF": null, |
| "LIOI_OLOGIC0_OFB": null, |
| "LIOI_OLOGIC0_OQ": null, |
| "LIOI_OLOGIC0_TFB": null, |
| "LIOI_OLOGIC0_TFB_LOCAL": null, |
| "LIOI_OLOGIC0_TQ": null, |
| "LIOI_OLOGIC1_CLKDIVF": null, |
| "LIOI_OLOGIC1_OFB": null, |
| "LIOI_OLOGIC1_OQ": null, |
| "LIOI_OLOGIC1_TFB": null, |
| "LIOI_OLOGIC1_TFB_LOCAL": null, |
| "LIOI_OLOGIC1_TQ": null, |
| "LIOI_OSIN10": null, |
| "LIOI_OSIN11": null, |
| "LIOI_OSIN20": null, |
| "LIOI_OSIN21": null, |
| "LIOI_OSOUT10": null, |
| "LIOI_OSOUT11": null, |
| "LIOI_OSOUT20": null, |
| "LIOI_OSOUT21": null, |
| "LIOI_PD_INT_EN_0": null, |
| "LIOI_PD_INT_EN_1": null, |
| "LIOI_PU_INT_EN_0": null, |
| "LIOI_PU_INT_EN_1": null, |
| "LIOI_T0": null, |
| "LIOI_T1": null |
| } |
| } |
