zynq7/ppips_cmt_top_l_upper_t.db

CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLK_TOIOI.CMT_PLL_PHASER_IN_D_ICLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_ICLKDIV_TOIOI.CMT_PLL_PHASER_IN_D_ICLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLKDIV_TOIOI.CMT_PLL_PHASER_OUT_D_OCLKDIV always
CMT_TOP_L_UPPER_T.CMT_PHASER_D_OCLK90_TOIOI.CMT_PLL_PHASER_OUT_D_OCLK1X_90 always
CMT_TOP_L_UPPER_T.CMT_PLL_PHYCTRL_SYNC_BB_UP.CMT_PLL_PHYCTRL_SYNC_BB_DN always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_0.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_1.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_2.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_3.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_4.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_5.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_6.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_7.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_8.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_9.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_10.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_11.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLK_12.CMT_PHASER_D_ICLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_0.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_1.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_2.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_3.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_4.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_5.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_6.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_7.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_8.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_9.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_10.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_11.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_ICLKDIV_12.CMT_PHASER_D_ICLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_L_CLKFBOUT2IN.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_FREQ_BB3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL4.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT4 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL5.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT5 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL6.CMT_TOP_R_UPPER_T_PLLE2_CLKFBOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_CLKPLL7.CMT_TOP_R_UPPER_T_PLLE2_TMUXOUT always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_FB_INT.CMT_TOP_CLK0_1 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN1_INT.CMT_TOP_CLK1_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_L_UPPER_T_PLLE2_CLK_IN2_INT.CMT_TOP_CLK0_0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_7.CMT_PLL_PHASERD_DQSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B0_12.CMT_TOP_R_UPPER_T_PLLE2_DO13 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B2_12.CMT_TOP_R_UPPER_T_PLLE2_DO5 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_7.CMT_PLL_PHASERD_DQSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B5_12.CMT_TOP_R_UPPER_T_PLLE2_DO9 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B7_12.CMT_TOP_R_UPPER_T_PLLE2_DO1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B8_12.CMT_TOP_R_UPPER_T_PLLE2_DO15 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B10_12.CMT_TOP_R_UPPER_T_PLLE2_DO7 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B13_12.CMT_TOP_R_UPPER_T_PLLE2_DO11 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_6.CMT_PLL_PHASERD_DTSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B14_7.CMT_PLL_PHASERD_CTSBUS0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B15_12.CMT_TOP_R_UPPER_T_PLLE2_DO3 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_11.CMT_TOP_R_UPPER_T_PLLE2_DRDY always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B16_12.CMT_TOP_R_UPPER_T_PLLE2_DO6 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B17_12.CMT_TOP_R_UPPER_T_PLLE2_DO0 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B18_12.CMT_TOP_R_UPPER_T_PLLE2_DO14 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B19_12.CMT_TOP_R_UPPER_T_PLLE2_DO8 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B20_12.CMT_TOP_R_UPPER_T_PLLE2_DO4 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_11.CMT_TOP_R_UPPER_T_PLLE2_LOCKED always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B21_12.CMT_TOP_R_UPPER_T_PLLE2_DO2 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B22_12.CMT_TOP_R_UPPER_T_PLLE2_DO12 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_6.CMT_PLL_PHASERD_DTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_7.CMT_PLL_PHASERD_CTSBUS1 always
CMT_TOP_L_UPPER_T.CMT_TOP_LOGIC_OUTS_L_B23_12.CMT_TOP_R_UPPER_T_PLLE2_DO10 always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_0.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_1.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_2.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_3.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_4.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_5.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_6.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_7.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_8.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_9.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_10.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_11.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK_12.CMT_PHASER_D_OCLK_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLK1X_90_7.CMT_PHASER_D_OCLK90_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_0.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_1.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_2.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_3.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_4.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_5.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_6.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_7.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_8.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_9.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_10.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_11.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_OCLKDIV_12.CMT_PHASER_D_OCLKDIV_TOIOI always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_CLKINSEL.CMT_TOP_IMUX47_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DCLK.CMT_TOP_CLK0_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DEN.CMT_TOP_IMUX1_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DWE.CMT_TOP_IMUX2_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_PWRDWN.CMT_TOP_IMUX0_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_RST.CMT_TOP_IMUX13_10 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR0.CMT_TOP_IMUX47_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR1.CMT_TOP_IMUX15_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR2.CMT_TOP_IMUX22_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR3.CMT_TOP_IMUX13_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR4.CMT_TOP_IMUX44_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR5.CMT_TOP_IMUX35_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DADDR6.CMT_TOP_IMUX3_11 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI0.CMT_TOP_IMUX39_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI1.CMT_TOP_IMUX7_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI2.CMT_TOP_IMUX38_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI3.CMT_TOP_IMUX6_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI4.CMT_TOP_IMUX37_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI5.CMT_TOP_IMUX5_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI6.CMT_TOP_IMUX36_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI7.CMT_TOP_IMUX4_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI8.CMT_TOP_IMUX35_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI9.CMT_TOP_IMUX3_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI10.CMT_TOP_IMUX34_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI11.CMT_TOP_IMUX2_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI12.CMT_TOP_IMUX33_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI13.CMT_TOP_IMUX1_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI14.CMT_TOP_IMUX32_12 always
CMT_TOP_L_UPPER_T.CMT_TOP_R_UPPER_T_PLLE2_DI15.CMT_TOP_IMUX0_12 always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS0.PLL_CLK_FREQ_BB0_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS1.PLL_CLK_FREQ_BB1_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS2.PLL_CLK_FREQ_BB2_NS always
CMT_TOP_L_UPPER_T.PLL_CLK_FREQ_BB_BUFOUT_NS3.PLL_CLK_FREQ_BB3_NS always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_0.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT0 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_1.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT1 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_2.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT2 always
CMT_TOP_L_UPPER_T.PLLOUT_CLK_FREQ_BB_3.CMT_TOP_R_UPPER_T_PLLE2_CLKOUT3 always