Sign in
foss-fpga-tools
/
prjxray
/
0f67fcf1d272b4a79d9b261178af1ee5cd847099
/
.
/
minitests
/
clkbuf
/
top.v
blob: 29984caef9e30e4102757820ea2f39d6a30b10e8 [
file
]
module
top
(
input c
,
d
,
output q
);
(*
LOC
=
"SLICE_X16Y100"
,
BEL
=
"AFF"
,
DONT_TOUCH
*)
FDRE ff
(
.
C
(
c
),
.
CE
(
1
'b1),
.R(1'
b0
),
.
D
(
d
),
.
Q
(
q
)
);
endmodule