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foss-fpga-tools/prjxray/3cc35bb3bbb7a20cb8a7dd417b45fb0b0d263ce9/./minitests/litex/min_ddr/arty/src.yosys
tree: 0e61baf053cc1323126a93260880f751c82328f5 [path history] [tgz]
  1. mem.init ⇨ ../verilog/mem.init
  2. mem_1.init ⇨ ../verilog/mem_1.init
  3. Makefile
  4. missing_bit_report.py
  5. synth.ys
  6. top.tcl
  7. top.xdc