Added forced routing of MMCM.CLKINn signals through HCLK tiles to remove bit aliasing

Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

fuzzers/031-cmt-mmcm/generate.tcl

diff --git a/fuzzers/031-cmt-mmcm/generate.tcl b/fuzzers/031-cmt-mmcm/generate.tcl
index a391442..118660d 100644
--- a/fuzzers/031-cmt-mmcm/generate.tcl
+++ b/fuzzers/031-cmt-mmcm/generate.tcl
@@ -21,7 +21,7 @@
         # Parse the line
         set fields [split $line " "]
         set net_name [lindex $fields 0]
-        set wire_name [lindex $fields 1]
+        set wire_names [lrange $fields 1 end]
 
         # Check if that net exist
         if {[get_nets $net_name] eq ""} {
@@ -30,7 +30,7 @@
         }
 
         # Make the route
-        set status [route_via $net_name [list $wire_name] 0]
+        set status [route_via $net_name $wire_names 0]
 
         # Failure, skip manual routing of this net
         if { $status != 1 } {

fuzzers/031-cmt-mmcm/top.py

diff --git a/fuzzers/031-cmt-mmcm/top.py b/fuzzers/031-cmt-mmcm/top.py
index b88d464..3d86654 100644
--- a/fuzzers/031-cmt-mmcm/top.py
+++ b/fuzzers/031-cmt-mmcm/top.py
@@ -17,6 +17,20 @@
 import json
 
 
+def find_hclk_ref_wires_for_mmcm(grid, loc):
+    tilename = grid.tilename_at_loc((loc[0], loc[1] - 17))
+    gridinfo = grid.gridinfo_at_tilename(tilename)
+
+    assert gridinfo.tile_type in ['HCLK_CMT_L', 'HCLK_CMT']
+
+    # HCLK_CMT_MUX_OUT_FREQ_REF[0-3]
+    wires = []
+    for idx in range(4):
+        wires.append('{}/HCLK_CMT_MUX_OUT_FREQ_REF{}'.format(tilename, idx))
+
+    return wires
+
+
 def gen_sites():
     db = Database(util.get_db_root(), util.get_part())
     grid = db.grid()
@@ -28,7 +42,8 @@
 
         for site_name, site_type in gridinfo.sites.items():
             if site_type in ['MMCME2_ADV']:
-                yield tile_name, tile_type, site_name
+                hclk_wires = find_hclk_ref_wires_for_mmcm(grid, loc)
+                yield tile_name, tile_type, site_name, hclk_wires
 
 
 def gen_true_false(p):
@@ -60,11 +75,8 @@
     LUT1 dummy();
 """.format(N=max_sites - 1))
 
-    for i, (
-            tile_name,
-            tile_type,
-            site,
-    ) in enumerate(sorted(gen_sites())):
+    for i, (tile_name, tile_type, site,
+            hclk_wires) in enumerate(sorted(gen_sites())):
         params = {
             "site":
             site,
@@ -171,35 +183,30 @@
             params['clkfbin_conn'] = random.choice(
                 ("", "clkfb[{}]".format(i), "clkfbout_mult_BUFG_" + site))
 
-        params['clkin1_route'] = random.choice(
-            (
-                "{}_CLKIN1",
-                "{}_FREQ_BB0",
-                "{}_FREQ_BB1",
-                "{}_FREQ_BB2",
-                "{}_FREQ_BB3",
-                "{}_MMCME2_CLK_IN1_INT",
-            )).format(tile_type)
+        def get_clkin_wires(idx):
+            wires = [
+                "{tile}_CLKIN{idx}", "{tile}_FREQ_BB0", "{tile}_FREQ_BB1",
+                "{tile}_FREQ_BB2", "{tile}_FREQ_BB3", "{tile}_CLK_IN{idx}_INT"
+                "{tile}_CLK_IN{idx}_HCLK"
+            ]
+            return [
+                tile_name + "/" + w.format(tile=tile_type, idx=idx)
+                for w in wires
+            ]
 
-        params['clkin2_route'] = random.choice(
-            (
-                "{}_CLKIN2",
-                "{}_FREQ_BB0",
-                "{}_FREQ_BB1",
-                "{}_FREQ_BB2",
-                "{}_FREQ_BB3",
-                "{}_MMCME2_CLK_IN2_INT",
-            )).format(tile_type)
+        params['clkin1_route'] = random.choice(get_clkin_wires(1) + hclk_wires)
+        params['clkin2_route'] = random.choice(get_clkin_wires(2) + hclk_wires)
 
         params['clkfbin_route'] = random.choice(
             (
                 "{}_CLKFBOUT2IN",
-                "{}_UPPER_T_FREQ_BB0",
-                "{}_UPPER_T_FREQ_BB1",
-                "{}_UPPER_T_FREQ_BB2",
-                "{}_UPPER_T_FREQ_BB3",
-                "{}_UPPER_T_MMCME2_CLK_FB_INT",
-            )).format(tile_type.replace("_UPPER_T", ""))
+                "{}_FREQ_BB0",
+                "{}_FREQ_BB1",
+                "{}_FREQ_BB2",
+                "{}_FREQ_BB3",
+                "{}_CLK_IN3_INT",
+                "{}_CLK_IN3_HCLK",
+            )).format(tile_type)
 
         f.write('%s\n' % (json.dumps(params)))
 
@@ -208,13 +215,17 @@
             return net[:p] + '_IBUF' + net[p:]
 
         if params['clkin1_conn'] != "":
-            net = make_ibuf_net(params['clkin1_conn'])
-            wire = '{}/{}'.format(tile_name, params['clkin1_route'])
+            net = params['clkin1_conn']
+            if "[" in net and "]" in net:
+                net = make_ibuf_net(net)
+            wire = params['clkin1_route']
             routes_file.write('{} {}\n'.format(net, wire))
 
         if params['clkin2_conn'] != "":
-            net = make_ibuf_net(params['clkin2_conn'])
-            wire = '{}/{}'.format(tile_name, params['clkin2_route'])
+            net = params['clkin2_conn']
+            if "[" in net and "]" in net:
+                net = make_ibuf_net(net)
+            wire = params['clkin2_route']
             routes_file.write('{} {}\n'.format(net, wire))
 
         if params['clkfbin_conn'] != "" and\