gtp: fix inverted signals. Change ZINV feature to INV

Signed-off-by: Alessandro Comodi <acomodi@antmicro.com>

fuzzers/063-gtp-common-conf/generate.py

diff --git a/fuzzers/063-gtp-common-conf/generate.py b/fuzzers/063-gtp-common-conf/generate.py
index f7bb4d9..ddcd299 100644
--- a/fuzzers/063-gtp-common-conf/generate.py
+++ b/fuzzers/063-gtp-common-conf/generate.py
@@ -103,7 +103,7 @@
                             site, "%s[%u]" % (param, i), bitstr[i])
 
             for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
-                segmk.add_site_tag(site, "ZINV_" + param, 1 ^ params[param])
+                segmk.add_site_tag(site, "INV_" + param, params[param])
 
             for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
                           "BOTH_GTREFCLK_USED"]:

fuzzers/063-gtp-common-conf/top.py

diff --git a/fuzzers/063-gtp-common-conf/top.py b/fuzzers/063-gtp-common-conf/top.py
index d7fe50c..0122e36 100644
--- a/fuzzers/063-gtp-common-conf/top.py
+++ b/fuzzers/063-gtp-common-conf/top.py
@@ -159,6 +159,8 @@
                 verilog_attr += """
             .{}({}),""".format(param, value_str)
 
+            verilog_ports = ""
+
             for param in ["PLL0LOCKDETCLK", "PLL1LOCKDETCLK", "DRPCLK"]:
                 is_inverted = random.randint(0, 1)
 
@@ -166,12 +168,12 @@
 
                 verilog_attr += """
             .IS_{}_INVERTED({}),""".format(param, is_inverted)
+                verilog_ports += """
+            .{}({}),""".format(param, luts.get_next_output_net())
 
             verilog_attr = verilog_attr.rstrip(",")
             verilog_attr += "\n)"
 
-            verilog_ports = ""
-
             for param in ["GTREFCLK0_USED", "GTREFCLK1_USED",
                           "BOTH_GTREFCLK_USED"]:
                 params[param] = 0

fuzzers/064-gtp-channel-conf/generate.py

diff --git a/fuzzers/064-gtp-channel-conf/generate.py b/fuzzers/064-gtp-channel-conf/generate.py
index 19dd98e..5240aa0 100644
--- a/fuzzers/064-gtp-channel-conf/generate.py
+++ b/fuzzers/064-gtp-channel-conf/generate.py
@@ -113,8 +113,7 @@
                 for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
                               "SIGVALIDCLK", "RXUSRCLK", "RXUSRCLK2", "DRPCLK",
                               "DMONITORCLK", "CLKRSVD0", "CLKRSVD1"]:
-                    segmk.add_site_tag(
-                        site, "ZINV_" + param, 1 ^ params[param])
+                    segmk.add_site_tag(site, "INV_" + param, params[param])
 
     gtp_channel_x = [
         "GTP_CHANNEL_0",

fuzzers/064-gtp-channel-conf/top.py

diff --git a/fuzzers/064-gtp-channel-conf/top.py b/fuzzers/064-gtp-channel-conf/top.py
index 7e6dd64..ed09ca1 100644
--- a/fuzzers/064-gtp-channel-conf/top.py
+++ b/fuzzers/064-gtp-channel-conf/top.py
@@ -17,6 +17,7 @@
 random.seed(int(os.getenv("SEED"), 16))
 from prjxray import util
 from prjxray import verilog
+from prjxray.lut_maker import LutMaker
 from prjxray.db import Database
 
 INT = "INT"
@@ -76,6 +77,8 @@
 assign out = in;
 ''')
 
+    luts = LutMaker()
+
     primitives_list = list()
 
     for tile_name, tile_type, site_name, site_type in gen_sites(
@@ -122,6 +125,7 @@
                 verilog_attr += """
             .{}({}),""".format(param, value_str)
 
+            verilog_ports = ""
             for param in ["TXUSRCLK", "TXUSRCLK2", "TXPHDLYTSTCLK",
                           "SIGVALIDCLK", "RXUSRCLK", "RXUSRCLK2", "DRPCLK",
                           "DMONITORCLK", "CLKRSVD0", "CLKRSVD1"]:
@@ -131,19 +135,29 @@
 
                 verilog_attr += """
             .IS_{}_INVERTED({}),""".format(param, is_inverted)
+                verilog_ports += """
+            .{}({}),""".format(param, luts.get_next_output_net())
 
             verilog_attr = verilog_attr.rstrip(",")
             verilog_attr += "\n)"
 
             print("(* KEEP, DONT_TOUCH, LOC=\"{}\" *)".format(site_name))
             print(
-                """GTPE2_CHANNEL {} {} ();
-            """.format(verilog_attr, tile_type.lower()))
+                """GTPE2_CHANNEL {attrs} {site} (
+    {ports}
+);
+            """.format(
+                    attrs=verilog_attr,
+                    site=tile_type.lower(),
+                    ports=verilog_ports.rstrip(",")))
 
         params_list.append(params)
         params_dict["params"] = params_list
         primitives_list.append(params_dict)
 
+    for l in luts.create_wires_and_luts():
+        print(l)
+
     print("endmodule")
 
     with open('params.json', 'w') as f: