| # Loosely based on | |
| # ./utils/bits2fasm.py --db-root database/artix7 --canonical utils/test_data/ff_int/design.bits | |
| # FF as LDCE | |
| CLBLM_L_X10Y102.SLICEM_X0.AFFMUX.AX | |
| CLBLM_L_X10Y102.SLICEM_X0.AFF.ZINI | |
| CLBLM_L_X10Y102.SLICEM_X0.AFF.ZRST | |
| CLBLM_L_X10Y102.SLICEM_X0.CEUSEDMUX | |
| CLBLM_L_X10Y102.SLICEM_X0.SRUSEDMUX | |
| # Unused bits explicitly set to 0 | |
| CLBLM_L_X10Y102.SLICEM_X0.FFSYNC = 0 | |
| CLBLM_L_X10Y102.SLICEM_X0.LATCH = 0 | |
| # Note: a number of pseudo pips here | |
| # Omitted | |
| INT_L_X10Y102.BYP_ALT0.EE2END0 | |
| INT_L_X10Y102.BYP_ALT1.EL1END1 | |
| INT_L_X10Y102.CLK_L1.GCLK_L_B11_WEST | |
| INT_L_X10Y102.CTRL_L1.ER1END2 | |
| INT_L_X10Y102.FAN_ALT7.BYP_BOUNCE0 | |
| INT_L_X10Y102.WW2BEG0.LOGIC_OUTS_L4 | |
| HCLK_L_X31Y130.ENABLE_BUFFER.HCLK_CK_BUFHCLK8 | |
| HCLK_L_X31Y130.HCLK_LEAF_CLK_B_BOTL5.HCLK_CK_BUFHCLK8 | |