| `define N 100 | 
 |  | 
 | module top(input clk, stb, di, output do); | 
 | 	localparam integer DIN_N = 6; | 
 | 	localparam integer DOUT_N = `N; | 
 |  | 
 | 	reg [DIN_N-1:0] din; | 
 | 	wire [DOUT_N-1:0] dout; | 
 |  | 
 | 	reg [DIN_N-1:0] din_shr; | 
 | 	reg [DOUT_N-1:0] dout_shr; | 
 |  | 
 | 	always @(posedge clk) begin | 
 | 		din_shr <= {din_shr, di}; | 
 | 		dout_shr <= {dout_shr, din_shr[DIN_N-1]}; | 
 | 		if (stb) begin | 
 | 			din <= din_shr; | 
 | 			dout_shr <= dout; | 
 | 		end | 
 | 	end | 
 |  | 
 | 	assign do = dout_shr[DOUT_N-1]; | 
 |  | 
 | 	roi roi ( | 
 | 		.clk(clk), | 
 | 		.din(din), | 
 | 		.dout(dout) | 
 | 	); | 
 | endmodule | 
 |  | 
 | module roi(input clk, input [5:0] din, output [`N-1:0] dout); | 
 | 	genvar i; | 
 | 	generate | 
 | 		for (i = 0; i < `N; i = i+1) begin:is | 
 | 			LUT6 #( | 
 | 				.INIT(64'h8000_0000_0000_0001 + (i << 16)) | 
 | 			) lut ( | 
 | 				.I0(din[0]), | 
 | 				.I1(din[1]), | 
 | 				.I2(din[2]), | 
 | 				.I3(din[3]), | 
 | 				.I4(din[4]), | 
 | 				.I5(din[5]), | 
 | 				.O(dout[i]) | 
 | 			); | 
 | 		end | 
 | 	endgenerate | 
 | endmodule |