| `include "src/plle2_test.v" |
| |
| `default_nettype none |
| |
| // ============================================================================ |
| |
| module top |
| ( |
| input wire clk, |
| |
| input wire rx, |
| output wire tx, |
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| input wire [15:0] sw, |
| output wire [15:0] led |
| ); |
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| // ============================================================================ |
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| assign tx = rx; |
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| // ============================================================================ |
| // Clock & reset |
| reg [3:0] rst_sr; |
| |
| initial rst_sr <= 4'hF; |
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| always @(posedge clk) |
| if (sw[0]) |
| rst_sr <= 4'hF; |
| else |
| rst_sr <= rst_sr >> 1; |
| |
| wire CLK = clk; |
| wire RST = rst_sr[0]; |
| |
| // ============================================================================ |
| // The tester |
| |
| plle2_test plle2_test |
| ( |
| .CLK (CLK), |
| .RST (RST), |
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| .I_CLKINSEL (sw[1]), |
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| .O_LOCKED (led[15]), |
| .O_CNT (led[5:0]) |
| ); |
| |
| assign led [14] = |sw; |
| assign led [13:6] = 0; |
| |
| endmodule |
| |