Sign in
foss-fpga-tools
/
prjxray
/
5c0ef1cc973e3e8631edb8d812a766a8c8477a33
/
.
/
fuzzers
/
007-timing
/
routing-bels
/
top.v
blob: a234addd63c4c02e4d17278d0444c659b2e0170a [
file
]
module
top
(
input di
,
output
do
);
assign
do
=
di
;
endmodule
