Sign in
foss-fpga-tools
/
prjxray
/
6c6c528970d74df2f3f218f2e4d14b20ebcab92f
/
.
/
minitests
/
fixedpnr
/
top_fdce.v
blob: db0caffc13f756f10108b423a1cc7839ec2359f6 [
file
] [
log
] [
blame
]
module
top
(
input clk
,
ce
,
sr
,
d
,
output q
);
(*
LOC
=
"SLICE_X16Y100"
,
BEL
=
"AFF"
,
DONT_TOUCH
*)
FDCE ff
(
.
C
(
clk
),
.
CE
(
ce
),
.
CLR
(
sr
),
.
D
(
d
),
.
Q
(
q
)
);
endmodule