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foss-fpga-tools
/
prjxray
/
8325eb0aae2de2dd3b72c16b39cb4fbfc3f8fbbb
/
.
/
minitests
/
partial_reconfig_flow
/
roi_synthesize.tcl
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read_verilog
[
lindex
$
argv
0
]
synth_design -mode out_of_context -top roi -part
$::
env(XRAY_PART)
write_checkpoint -force
[
lindex
$
argv
1
]
