Merge pull request #1607 from antmicro/fix-gtp-pips
071-ppips: additional fix for GTP-related PPIPs
diff --git a/fuzzers/005-tilegrid/add_tdb.py b/fuzzers/005-tilegrid/add_tdb.py
index 9e3ab41..9c4c442 100644
--- a/fuzzers/005-tilegrid/add_tdb.py
+++ b/fuzzers/005-tilegrid/add_tdb.py
@@ -108,7 +108,7 @@
("hclk_cmt", 30, 10),
("hclk_ioi", 42, 1),
("pcie", 36, 101),
- ("gtp_common", 42, 101),
+ ("gtp_common", 32, 101),
("gtp_channel", 32, 22),
("clb_int", int_frames, int_words),
("iob_int", int_frames, int_words),
diff --git a/fuzzers/031-cmt-mmcm/write_mmcm_reg.py b/fuzzers/031-cmt-mmcm/write_mmcm_reg.py
index 8a8afe1..81fd570 100644
--- a/fuzzers/031-cmt-mmcm/write_mmcm_reg.py
+++ b/fuzzers/031-cmt-mmcm/write_mmcm_reg.py
@@ -171,7 +171,7 @@
Other features generated in fuzzing are passed through.
"""
- base_offset_register = 'CMT_LOWER_B.MMCME2.CLKOUT5_DIVIDE[1]'
+ base_offset_register = 'CMT_LOWER_B.MMCME2_ADV.CLKOUT5_DIVIDE[1]'
bit_offset = None
in_use = None
@@ -266,7 +266,7 @@
continue
print(
- 'CMT_LOWER_B.MMCME2.{}_{}_{}[{}] {}'.format(
+ 'CMT_LOWER_B.MMCME2_ADV.{}_{}_{}[{}] {}'.format(
register_name, layout, field, bit,
reg.next_bit()))
else:
@@ -279,7 +279,7 @@
continue
print(
- 'CMT_LOWER_B.MMCME2.{}[{}] {}'.format(
+ 'CMT_LOWER_B.MMCME2_ADV.{}[{}] {}'.format(
field, start_bit + bit, reg.next_bit()))
assert bit_count == 16
@@ -287,11 +287,11 @@
for bit in range(16):
if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']:
print(
- 'CMT_LOWER_B.MMCME2.{}_{}[{}] {}'.format(
+ 'CMT_LOWER_B.MMCME2_ADV.{}_{}[{}] {}'.format(
register_name, layout, bit, reg.next_bit()))
else:
print(
- 'CMT_LOWER_B.MMCME2.{}[{}] {}'.format(
+ 'CMT_LOWER_B.MMCME2_ADV.{}[{}] {}'.format(
register_name, bit, reg.next_bit()))
parts = in_use.split()
diff --git a/fuzzers/032-cmt-pll/write_pll_reg.py b/fuzzers/032-cmt-pll/write_pll_reg.py
index 749a84d..aeeae4a 100644
--- a/fuzzers/032-cmt-pll/write_pll_reg.py
+++ b/fuzzers/032-cmt-pll/write_pll_reg.py
@@ -151,7 +151,7 @@
Other features generated in fuzzing are passed through.
"""
- base_offset_register = 'CMT_UPPER_T.PLLE2.CLKOUT5_DIVIDE[1]'
+ base_offset_register = 'CMT_UPPER_T.PLLE2_ADV.CLKOUT5_DIVIDE[1]'
bit_offset = None
in_use = None
@@ -244,7 +244,7 @@
continue
print(
- 'CMT_UPPER_T.PLLE2.{}_{}_{}[{}] {}'.format(
+ 'CMT_UPPER_T.PLLE2_ADV.{}_{}_{}[{}] {}'.format(
register_name, layout, field, bit,
reg.next_bit()))
else:
@@ -257,7 +257,7 @@
continue
print(
- 'CMT_UPPER_T.PLLE2.{}[{}] {}'.format(
+ 'CMT_UPPER_T.PLLE2_ADV.{}[{}] {}'.format(
field, start_bit + bit, reg.next_bit()))
assert bit_count == 16
@@ -265,11 +265,11 @@
for bit in range(16):
if register_name != layout or layout in ['CLKOUT1', 'CLKOUT2']:
print(
- 'CMT_UPPER_T.PLLE2.{}_{}[{}] {}'.format(
+ 'CMT_UPPER_T.PLLE2_ADV.{}_{}[{}] {}'.format(
register_name, layout, bit, reg.next_bit()))
else:
print(
- 'CMT_UPPER_T.PLLE2.{}[{}] {}'.format(
+ 'CMT_UPPER_T.PLLE2_ADV.{}[{}] {}'.format(
register_name, bit, reg.next_bit()))
parts = in_use.split()
diff --git a/fuzzers/063-gtp-common-conf/generate.py b/fuzzers/063-gtp-common-conf/generate.py
index f7bb4d9..640e4b5 100644
--- a/fuzzers/063-gtp-common-conf/generate.py
+++ b/fuzzers/063-gtp-common-conf/generate.py
@@ -134,7 +134,7 @@
for i in range(2):
segmk.add_tile_tag(
- tile, "IBUFDS_GTE2.%s[%u]" % (param, i), bitstr[i])
+ tile, "IBUFDS_GTE2.CLKSWING_CFG[%u]" % (i), bitstr[i])
if tile_type.startswith("GTP_COMMON_MID"):
bitfilter = bitfilter_gtp_common_mid
diff --git a/prjxray/segmaker.py b/prjxray/segmaker.py
index 2c16282..4d6795f 100644
--- a/prjxray/segmaker.py
+++ b/prjxray/segmaker.py
@@ -283,7 +283,7 @@
segment["tags"][tag] = value
def add_site_tags():
- site_prefix = site.split('_')[0]
+ site_prefix = "_".join(site.split('_')[0:-1])
def name_slice():
'''
@@ -331,7 +331,7 @@
'IDELAY': name_y0y1,
'ILOGIC': name_y0y1,
'OLOGIC': name_y0y1,
- 'IBUFDS': name_y0y1,
+ 'IBUFDS_GTE2': name_y0y1,
}.get(site_prefix, name_default)()
self.verbose and print(
'site %s w/ %s prefix => tag %s' %
