Sign in
foss-fpga-tools
/
prjxray
/
8cdc7123546b8969d4b9e5db1cd25599682d8ee3
/
.
/
minitests
/
litex
/
uart_ddr
/
arty
/
src.yosys
/
synth.ys
blob: 3344c98db2bfa4db0cf9f216ea1717c5c5e8090c [
file
]
read_verilog
../
generated
/
top
.
v
synth_xilinx
-
edif top
.
edif