Sign in
foss-fpga-tools
/
prjxray
/
8ef904d40eb5e1a4cebe9f15e6080fa8e3a5029a
/
.
/
minitests
/
clb-configs
/
README
blob: dc2fac245f33671e4eea3d00c8cb4ef908102f93 [
file
] [
log
] [
blame
]
Some
small examples on manually placing elements within a CLB
.
Probably
only works
for
with
the
Artix
7
settings because contains
hardcoded slice addresses
.