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foss-fpga-tools
/
prjxray
/
95eb4f812b2f29ce74885abf8ecc69c72517d62f
/
.
/
fuzzers
/
007-timing
/
routing-bels
/
top.v
blob: a234addd63c4c02e4d17278d0444c659b2e0170a [
file
]
module
top
(
input di
,
output
do
);
assign
do
=
di
;
endmodule
