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foss-fpga-tools
/
prjxray
/
95eb4f812b2f29ce74885abf8ecc69c72517d62f
/
.
/
minitests
/
litex
/
uart_ddr
/
arty
/
src.yosys
/
synth.ys
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read_verilog
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generated
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synth_xilinx
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