Sign in
foss-fpga-tools
/
prjxray
/
a9dfd0b229a795bc7e4ab5b8405f9b1bb3525120
/
.
/
fuzzers
/
007-timing
/
routing-bels
/
top.v
blob: a234addd63c4c02e4d17278d0444c659b2e0170a [
file
] [
log
] [
blame
]
module
top
(
input di
,
output
do
);
assign
do
=
di
;
endmodule