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foss-fpga-tools
/
prjxray
/
cb4b0889907d58fd4fef9eaafbf3aa901abe2fd6
/
.
/
minitests
/
partial_reconfig_flow
/
harness_synthesize.tcl
blob: bde35810fd0d6e268533d07eec9de47ba3e2ff11 [
file
]
read_verilog harness
.
v
synth_design -top top -part
$::
env(XRAY_PART)
write_checkpoint -force harness_synth
.
dcp
