docs/db_dev_process/fuzzers/index.rst

Fuzzers
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Fuzzers are a set of tests which generate a design, feed it to Vivado, and look at the resulting bitstream to make some conclusion.
This is how the contents of the database are generated.

The general idea behind fuzzers is to pick some element in the device (say a block RAM or IOB) to target.
If you picked the IOB, you'd write a design that is implemented in a specific IOB.
Then you'd create a program that creates variations of the design (called specimens) that vary the design parameters, for example, changing the configuration of a single pin.

A lot of this program is TCL that runs inside Vivado to change the design parameters, because it is a bit faster to load in one Verilog model and use TCL to replicate it with varying inputs instead of having different models and loading them individually.

By looking at all the resulting specimens, you can correlate which bits in which frame correspond to a particular choice in the design.

Looking at the implemented design in Vivado with "Show Routing Resources" turned on is quite helpful in understanding what all choices exist.

Configurable Logic Blocks (CLB)
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   *clb*

Block RAM (BRAM)
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   *bram*

Input / Output (IOB)
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   *iob*

Clocking (CMT, PLL, BUFG, etc)
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   *clk*
   *cmt*

Programmable Interconnect Points (PIPs)
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   *pip*

Hard Block Fuzzers
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   *xadc*

Grid and Wire
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   tilegrid

All Fuzzers
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   *