Sign in
foss-fpga-tools
/
prjxray
/
ff20da130cc35224f9873acfa6a032fa9e2f9734
/
.
/
minitests
/
clb-configs
/
README
blob: dc2fac245f33671e4eea3d00c8cb4ef908102f93 [
file
] [
log
] [
blame
]
Some
small examples on manually placing elements within a CLB
.
Probably
only works
for
with
the
Artix
7
settings because contains
hardcoded slice addresses
.
