| # Copyright (C) 2017-2020 The Project X-Ray Authors |
| # |
| # Use of this source code is governed by a ISC-style |
| # license that can be found in the LICENSE file or at |
| # https://opensource.org/licenses/ISC |
| # |
| # SPDX-License-Identifier: ISC |
| create_project -force -part $::env(XRAY_PART) design design |
| |
| read_verilog top.v |
| synth_design -top top |
| |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports i] |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports o] |
| |
| create_pblock roi |
| resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" |
| |
| set_property CFGBVS VCCO [current_design] |
| set_property CONFIG_VOLTAGE 3.3 [current_design] |
| set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] |
| |
| place_design |
| route_design |
| |
| write_checkpoint -force design.dcp |
| write_bitstream -force design.bit |
| |
| source ../../utils/utils.tcl |
| |
| set fp [open "nodes_wires_list.txt" w] |
| foreach node [lsort [get_nodes -of_objects [pblock_tiles roi]]] { |
| set wires [lsort [get_wires -of_objects $node]] |
| if {$wires != $node} {puts $fp $wires} |
| } |
| close $fp |
