| create_project -force -part $::env(XRAY_PART) design design |
| |
| read_verilog ../top.v |
| synth_design -top top |
| |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_00) IOSTANDARD LVCMOS33" [get_ports a] |
| set_property -dict "PACKAGE_PIN $::env(XRAY_PIN_01) IOSTANDARD LVCMOS33" [get_ports y] |
| |
| create_pblock roi |
| resize_pblock [get_pblocks roi] -add "$::env(XRAY_ROI)" |
| |
| set_property CFGBVS VCCO [current_design] |
| set_property CONFIG_VOLTAGE 3.3 [current_design] |
| set_property BITSTREAM.GENERAL.PERFRAMECRC YES [current_design] |
| set_param tcl.collectionResultDisplayLimit 0 |
| |
| place_design |
| route_design |
| |
| write_checkpoint -force design.dcp |
| # write_bitstream -force design.bit |
| |
| source ../../../utils/utils.tcl |
| |
| set fp [open "nodewires.txt" w] |
| foreach node [get_nodes -of_objects [roi_tiles]] { |
| puts $fp "$node [get_wires -of_objects $node]" |
| } |
| close $fp |
