Sign in
foss-fpga-tools
/
prjxray
/
refs/heads/fix-runs-on
/
.
/
minitests
/
clb-configs
/
README
blob: dc2fac245f33671e4eea3d00c8cb4ef908102f93 [
file
] [
log
] [
blame
]
Clifford Wolf
04f37f2
2017-11-14 21:30:36 +0100
[
diff
] [
blame
]
1
2
Some
small examples on manually placing elements within a CLB
.
3
4
Probably
only works
for
with
the
Artix
7
settings because contains
5
hardcoded slice addresses
.
6
