Fixed docs for VTR examples Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/tests/test_v2x.py b/tests/test_v2x.py index 8c3c83c..bfefe66 100644 --- a/tests/test_v2x.py +++ b/tests/test_v2x.py
@@ -73,10 +73,10 @@ with open(newpbfile, 'w') as model: model.write(pbtypeout) - # Generate ff.pb_type.xml required by various tests - newpbfile = os.path.join(testdir, 'vtr/lutff-pair/ff/ff.pb_type.xml') + # Generate dff.pb_type.xml required by various tests + newpbfile = os.path.join(testdir, 'vtr/lutff-pair/dff/dff.pb_type.xml') pbtypeout = vlog_to_pbtype.vlog_to_pbtype( - [os.path.join(testdir, 'vtr/lutff-pair/ff/ff.sim.v')], + [os.path.join(testdir, 'vtr/lutff-pair/dff/dff.sim.v')], newpbfile, 'DFF') with open(newpbfile, 'w') as model:
diff --git a/tests/vtr/README.rst b/tests/vtr/README.rst new file mode 100644 index 0000000..fe1cb76 --- /dev/null +++ b/tests/vtr/README.rst
@@ -0,0 +1,9 @@ +.. Examples from the Verilog to Routing documentation / tutorials. + +Verilog to Routing +================== + +The following shows some examples taken from the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. + +.. toctree:: + primitives.rst
diff --git a/tests/vtr/dff/README.md b/tests/vtr/dff/README.md deleted file mode 100644 index c4c2fe3..0000000 --- a/tests/vtr/dff/README.md +++ /dev/null
@@ -1,28 +0,0 @@ -# Classical D-Flip-Flop test - -An example of the classical D-Flip-Flop. - -This is shown in `Figure 43 - DFF` of the -["Sequential block (no internal paths)"](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-no-internal-paths) -section in the -[Primitive Block Timing Modeling Tutorial](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#) -of the -[Verilog to Routing documentation](https://docs.verilogtorouting.org) -and reproduced below; - ->  -> *Fig. 43 DFF* - -## Clock associations inference - - - [ ] automatic inference is signal is associated with any clock and include the info in the model - - [ ] automatic clock detection (signals named `clk` are considered as clocks) - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - -## Timings - - - [ ] all the timings defined for wires with attributes should be included in `pb_type` XML
diff --git a/tests/vtr/dff/README.rst b/tests/vtr/dff/README.rst index 79ce265..0d0ee49 100644 --- a/tests/vtr/dff/README.rst +++ b/tests/vtr/dff/README.rst
@@ -6,29 +6,27 @@ .. |fig60| replace:: ``Figure 60 - DFF`` .. _fig60: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#sequential-block-no-internal-paths -.. image:: ../../../tests/vtr/dff/dff.svg +.. image:: dff.svg :alt: Figure 60 from Verilog to Routing Documentation *Fig. 60 - DFF* | -.. symbolator:: ../../../tests/vtr/dff/dff.sim.v - -.. verilog-diagram:: ../../../tests/vtr/dff/dff.sim.v - :type: netlistsvg - :module: DFF | -.. no-license:: ../../../tests/vtr/dff/dff.sim.v +.. no-license:: dff.sim.v :language: verilog - :caption: tests/vtr/dff/dff.sim.v + :caption: dff.sim.v -.. no-license:: ../../../tests/vtr/dff/golden.model.xml +.. no-license:: dff.model.xml :language: xml - :caption: tests/vtr/dff/golden.model.xml + :caption: dff.model.xml +.. no-license:: dff.pb_type.xml + :language: xml + :caption: dff.pb_type.xml Clock associations inference ****************************
diff --git a/tests/vtr/full-adder/README.md b/tests/vtr/full-adder/README.md deleted file mode 100644 index 08f302d..0000000 --- a/tests/vtr/full-adder/README.md +++ /dev/null
@@ -1,27 +0,0 @@ -# Full Adder Example - -An example of the classical combinational ["full adder"](https://en.wikipedia.org/wiki/Adder_(electronics)#Full_adder) circuit. - -This is shown in `Figure 41 - Full Adder` of the -["Combinational block"](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block) -section in the -[Primitive Block Timing Modeling Tutorial](https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#) -of the -[Verilog to Routing documentation](https://docs.verilogtorouting.org) -and reproduced below; - ->  -> *Fig. 41 Full Adder* - -## Detection of combinational connections - - - [ ] output has combinational connection with input - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - -## Timings - - - [ ] all the timings defined for wires with attributes should be included in `pb_type` XML
diff --git a/tests/vtr/full-adder/README.rst b/tests/vtr/full-adder/README.rst index 8087fb6..7f14b68 100644 --- a/tests/vtr/full-adder/README.rst +++ b/tests/vtr/full-adder/README.rst
@@ -6,32 +6,32 @@ .. |fig59| replace:: ``Figure 59 - Full Adder`` .. _fig59: https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#combinational-block -.. image:: ../../../tests/vtr/full-adder/full-adder.svg +.. image:: full-adder.svg :alt: Figure 59 from Verilog to Routing Documentation *Fig. 59 - Full Adder* | -.. symbolator:: ../../../tests/vtr/full-adder/adder.sim.v +.. symbolator:: adder.sim.v -.. verilog-diagram:: ../../../tests/vtr/full-adder/adder.sim.v +.. verilog-diagram:: adder.sim.v :type: netlistsvg :module: ADDER | -.. no-license:: ../../../tests/vtr/full-adder/adder.sim.v +.. no-license:: adder.sim.v :language: verilog - :caption: tests/vtr/full-adder/adder.sim.v + :caption: adder.sim.v -.. no-license:: ../../../tests/vtr/full-adder/golden.model.xml +.. no-license:: adder.model.xml :language: xml - :caption: tests/vtr/full-adder/golden.model.xml + :caption: adder.model.xml -.. no-license:: ../../../tests/vtr/full-adder/golden.pb_type.xml +.. no-license:: adder.pb_type.xml :language: xml - :caption: tests/vtr/full-adder/golden.pb_type.xml + :caption: adder.pb_type.xml Detection of combinational connections
diff --git a/tests/vtr/lutff-pair/README.md b/tests/vtr/lutff-pair/README.md deleted file mode 100644 index dbd5796..0000000 --- a/tests/vtr/lutff-pair/README.md +++ /dev/null
@@ -1,20 +0,0 @@ -# LUT with FlipFlop Example - -An example of the classical LUT with FlipFlop pair. - -This is shown in `Figure 28` of the -[Architecture Reference section of the Verilog to Routing Documentation](https://docs.verilogtorouting.org/en/latest/arch/reference) -and reproduced below; - ->  -> *Fig. 28 Pack Pattern Example.* - -## Blackbox detection - - - [ ] model of the leaf `pb_type` is generated - - [ ] leaf `pb_type` XML is generated - - [ ] all dependency models and `pb_type`s are included in the output files - -## Carry chain inference - - - [ ] `pack_pattern` inference - `pack_pattern`s defined on wires with `pack` attributes should be propagated to `pb_type` XMLs
diff --git a/tests/vtr/lutff-pair/README.rst b/tests/vtr/lutff-pair/README.rst index e6550a8..6454c41 100644 --- a/tests/vtr/lutff-pair/README.rst +++ b/tests/vtr/lutff-pair/README.rst
@@ -6,32 +6,32 @@ .. |fig31| replace:: ``Figure 31 - Pack Pattern Example`` .. _fig31: https://docs.verilogtorouting.org/en/latest/arch/reference/#id35 -.. image:: ../../../tests/vtr/lutff-pair/lutff-pair.png +.. image:: lutff-pair.png :alt: Figure 31 from Verilog to Routing Documentation *Fig. 31 - Pack Pattern Example* | -.. symbolator:: ../../../tests/vtr/lutff-pair/pair.sim.v +.. symbolator:: pair.sim.v -.. .. verilog-diagram:: ../../../tests/vtr/lutff-pair/pair.sim.v -.. :type: netlistsvg -.. :module: PAIR +.. verilog-diagram:: pair.sim.v + :type: netlistsvg + :module: PAIR | -.. no-license:: ../../../tests/vtr/lutff-pair/pair.sim.v +.. no-license:: pair.sim.v :language: verilog - :caption: tests/vtr/lutff-pair/pair.sim.v + :caption: pair.sim.v -.. no-license:: ../../../tests/vtr/lutff-pair/golden.model.xml +.. no-license:: pair.model.xml :language: xml - :caption: tests/vtr/lutff-pair/golden.model.xml + :caption: pair.model.xml -.. no-license:: ../../../tests/vtr/lutff-pair/golden.pb_type.xml +.. no-license:: pair.pb_type.xml :language: xml - :caption: tests/vtr/lutff-pair/golden.pb_type.xml + :caption: pair.pb_type.xml Blackbox detection ------------------
diff --git a/tests/vtr/lutff-pair/ff/ff.sim.v b/tests/vtr/lutff-pair/dff/dff.sim.v similarity index 100% rename from tests/vtr/lutff-pair/ff/ff.sim.v rename to tests/vtr/lutff-pair/dff/dff.sim.v
diff --git a/tests/vtr/lutff-pair/ff/golden.model.xml b/tests/vtr/lutff-pair/dff/golden.model.xml similarity index 100% rename from tests/vtr/lutff-pair/ff/golden.model.xml rename to tests/vtr/lutff-pair/dff/golden.model.xml
diff --git a/tests/vtr/lutff-pair/golden.model.xml b/tests/vtr/lutff-pair/golden.model.xml index 59092ef..1a85f1e 100644 --- a/tests/vtr/lutff-pair/golden.model.xml +++ b/tests/vtr/lutff-pair/golden.model.xml
@@ -1,5 +1,5 @@ <models xmlns:xi="http://www.w3.org/2001/XInclude"> - <xi:include href="ff/ff.model.xml" xpointer="xpointer(models/child::node())"/> + <xi:include href="dff/dff.model.xml" xpointer="xpointer(models/child::node())"/> <xi:include href="lut/lut4.model.xml" xpointer="xpointer(models/child::node())"/> <xi:include href="omux/omux.model.xml" xpointer="xpointer(models/child::node())"/> </models>
diff --git a/tests/vtr/lutff-pair/golden.pb_type.xml b/tests/vtr/lutff-pair/golden.pb_type.xml index ea403db..66bb865 100644 --- a/tests/vtr/lutff-pair/golden.pb_type.xml +++ b/tests/vtr/lutff-pair/golden.pb_type.xml
@@ -3,8 +3,8 @@ <clock name="CLK" num_pins="1"/> <input name="I" num_pins="4"/> <output name="O" num_pins="1"/> - <pb_type name="ff" num_pb="1"> - <xi:include href="ff/ff.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> + <pb_type name="dff" num_pb="1"> + <xi:include href="dff/dff.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> </pb_type> <pb_type name="lut" num_pb="1"> <xi:include href="lut/lut4.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/> @@ -12,14 +12,14 @@ <interconnect> <direct> <port name="CLK" type="input"/> - <port from="ff" name="CLK" type="output"/> + <port from="dff" name="CLK" type="output"/> </direct> <direct> <port from="lut" name="O" type="input"/> - <port from="ff" name="D" type="output"/> + <port from="dff" name="D" type="output"/> <pack_pattern name="LUT2FF" type="pack"> <port from="lut" name="O" type="input"/> - <port from="ff" name="D" type="output"/> + <port from="dff" name="D" type="output"/> </pack_pattern> </direct> <direct> @@ -39,7 +39,7 @@ <port from="lut" name="I[3]" type="output"/> </direct> <mux name="mux"> - <port from="ff" name="Q" type="input"> + <port from="dff" name="Q" type="input"> <metadata> <meta name="fasm_mux">F</meta> </metadata>
diff --git a/tests/vtr/lutff-pair/pair.sim.v b/tests/vtr/lutff-pair/pair.sim.v index 025bea2..7f7e8b5 100644 --- a/tests/vtr/lutff-pair/pair.sim.v +++ b/tests/vtr/lutff-pair/pair.sim.v
@@ -9,7 +9,7 @@ */ `include "lut/lut4.sim.v" -`include "ff/ff.sim.v" +`include "dff/dff.sim.v" `include "omux/omux.sim.v" module PAIR ( @@ -28,7 +28,7 @@ LUT4 lut (.I(I), .O(lut_out)); wire ff_out; - DFF ff (.CLK(CLK), .D(lut_out), .Q(ff_out)); + DFF dff (.CLK(CLK), .D(lut_out), .Q(ff_out)); parameter FF_BYPASS = "F"; OMUX #(.MODE(FF_BYPASS)) mux(.L(lut_out), .F(ff_out), .O(O));
diff --git a/tests/vtr/primitives.rst b/tests/vtr/primitives.rst new file mode 100644 index 0000000..20281f4 --- /dev/null +++ b/tests/vtr/primitives.rst
@@ -0,0 +1,11 @@ +Primitive Block Timing Modeling Tutorial +======================================== + +The following shows examples taken from the +`Primitive Block Timing Modeling Tutorial <https://docs.verilogtorouting.org/en/latest/tutorials/arch/timing_modeling/#>`_ +in the `Verilog to Routing documentation <https://docs.verilogtorouting.org>`_. + +.. toctree:: + dff/README.rst + full-adder/README.rst + lutff-pair/README.rst