tests/clocks/multiple_outputs_named_clk/golden.model.xml

<?xml version="1.0"?>
<models>
  <model name="BLOCK">
    <input_ports>
      <port name="a"/>
      <port name="b"/>
    </input_ports>
    <output_ports>
      <port name="o"/>
      <port name="rdclk" is_clock="1"/>
      <port name="wrclk" is_clock="1"/>
    </output_ports>
  </model>
</models>