Make mux_gen.py satisfy pep8

mux_gen.py is satisfying pep8 #13

Signed-off-by: Dhiraj240 <dhirajcoolssharma@gmail.com>

v2x/mux_gen.py

diff --git a/v2x/mux_gen.py b/v2x/mux_gen.py
index e06d0d3..41bea85 100755
--- a/v2x/mux_gen.py
+++ b/v2x/mux_gen.py
@@ -67,8 +67,7 @@
     '--name-inputs',
     type=str,
     default=None,
-    help=
-    "Comma deliminator list for the name of each input to the mux (implies --split-inputs)."
+    help="Comma deliminator list for the name of each input to the mux (implies --split-inputs)."
 )
 
 parser.add_argument(
@@ -87,8 +86,7 @@
     '--name-selects',
     type=str,
     default=None,
-    help=
-    "Comma deliminator list for the name of each select to the mux (implies --split-selects)."
+    help="Comma deliminator list for the name of each select to the mux (implies --split-selects)."
 )
 
 parser.add_argument(
@@ -96,8 +94,7 @@
     choices=[''.join(x) for x in itertools.permutations('ios')] +
     [''.join(x) for x in itertools.permutations('io')],
     default='iso',
-    help=
-    """Order of the arguments for the MUX. (i - Inputs, o - Output, s - Select)"""
+    help="""Order of the arguments for the MUX. (i - Inputs, o - Output, s - Select)"""
 )
 
 parser.add_argument(
@@ -229,7 +226,8 @@
                                            j], 1, '[%i]' % j, args.data_width)
                     for j in range(args.width))
             else:
-                # verilog range bounds are inclusive and convention is [<width-1>:0]
+                # verilog range bounds are inclusive and convention is
+                # [<width-1>:0]
                 port_names.append(
                     mux_lib.ModulePort(mux_lib.MuxPinType.INPUT,
                                        args.name_input, args.width,
@@ -241,7 +239,8 @@
                                        args.name_selects[j], 1, '[%i]' % j)
                     for j in range(args.width_bits))
             else:
-                # verilog range bounds are inclusive and convention is [<width-1>:0]
+                # verilog range bounds are inclusive and convention is
+                # [<width-1>:0]
                 assert args.name_select is not None
                 port_names.append(
                     mux_lib.ModulePort(mux_lib.MuxPinType.SELECT,