| /* | |
| * Copyright (C) 2020 The SymbiFlow Authors. | |
| * | |
| * Permission to use, copy, modify, and/or distribute this software for any | |
| * purpose with or without fee is hereby granted, provided that the above | |
| * copyright notice and this permission notice appear in all copies. | |
| * | |
| * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES | |
| * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF | |
| * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR | |
| * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES | |
| * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN | |
| * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF | |
| * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. | |
| */ | |
| /* | |
| * `input wire a` should be detected as a clock because it drives the flip | |
| * flop. However, it has the attribute CLOCK set to 0 which should force it | |
| * to be a regular input. | |
| */ | |
| module BLOCK(a, b, c); | |
| (* CLOCK=0 *) | |
| input wire a; | |
| input wire b; | |
| output wire c; | |
| reg r; | |
| always @ ( posedge a ) begin | |
| r <= b; | |
| end | |
| assign c = r; | |
| endmodule |