tests/clocks/input_attr_clock/README.rst

Manually set input as clock by setting the CLOCK attribute
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The following shows that ``input wire a`` is given the ``(* CLOCK *)`` attribute.

.. symbolator:: input_attr_clock.sim.v

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.. no-license:: input_attr_clock.sim.v
   :language: verilog
   :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v

As such, the ``is_clock`` attribute of the ``a`` port is set to 1.

.. literalinclude:: input_attr_clock.model.xml
   :language: xml
   :caption: input_attr_clock.model.xml