Added tests Signed-off-by: Maciej Kurc <mkurc@antmicro.com>

diff --git a/tests/internal_conn/child/child.model.xml b/tests/internal_conn/child/child.model.xml
new file mode 100644
index 0000000..90cfeb8
--- /dev/null
+++ b/tests/internal_conn/child/child.model.xml

@@ -0,0 +1,10 @@
+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <model name="CHILD">
+    <input_ports>
+      <port name="I"/>
+    </input_ports>
+    <output_ports>
+      <port name="O"/>
+    </output_ports>
+  </model>
+</models>

diff --git a/tests/internal_conn/child/child.pb_type.xml b/tests/internal_conn/child/child.pb_type.xml
new file mode 100644
index 0000000..0fda113
--- /dev/null
+++ b/tests/internal_conn/child/child.pb_type.xml

@@ -0,0 +1,6 @@
+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="CHILD">
+  <blif_model>.subckt CHILD</blif_model>
+  <input name="I" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+</pb_type>

diff --git a/tests/internal_conn/child/child.sim.v b/tests/internal_conn/child/child.sim.v
new file mode 100644
index 0000000..e6aee44
--- /dev/null
+++ b/tests/internal_conn/child/child.sim.v

@@ -0,0 +1,7 @@
+(* blackbox *)
+module CHILD(
+  input  wire I,
+  output wire O
+);
+
+endmodule

diff --git a/tests/internal_conn/golden.model.xml b/tests/internal_conn/golden.model.xml
new file mode 100644
index 0000000..9ca9fbd
--- /dev/null
+++ b/tests/internal_conn/golden.model.xml

@@ -0,0 +1,3 @@
+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <xi:include href="child/child.model.xml" xpointer="xpointer(models/child::node())"/>
+</models>

diff --git a/tests/internal_conn/golden.pb_type.xml b/tests/internal_conn/golden.pb_type.xml
new file mode 100644
index 0000000..646785c
--- /dev/null
+++ b/tests/internal_conn/golden.pb_type.xml

@@ -0,0 +1,16 @@
+<?xml version="1.0"?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" name="PARENT" num_pb="1">
+  <input name="I0" num_pins="1"/>
+  <input name="I1" num_pins="1"/>
+  <output name="O0" num_pins="1"/>
+  <output name="O1" num_pins="1"/>
+  <pb_type blif_model=".subckt CHILD" name="child" num_pb="1">
+    <input name="I" num_pins="1"/>
+    <output name="O" num_pins="1"/>
+  </pb_type>
+  <interconnect>
+    <direct input="child.O" name="PARENT-O0" output="PARENT.O0"/>
+    <direct input="PARENT.I1" name="PARENT-O1" output="PARENT.O1"/>
+    <direct input="PARENT.I0" name="child-I" output="child.I"/>
+  </interconnect>
+</pb_type>

diff --git a/tests/internal_conn/parent.sim.v b/tests/internal_conn/parent.sim.v
new file mode 100644
index 0000000..6f9f8df
--- /dev/null
+++ b/tests/internal_conn/parent.sim.v

@@ -0,0 +1,19 @@
+`include "./child/child.sim.v"
+
+module PARENT (
+  input  wire I0,
+  input  wire I1,
+  output wire O0,
+  output wire O1
+);
+
+  // A child cell was connected properly
+  CHILD child (
+  .I(I0),
+  .O(O0)
+  );
+
+  // Interconnect for this wasn't generated!
+  assign O1 = I1;
+
+endmodule

diff --git a/tests/modes/golden.model.xml b/tests/modes/golden.model.xml
new file mode 100644
index 0000000..36811d0
--- /dev/null
+++ b/tests/modes/golden.model.xml

@@ -0,0 +1,3 @@
+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <xi:include href="not/not.model.xml" xpointer="xpointer(models/child::node())"/>
+</models>

diff --git a/tests/modes/golden.pb_type.xml b/tests/modes/golden.pb_type.xml
new file mode 100644
index 0000000..d97e5ad
--- /dev/null
+++ b/tests/modes/golden.pb_type.xml

@@ -0,0 +1,43 @@
+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="INV">
+  <input name="I" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+  <mode name="PASSTHROUGH">
+    <interconnect>
+      <direct>
+        <port name="I" type="input"/>
+        <port name="O" type="output"/>
+      </direct>
+    </interconnect>
+  </mode>
+  <mode name="INVERT">
+    <pb_type num_pb="1" name="INVERT">
+      <input name="I" num_pins="1"/>
+      <output name="O" num_pins="1"/>
+      <pb_type num_pb="1" name="inverter">
+        <!--old_name NOT-->
+        <xi:include href="not/not.pb_type.xml" xpointer="xpointer(pb_type/child::node())"/>
+      </pb_type>
+      <interconnect>
+        <direct>
+          <port name="I" type="input"/>
+          <port name="I" type="output" from="inverter"/>
+        </direct>
+        <direct>
+          <port name="O" type="input" from="inverter"/>
+          <port name="O" type="output"/>
+        </direct>
+      </interconnect>
+    </pb_type>
+    <interconnect>
+      <direct>
+        <port name="I" type="input"/>
+        <port name="I" type="output" from="INVERT"/>
+      </direct>
+      <direct>
+        <port name="O" type="input" from="INVERT"/>
+        <port name="O" type="output"/>
+      </direct>
+    </interconnect>
+  </mode>
+</pb_type>

diff --git a/tests/modes/inv.sim.v b/tests/modes/inv.sim.v
new file mode 100644
index 0000000..1753c48
--- /dev/null
+++ b/tests/modes/inv.sim.v

@@ -0,0 +1,19 @@
+`include "./not/not.sim.v"
+
+(* MODES="PASSTHROUGH;INVERT" *)
+module INV(I, O);
+    input  wire I;
+    output wire O;
+
+    parameter MODE="";
+
+    // Passthrough (no inversion) mode
+    generate if (MODE == "PASSTHROUGH") begin
+        assign O = I;
+
+    // Inversion with placeable inverter
+    end else if (MODE == "INVERT") begin
+        NOT inverter(I, O);
+
+    end endgenerate
+endmodule

diff --git a/tests/modes/not/not.model.xml b/tests/modes/not/not.model.xml
new file mode 100644
index 0000000..e135dda
--- /dev/null
+++ b/tests/modes/not/not.model.xml

@@ -0,0 +1,10 @@
+<models xmlns:xi="http://www.w3.org/2001/XInclude">
+  <model name="NOT">
+    <input_ports>
+      <port name="I" combinational_sink_ports="O"/>
+    </input_ports>
+    <output_ports>
+      <port name="O"/>
+    </output_ports>
+  </model>
+</models>

diff --git a/tests/modes/not/not.pb_type.xml b/tests/modes/not/not.pb_type.xml
new file mode 100644
index 0000000..5a6798f
--- /dev/null
+++ b/tests/modes/not/not.pb_type.xml

@@ -0,0 +1,7 @@
+<?xml version='1.0' encoding='utf-8'?>
+<pb_type xmlns:xi="http://www.w3.org/2001/XInclude" num_pb="1" name="NOT">
+  <blif_model>.subckt NOT</blif_model>
+  <input name="I" num_pins="1"/>
+  <output name="O" num_pins="1"/>
+  <delay_constant in_port="I" out_port="O" max="1e-10"/>
+</pb_type>

diff --git a/tests/modes/not/not.sim.v b/tests/modes/not/not.sim.v
new file mode 100644
index 0000000..c4b4d1d
--- /dev/null
+++ b/tests/modes/not/not.sim.v

@@ -0,0 +1,10 @@
+(* whitebox *)
+module NOT (I, O);
+
+  input  wire I;
+  (* DELAY_CONST_I="1e-10" *)
+  output wire O;
+
+  assign O = ~I;
+
+endmodule