Added back "clocks" examples Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
diff --git a/tests/clocks/README.md b/tests/clocks/README.md deleted file mode 100644 index e969e29..0000000 --- a/tests/clocks/README.md +++ /dev/null
@@ -1,21 +0,0 @@ -# `clocks` tests - -This directory contains test for the clock detection functionality for the -`vlog_to_model.py` and `vlog_to_pbtype.py` tool. - - -## Detection of clock signals - - - [ ] Signal name matches the regexp `[a-z_]*clk[a-z0-9]*$` - - [ ] Manually set via the `(* CLOCK *)` or `(* CLOCK=1 *)` Verilog attribute. - - [ ] Manually cleared via the `(* CLOCK=0 *)` Verilog attribute. - - [ ] Signal drives synchronous logic (IE flipflop). - - [ ] Detection in recursive module includes. - -## Detection of clock association - - - [ ] Clock comes from synchronous logic - - [ ] Manually associated via `(* ASSOC_CLOCK="<clock signal"> *)` Verilog - attribute. - - [ ] Detection in recursive module includes. -
diff --git a/tests/clocks/README.rst b/tests/clocks/README.rst new file mode 100644 index 0000000..36c3f20 --- /dev/null +++ b/tests/clocks/README.rst
@@ -0,0 +1,12 @@ +.. Clock Example Tests + +Clock +===== + +There are various ways for an input or output port to be detected as a clock by v2x. Here are examples on ways to do so. + +.. toctree:: + autodetection.rst + manual_input.rst + manual_output.rst + multiple.rst
diff --git a/tests/clocks/autodetection.rst b/tests/clocks/autodetection.rst new file mode 100644 index 0000000..0de1715 --- /dev/null +++ b/tests/clocks/autodetection.rst
@@ -0,0 +1,7 @@ +Autodetection of clock from flipflop +==================================== + +.. toctree:: + dff_one_clock/README.rst + dff_comb_one_clock/README.rst + dff_two_clocks/README.rst
diff --git a/tests/clocks/dff_comb_one_clock/README.rst b/tests/clocks/dff_comb_one_clock/README.rst index d2df31e..1cb714d 100644 --- a/tests/clocks/dff_comb_one_clock/README.rst +++ b/tests/clocks/dff_comb_one_clock/README.rst
@@ -3,20 +3,20 @@ The following shows a combinational logic design driven by a clock. ``input wire a`` should be detected as a clock because it drives the flip flop. -.. symbolator:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v +.. symbolator:: dff_comb_one_clock.sim.v -.. verilog-diagram:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v +.. verilog-diagram:: dff_comb_one_clock.sim.v :type: netlistsvg :module: BLOCK | -.. no-license:: ../../../tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v +.. no-license:: dff_comb_one_clock.sim.v :language: verilog :caption: tests/clocks/dff_comb_one_clock/dff_comb_one_clock.sim.v The ``is_clock`` attribute of the ``a`` port is set to 1, and the ports ``b``, ``c`` and ``d`` have their ``clock`` attribute set to ``a``. -.. literalinclude:: ../../../tests/clocks/dff_comb_one_clock/golden.model.xml +.. literalinclude:: dff_comb_one_clock.model.xml :language: xml - :caption: tests/clocks/dff_comb_one_clock/golden.model.xml \ No newline at end of file + :caption: dff_comb_one_clock.model.xml
diff --git a/tests/clocks/dff_one_clock/README.rst b/tests/clocks/dff_one_clock/README.rst index 5301f49..bc7ad5a 100644 --- a/tests/clocks/dff_one_clock/README.rst +++ b/tests/clocks/dff_one_clock/README.rst
@@ -3,20 +3,20 @@ The following shows a simple D-flip flop driven by one clock. ``input wire a`` should be detected as a clock because it drives the flip flop. -.. symbolator:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v +.. symbolator:: dff_one_clock.sim.v -.. verilog-diagram:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v +.. verilog-diagram:: dff_one_clock.sim.v :type: netlistsvg :module: BLOCK | -.. no-license:: ../../../tests/clocks/dff_one_clock/dff_one_clock.sim.v +.. no-license:: dff_one_clock.sim.v :language: verilog :caption: tests/clocks/dff_one_clock/dff_one_clock.sim.v As you can see in the generated model, the ``is_clock`` attribute of the ``a`` port is set to 1, while the ``b`` and ``c`` ports have their ``clock`` attribute set to ``a``. -.. literalinclude:: ../../../tests/clocks/dff_one_clock/golden.model.xml +.. literalinclude:: dff_one_clock.model.xml :language: xml - :caption: tests/clocks/dff_one_clock/golden.model.xml + :caption: dff_one_clock.model.xml
diff --git a/tests/clocks/dff_two_clocks/README.rst b/tests/clocks/dff_two_clocks/README.rst index 12c9f9a..d58b384 100644 --- a/tests/clocks/dff_two_clocks/README.rst +++ b/tests/clocks/dff_two_clocks/README.rst
@@ -3,20 +3,20 @@ ``input wire c1`` and ``input wire c2`` should be detected as clocks because they drive the flip flop. -.. symbolator:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v +.. symbolator:: dff_two_clocks.sim.v -.. verilog-diagram:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v +.. verilog-diagram:: dff_two_clocks.sim.v :type: netlistsvg :module: BLOCK | -.. no-license:: ../../../tests/clocks/dff_two_clocks/dff_two_clocks.sim.v +.. no-license:: dff_two_clocks.sim.v :language: verilog :caption: tests/clocks/dff_two_clocks/dff_two_clocks.sim.v The ``is_clock`` attribute of the ``c1`` and ``c2`` ports are set to 1, and the ports ``a``, ``b``, ``c``, ``o1`` and ``o2`` have their ``clock`` attribute set to the respective clocks they are driven by. -.. literalinclude:: ../../../tests/clocks/dff_two_clocks/golden.model.xml +.. literalinclude:: dff_two_clocks.model.xml :language: xml - :caption: tests/clocks/dff_two_clocks/golden.model.xml + :caption: dff_two_clocks.model.xml
diff --git a/tests/clocks/input_attr_clock/README.rst b/tests/clocks/input_attr_clock/README.rst index c1117d2..dd8ab55 100644 --- a/tests/clocks/input_attr_clock/README.rst +++ b/tests/clocks/input_attr_clock/README.rst
@@ -3,16 +3,16 @@ The following shows that ``input wire a`` is given the ``(* CLOCK *)`` attribute. -.. symbolator:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v +.. symbolator:: input_attr_clock.sim.v | -.. no-license:: ../../../tests/clocks/input_attr_clock/input_attr_clock.sim.v +.. no-license:: input_attr_clock.sim.v :language: verilog :caption: tests/clocks/input_attr_clock/input_attr_clock.sim.v As such, the ``is_clock`` attribute of the ``a`` port is set to 1. -.. literalinclude:: ../../../tests/clocks/input_attr_clock/golden.model.xml +.. literalinclude:: input_attr_clock.model.xml :language: xml - :caption: tests/clocks/input_attr_clock/golden.model.xml \ No newline at end of file + :caption: input_attr_clock.model.xml
diff --git a/tests/clocks/input_attr_not_clock/README.rst b/tests/clocks/input_attr_not_clock/README.rst index 40a2f16..e3485fc 100644 --- a/tests/clocks/input_attr_not_clock/README.rst +++ b/tests/clocks/input_attr_not_clock/README.rst
@@ -3,24 +3,24 @@ ``input wire a`` should be detected as a clock because it drives the flip flop. However, it has the attribute CLOCK set to 0 which should force it to be a regular input. -.. symbolator:: ../../../tests/clocks/input_attr_not_clock/block.sim.v +.. symbolator:: block.sim.v -.. verilog-diagram:: ../../../tests/clocks/input_attr_not_clock/block.sim.v +.. verilog-diagram:: block.sim.v :type: netlistsvg :module: BLOCK | -.. no-license:: ../../../tests/clocks/input_attr_not_clock/block.sim.v +.. no-license:: block.sim.v :language: verilog :caption: tests/clocks/input_attr_not_clock/block.sim.v As such, the ``is_clock`` attribute of the ``a`` port is not set. -.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.model.xml +.. literalinclude:: block.model.xml :language: xml - :caption: tests/clocks/input_attr_not_clock/golden.model.xml + :caption: block.model.xml -.. literalinclude:: ../../../tests/clocks/input_attr_not_clock/golden.pb_type.xml +.. literalinclude:: block.pb_type.xml :language: xml - :caption: tests/clocks/input_attr_not_clock/golden.pb_type.xml \ No newline at end of file + :caption: block.pb_type.xml
diff --git a/tests/clocks/input_named_clk/README.rst b/tests/clocks/input_named_clk/README.rst index b0a8ee0..ac34c05 100644 --- a/tests/clocks/input_named_clk/README.rst +++ b/tests/clocks/input_named_clk/README.rst
@@ -3,16 +3,16 @@ An input wire can be set as a clock by assigning ``clk`` as its name. -.. symbolator:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v +.. symbolator:: input_named_clk.sim.v | -.. no-license:: ../../../tests/clocks/input_named_clk/input_named_clk.sim.v +.. no-license:: input_named_clk.sim.v :language: verilog :caption: tests/clocks/input_named_clk/input_named_clk.sim.v As such, the ``is_clock`` attribute of the ``clk`` port is set to 1, without needing to set anything else in the verilog code. -.. literalinclude:: ../../../tests/clocks/input_named_clk/golden.model.xml +.. literalinclude:: input_named_clk.model.xml :language: xml - :caption: tests/clocks/input_named_clk/golden.model.xml \ No newline at end of file + :caption: input_named_clk.model.xml
diff --git a/tests/clocks/input_named_regex/README.rst b/tests/clocks/input_named_regex/README.rst index 04b7eed..3aabd8a 100644 --- a/tests/clocks/input_named_regex/README.rst +++ b/tests/clocks/input_named_regex/README.rst
@@ -3,20 +3,20 @@ An input wire can be set as a clock by having ``clk`` in its name (case insensitive). -.. symbolator:: ../../../tests/clocks/input_named_regex/block.sim.v +.. symbolator:: block.sim.v | -.. no-license:: ../../../tests/clocks/input_named_regex/block.sim.v +.. no-license:: block.sim.v :language: verilog :caption: tests/clocks/input_named_regex/block.sim.v As such, the ``is_clock`` attribute of wires with a variation of ``clk`` in their name is set to 1. -.. literalinclude:: ../../../tests/clocks/input_named_regex/golden.model.xml +.. literalinclude:: block.model.xml :language: xml - :caption: tests/clocks/input_named_regex/golden.model.xml + :caption: block.model.xml -.. literalinclude:: ../../../tests/clocks/input_named_regex/golden.pb_type.xml +.. literalinclude:: block.pb_type.xml :language: xml - :caption: tests/clocks/input_named_regex/golden.pb_type.xml \ No newline at end of file + :caption: block.pb_type.xml
diff --git a/tests/clocks/manual_input.rst b/tests/clocks/manual_input.rst new file mode 100644 index 0000000..bf0fad9 --- /dev/null +++ b/tests/clocks/manual_input.rst
@@ -0,0 +1,8 @@ +Manually set inputs as clock +============================ + +.. toctree:: + input_attr_clock/README.rst + input_attr_not_clock/README.rst + input_named_clk/README.rst + input_named_regex/README.rst
diff --git a/tests/clocks/manual_output.rst b/tests/clocks/manual_output.rst new file mode 100644 index 0000000..c2bf9d5 --- /dev/null +++ b/tests/clocks/manual_output.rst
@@ -0,0 +1,6 @@ +Manually set outputs as clock +============================= + +.. toctree:: + output_attr_clock/README.rst + output_named_clk/README.rst
diff --git a/tests/clocks/multiple.rst b/tests/clocks/multiple.rst new file mode 100644 index 0000000..5f78d17 --- /dev/null +++ b/tests/clocks/multiple.rst
@@ -0,0 +1,6 @@ +Multiple clocks +=============== + +.. toctree:: + multiple_inputs_named_clk/README.rst + multiple_outputs_named_clk/README.rst
diff --git a/tests/clocks/multiple_inputs_named_clk/README.rst b/tests/clocks/multiple_inputs_named_clk/README.rst index 3e802b5..3b4e6fd 100644 --- a/tests/clocks/multiple_inputs_named_clk/README.rst +++ b/tests/clocks/multiple_inputs_named_clk/README.rst
@@ -3,16 +3,16 @@ ``input wire rdclk`` and ``input wire wrclk`` have ``clk`` in their names, hence are recognized as clock inputs by v2x. -.. symbolator:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v +.. symbolator:: multiple_inputs_named_clk.sim.v | -.. no-license:: ../../../tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v +.. no-license:: multiple_inputs_named_clk.sim.v :language: verilog :caption: tests/clocks/multiple_inputs_named_clk/multiple_inputs_named_clk.sim.v As such, the ``is_clock`` attribute of the ``rdclk`` and ``wrclk`` ports are set to 1. -.. literalinclude:: ../../../tests/clocks/multiple_inputs_named_clk/golden.model.xml +.. literalinclude:: multiple_inputs_named_clk.model.xml :language: xml - :caption: tests/clocks/multiple_inputs_named_clk/golden.model.xml \ No newline at end of file + :caption: multiple_inputs_named_clk.model.xml
diff --git a/tests/clocks/multiple_outputs_named_clk/README.rst b/tests/clocks/multiple_outputs_named_clk/README.rst index 6c2ef3c..cf18bae 100644 --- a/tests/clocks/multiple_outputs_named_clk/README.rst +++ b/tests/clocks/multiple_outputs_named_clk/README.rst
@@ -3,16 +3,16 @@ ``output wire rdclk`` and ``output wire wrclk`` have ``clk`` in their names, hence are recognized as clock inputs by v2x. -.. symbolator:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v +.. symbolator:: multiple_outputs_named_clk.sim.v | -.. no-license:: ../../../tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v +.. no-license:: multiple_outputs_named_clk.sim.v :language: verilog :caption: tests/clocks/multiple_outputs_named_clk/multiple_outputs_named_clk.sim.v As such, the ``is_clock`` attribute of the ``rdclk`` and ``wrclk`` ports are set to 1. -.. literalinclude:: ../../../tests/clocks/multiple_outputs_named_clk/golden.model.xml +.. literalinclude:: multiple_outputs_named_clk.model.xml :language: xml - :caption: tests/clocks/multiple_outputs_named_clk/golden.model.xml \ No newline at end of file + :caption: multiple_outputs_named_clk.model.xml
diff --git a/tests/clocks/output_attr_clock/README.rst b/tests/clocks/output_attr_clock/README.rst index 88ba93a..b928a77 100644 --- a/tests/clocks/output_attr_clock/README.rst +++ b/tests/clocks/output_attr_clock/README.rst
@@ -3,16 +3,16 @@ The following shows that ``output wire o`` is given the ``(* CLOCK *)`` attribute. -.. symbolator:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v +.. symbolator:: output_attr_clock.sim.v | -.. no-license:: ../../../tests/clocks/output_attr_clock/output_attr_clock.sim.v +.. no-license:: output_attr_clock.sim.v :language: verilog :caption: tests/clocks/output_attr_clock/output_attr_clock.sim.v As such, the ``is_clock`` attribute of the ``o`` port is set to 1. -.. literalinclude:: ../../../tests/clocks/output_attr_clock/golden.model.xml +.. literalinclude:: output_attr_clock.model.xml :language: xml - :caption: tests/clocks/output_attr_clock/golden.model.xml \ No newline at end of file + :caption: output_attr_clock.model.xml
diff --git a/tests/clocks/output_named_clk/README.rst b/tests/clocks/output_named_clk/README.rst index 5a43c72..a93e3de 100644 --- a/tests/clocks/output_named_clk/README.rst +++ b/tests/clocks/output_named_clk/README.rst
@@ -3,16 +3,16 @@ An output wire can be set as a clock by assigning ``clk`` as its name. -.. symbolator:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v +.. symbolator:: output_named_clk.sim.v | -.. no-license:: ../../../tests/clocks/output_named_clk/output_named_clk.sim.v +.. no-license:: output_named_clk.sim.v :language: verilog :caption: tests/clocks/output_named_clk/output_named_clk.sim.v As such, the ``is_clock`` attribute of the ``clk`` output port is set to 1. -.. literalinclude:: ../../../tests/clocks/output_named_clk/golden.model.xml +.. literalinclude:: output_named_clk.model.xml :language: xml - :caption: tests/clocks/output_named_clk/golden.model.xml \ No newline at end of file + :caption: output_named_clk.model.xml