tests: vlog: update dsp_modes test

Signed-off-by: Karol Gugala <kgugala@antmicro.com>

tests/dsp_modes/dsp_modes.sim.v

diff --git a/tests/dsp_modes/dsp_modes.sim.v b/tests/dsp_modes/dsp_modes.sim.v
index b845392..973c282 100644
--- a/tests/dsp_modes/dsp_modes.sim.v
+++ b/tests/dsp_modes/dsp_modes.sim.v
@@ -1,5 +1,8 @@
 `include "../dsp_combinational/dsp_combinational.sim.v"
 `include "../dsp_inout_registered/dsp_inout_registered.sim.v"
+`include "../dsp_in_registered/dsp_in_registered.sim.v"
+`include "../dsp_out_registered/dsp_out_registered.sim.v"
+`include "../dsp_partial_registered/dsp_partial_registered.sim.v"
 
 /* DSP Block with register on both the inputs and the output */
 (* MODES="REGISTERED_NONE; REGISTERED_IN; REGISTERED_OUT; REGISTERED_INOUT; REGISTERED_PARTIAL" *)
@@ -17,17 +20,15 @@
 	/* Register modes */
 	generate
 		if (MODE == "REGISTERED_NONE") begin
-			DSP_COMBINATIONAL dsp_int_comb (.clk(clk), .a(a), .b(b), .m(m), .out(out));
+			DSP_COMBINATIONAL dsp_int_comb (.a(a), .b(b), .m(m), .out(out));
 		end if (MODE == "REGISTERED_INOUT") begin
 			DSP_INOUT_REGISTERED dsp_int_regio (.clk(clk), .a(a), .b(b), .m(m), .out(out));
-/* FIXME: DSP_(IN|OUT)_REGISTERED is currently disabled.
 		end if (MODE == "REGISTERED_IN") begin
 			DSP_IN_REGISTERED dsp_int_regi (.clk(clk), .a(a), .b(b), .m(m), .out(out));
 		end if (MODE == "REGISTERED_OUT") begin
 			DSP_OUT_REGISTERED dsp_int_rego (.clk(clk), .a(a), .b(b), .m(m), .out(out));
 		end if (MODE == "REGISTERED_PARTIAL") begin
 			DSP_PARTIAL_REGISTERED dsp_int_part (.clk(clk), .a(a), .b(b), .m(m), .out(out));
-*/
 		end
 	endgenerate
 endmodule

tests/dsp_modes/golden.model.xml

diff --git a/tests/dsp_modes/golden.model.xml b/tests/dsp_modes/golden.model.xml
index 5efc49a..e69422e 100644
--- a/tests/dsp_modes/golden.model.xml
+++ b/tests/dsp_modes/golden.model.xml
@@ -1,15 +1,7 @@
 <models xmlns:xi="http://www.w3.org/2001/XInclude">
   <xi:include href="../dsp_combinational/dsp_combinational.model.xml" xpointer="xpointer(models/child::node())"/>
+  <xi:include href="../dsp_in_registered/dsp_in_registered.model.xml" xpointer="xpointer(models/child::node())"/>
   <xi:include href="../dsp_inout_registered/dsp_inout_registered.model.xml" xpointer="xpointer(models/child::node())"/>
-  <model name="DSP_MODES">
-    <input_ports>
-      <port clock="clk" combinational_sink_ports="out" name="a"/>
-      <port clock="clk" combinational_sink_ports="out" name="b"/>
-      <port is_clock="1" name="clk"/>
-      <port clock="clk" combinational_sink_ports="out" name="m"/>
-    </input_ports>
-    <output_ports>
-      <port clock="clk" name="out"/>
-    </output_ports>
-  </model>
+  <xi:include href="../dsp_out_registered/dsp_out_registered.model.xml" xpointer="xpointer(models/child::node())"/>
+  <xi:include href="../dsp_partial_registered/dsp_partial_registered.model.xml" xpointer="xpointer(models/child::node())"/>
 </models>