move main() to __main__ Signed-off-by: Karol Gugala <kgugala@antmicro.com>
diff --git a/v2x/__main__.py b/v2x/__main__.py index f038ba4..b54a175 100644 --- a/v2x/__main__.py +++ b/v2x/__main__.py
@@ -1,9 +1,63 @@ #!/usr/bin/env python3 -from .v2x import vlog_to_pbtype +from . import vlog_to_pbtype +from . import vlog_to_model +import argparse +import sys -def main(): - echo("main") +def main(args): + if args.mode == "pb_type": + vlog_to_pbtype.vlog_to_pbtype(args.infiles, args.outfile, args.top) + else: + vlog_to_model.vlog_to_model(args.infiles, args.includes, args.top, args.outfile) -if __name__ = '__main__': - main() +if __name__ == '__main__': + parser = argparse.ArgumentParser( + description="Verilog to XML" + ) + parser.add_argument( + 'infiles', + metavar='input.v', + type=str, + nargs='+', + help="""\ +One or more Verilog input files, that will be passed to Yosys internally. +They should be enough to generate a flattened representation of the model, +so that paths through the model can be determined. +""" + ) + parser.add_argument( + '--top', + help="""\ +Top level module, will usually be automatically determined from the file name +%.sim.v +""" + ) + parser.add_argument( + '--outfile', + '-o', + type=str, + default="output.xml", + help="""\ +Output filename, default 'output.xml' +""" + ) + parser.add_argument( + '--includes', + help="""\ +Comma separate list of include directories. +""", + default="" + ) + parser.add_argument( + '--mode', + type=str, + default='pb_type', + choices=['pb_type', 'model'], + help="""\ +Output file type, possible values are: pb_type and model. +Default value is pb_type +""" + ) + args = parser.parse_args() + sys.exit(main(args))
diff --git a/v2x/vlog_to_model.py b/v2x/vlog_to_model.py index 91fc0e0..993abe8 100755 --- a/v2x/vlog_to_model.py +++ b/v2x/vlog_to_model.py
@@ -205,36 +205,3 @@ f.close() print("Generated {} from {}".format(outfile, iname)) -if __name__ == "__main__": - - parser = argparse.ArgumentParser(description=__doc__.strip()) - parser.add_argument( - 'infiles', - metavar='input.v', - type=str, - nargs='+', - help="""\ - One or more Verilog input files, that will be passed to Yosys internally. - They should be enough to generate a flattened representation of the model, - so that paths through the model can be determined. - """ - ) - parser.add_argument( - '--top', - help="""\ - Top level module, will usually be automatically determined from the file name - %.sim.v - """ - ) - parser.add_argument( - '--includes', - help="""\ - Comma separate list of include directories. - """, - default="" - ) - parser.add_argument('-o', help="""\ - Output filename, default 'model.xml' - """) - - args = parser.parse_args()
diff --git a/v2x/vlog_to_pbtype.py b/v2x/vlog_to_pbtype.py index b43fd50..564d583 100755 --- a/v2x/vlog_to_pbtype.py +++ b/v2x/vlog_to_pbtype.py
@@ -797,39 +797,6 @@ return pb_type_xml - -parser = argparse.ArgumentParser( - description=__doc__.strip(), formatter_class=argparse.RawTextHelpFormatter -) -parser.add_argument( - 'infiles', - metavar='input.v', - type=str, - nargs='+', - help="""\ -One or more Verilog input files, that will be passed to Yosys internally. -They should be enough to generate a flattened representation of the model, -so that paths through the model can be determined. -""" -) -parser.add_argument( - '--top', - help="""\ -Top level module, will usually be automatically determined from the file name -%.sim.v -""" -) -parser.add_argument( - '--outfile', - '-o', - type=argparse.FileType('w'), - default="pb_type.xml", - help="""\ -Output filename, default 'model.xml' -""" -) - - def vlog_to_pbtype(infiles, outfile, top=None): iname = os.path.basename(infiles[0]) @@ -870,9 +837,3 @@ print("Generated {} from {}".format(outfile.name, iname)) outfile.close() - -if __name__ == "__main__": - import doctest - doctest.testmod() - args = parser.parse_args() - sys.exit(main(args))