| .. Examples from the Verilog to Routing documentation / tutorials. | |
| Verilog to Routing Examples | |
| =========================== | |
| Primitive Block Timing Modeling Tutorial | |
| ---------------------------------------- | |
| .. toctree:: | |
| vtr/fig28-lutff-pair.md | |
| vtr/fig41-full-adder.md | |
| vtr/fig42-dff.md |