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foss-fpga-tools
/
python-symbiflow-v2x
/
36a82f962cfaae15f7028e1e83c9b5a443493383
/
.
/
tests
/
vtr
/
lutff-pair
/
lut
/
lut4.sim.v
blob: caa640b4572f9f728fcd450def905d051bc62a46 [
file
]
(*
whitebox
*)
module
LUT4
(
I
,
O
);
input wire
[
3
:
0
]
I
;
(*
DELAY_MATRIX_I
=
"30e-12 20e-12 11e-12 3e-12"
*)
output wire O
;
localparam INIT
=
16
'h0000;
assign O = INIT[I];
endmodule